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riscv: Provide vector crypto implementation of AES-CBC mode.
[thirdparty/openssl.git] / crypto / arm64cpuid.pl
2022-05-03  Matt CaswellUpdate copyright year
2022-05-03  Daniel HuAcceleration of chacha20 on aarch64 by SVE
2022-04-29  yavtukPrefer .inst rather than .long for probe instructions...
2022-02-09  Tom Cosgroveaarch64: fix branch target indications in arm64cpuid...
2022-01-25  XiaokangQianOptimize AES-GCM for uarchs with unroll and new instruc...
2022-01-18  Daniel HuSM4 optimization for ARM by HW instruction
2022-01-14  fangming.fangSM3 acceleration with SM3 hardware instruction on aarch64
2021-12-16  Orr ToledanoAdd Arm Assembly (aarch64) support for RNG
2021-10-01  Russ Butleraarch64: support BTI and pointer authentication in...
2020-12-09  Fangming.FangRead MIDR_EL1 system register on aarch64
2020-04-23  Matt CaswellUpdate copyright year
2020-02-17  David BenjaminAlso check for errors in x86_64-xlate.pl.
2020-01-22  David BenjaminDo not silently truncate files on perlasm errors
2019-09-16  Richard LevitteUnify all assembler file generators
2018-12-06  Richard LevitteFollowing the license change, modify the boilerplates...
2018-06-03  Andy Polyakov{arm64|x86_64}cpuid.pl: add special 16-byte case to...
2018-02-13  Matt CaswellUpdate copyright year
2018-02-12  Andy Polyakovcrypto/armcap.c: detect hardware-assisted SHA512 support.
2016-05-19  Andy PolyakovAdd assembly CRYPTO_memcmp.
2016-05-16  Andy PolyakovARMv8 assembly pack: add OPENSSL_cleanse.
2016-04-20  Rich SalzCopyright consolidation: perl files
2015-01-23  Andy PolyakovAdd assembly support to ios64-cross.