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[thirdparty/gcc.git] / gcc / config / riscv / riscv.md

2019-06-27	Aaron Sawdey	builtins.c (get_memory_rtx): Fix comment.	blob \| commitdiff \| raw
2019-04-30	Andrew Waterman	RISC-V: Short-forward-branch opt for SiFive 7 series...	blob \| commitdiff \| raw \| diff to current
2019-04-27	Jim Wilson	RISC-V: Promode modes of constant loads for store insns.	blob \| commitdiff \| raw \| diff to current
2019-03-26	Andrew Waterman	RISC-V: Add sifive-7 pipeline description.	blob \| commitdiff \| raw \| diff to current
2019-01-01	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2018-10-05	Andrew Waterman	RISC-V: Fix -fsignaling-nans for glibc testsuite.	blob \| commitdiff \| raw \| diff to current
2018-09-26	Jim Wilson	RISC-V: Add missing negate patterns.	blob \| commitdiff \| raw \| diff to current
2018-08-29	Jim Wilson	Rewrite pic.md to improve medany and pic code size.	blob \| commitdiff \| raw \| diff to current
2018-07-03	Jim Wilson	RISC-V: Fix interrupt support for -g.	blob \| commitdiff \| raw \| diff to current
2018-06-30	Jim Wilson	RISC-V: Add patterns to convert AND mask to two shifts.	blob \| commitdiff \| raw \| diff to current
2018-06-06	Jim Wilson	RISC-V: Add interrupt attribute modes.	blob \| commitdiff \| raw \| diff to current
2018-06-04	Jim Wilson	RISC-V: Don't clobber retval when __builtin_eh_return...	blob \| commitdiff \| raw \| diff to current
2018-05-25	Jim Wilson	RISC-V: Add interrupt attribute support.	blob \| commitdiff \| raw \| diff to current
2018-05-16	Jim Wilson	RISC-V: Minor pattern name cleanup.	blob \| commitdiff \| raw \| diff to current
2018-04-02	Jim Wilson	RISC-V: Fix for combine bug with shift and AND operations.	blob \| commitdiff \| raw \| diff to current
2018-01-10	Kito Cheng	RISC-V: Add naked function support.	blob \| commitdiff \| raw \| diff to current
2018-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2018-01-02	Andrew Waterman	RISC-V: Fix for icache flush issue on multicore processors.	blob \| commitdiff \| raw \| diff to current
2017-11-29	Jim Wilson	Riscv patterns to optimize away some redundant zero...	blob \| commitdiff \| raw \| diff to current
2017-11-07	Andrew Waterman	RISC-V: Implement movmemsi	blob \| commitdiff \| raw \| diff to current
2017-11-05	Michael Clark	RISC-V: Emit "i" suffix for instructions with immediate...	blob \| commitdiff \| raw \| diff to current
2017-10-25	Palmer Dabbelt	RISC-V: Add Sign/Zero extend patterns for PIC loads	blob \| commitdiff \| raw \| diff to current
2017-09-15	Richard Sandiford	Turn TRULY_NOOP_TRUNCATION into a hook	blob \| commitdiff \| raw \| diff to current
2017-05-05	Kito Cheng	RISC-V: Unify indention in riscv.md	blob \| commitdiff \| raw \| diff to current
2017-02-06	Palmer Dabbelt	RISC-V Port: gcc	blob \| commitdiff \| raw \| diff to current

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