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[thirdparty/binutils-gdb.git] / sim / bfin / ChangeLog

2011-06-22	Mike Frysinger	sim: bfin: pass up result2/errcode with libgloss syscalls	blob \| commitdiff \| raw
2011-06-18	Mike Frysinger	sim: bfin: set ASTAT AV/AVS when shifting accumulators...	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: do not touch ASTAT[V] when shifting accumulators	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: do not extend accumulator in LSHIFT insns	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: tweak saturation handling with TFU/FU modes...	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: handle large shift values with accumulator...	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: handle odd shift values with shift insns	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: fix M_IH saturation size	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: handle V/VS saturation in dsp mac insns	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: handle the MM flag in M_IU/M_TFU modes with...	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: fix sign extension in dsp insns with MM...	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: fix dsp insns IH saturation/rounding behavior	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: fix inverted changelog entry	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: fix accumulator edge case saturation	blob \| commitdiff \| raw \| diff to current
2011-06-18	Mike Frysinger	sim: bfin: use freeargv for freeing argvs	blob \| commitdiff \| raw \| diff to current
2011-06-04	Mike Frysinger	sim: bfin: add support for glued SIC interrupt lines	blob \| commitdiff \| raw \| diff to current
2011-06-04	Mike Frysinger	sim: bfin: push SIC mappings to device tree	blob \| commitdiff \| raw \| diff to current
2011-06-03	Mike Frysinger	sim: bfin: dma: fix indentation	blob \| commitdiff \| raw \| diff to current
2011-05-26	Mike Frysinger	sim: bfin: switch to new syscall trace level	blob \| commitdiff \| raw \| diff to current
2011-05-25	Mike Frysinger	sim: bfin: move model data into machs.h	blob \| commitdiff \| raw \| diff to current
2011-05-25	Mike Frysinger	sim: bfin: add a performance monitor stub	blob \| commitdiff \| raw \| diff to current
2011-05-25	Mike Frysinger	sim: bfin: add bf526-0.2/bf54x-0.4 rom regions	blob \| commitdiff \| raw \| diff to current
2011-05-14	Mike Frysinger	sim: bfin: allow pushing of SP	blob \| commitdiff \| raw \| diff to current
2011-05-14	Mike Frysinger	sim: bfin: implement loop back support in the UARTs	blob \| commitdiff \| raw \| diff to current
2011-05-09	Mike Frysinger	sim: bfin: fix UART LSR read-only bit saturation	blob \| commitdiff \| raw \| diff to current
2011-04-27	Mike Frysinger	sim: bfin: constify dmac pmap arrays	blob \| commitdiff \| raw \| diff to current
2011-04-26	Mike Frysinger	sim: gpio: add output support	blob \| commitdiff \| raw \| diff to current
2011-04-26	Mike Frysinger	sim: gpio: update mask a/b signals better	blob \| commitdiff \| raw \| diff to current
2011-04-16	Mike Frysinger	sim: bfin: use store buffer with more 32bit insns	blob \| commitdiff \| raw \| diff to current
2011-04-15	Mike Frysinger	sim: bfin: handle implicit DISALGNEXCPT with video...	blob \| commitdiff \| raw \| diff to current
2011-04-11	Mike Frysinger	sim: bfin: respect the port level on signals to the SIC	blob \| commitdiff \| raw \| diff to current
2011-04-11	Mike Frysinger	sim: bfin: add missing GPIO pin 15	blob \| commitdiff \| raw \| diff to current
2011-04-01	Mike Frysinger	sim: bfin: add OTP output port	blob \| commitdiff \| raw \| diff to current
2011-03-29	Mike Frysinger	sim: bfin: regen configure to include new cfi device	blob \| commitdiff \| raw \| diff to current
2011-03-29	Mike Frysinger	sim: bfin: fix sign extension with 16bit acc add insns	blob \| commitdiff \| raw \| diff to current
2011-03-27	Mike Frysinger	sim: bfin: handle saturation with RND12 sub insns	blob \| commitdiff \| raw \| diff to current
2011-03-26	Mike Frysinger	sim: bfin: add missing VS set with add/sub insns	blob \| commitdiff \| raw \| diff to current
2011-03-25	Mike Frysinger	sim: bfin: add hw tracing to gpio/sic port events	blob \| commitdiff \| raw \| diff to current
2011-03-25	Mike Frysinger	sim: bfin: fix GPIO logic bugs when processing events	blob \| commitdiff \| raw \| diff to current
2011-03-25	Mike Frysinger	sim: bfin: fix clear/set/toggle GPIO handling	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: document SIC limitation	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: fix inverted W1C logic	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: define more UART LSR bits	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: fix typo in TWI stat reg	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: update VIT_MAX behavior to match hardware...	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: always do 16bit sign extension with the...	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: update AV and AC ASTAT bits with acc negation	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: fix thinko in SIC pin encoding	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: allow byteop[123]p src regs to be the same	blob \| commitdiff \| raw \| diff to current
2011-03-24	Mike Frysinger	sim: bfin: fix thinko in bfin_gpio bus addresses	blob \| commitdiff \| raw \| diff to current
2011-03-17	Mike Frysinger	sim: bfin: check for kill/pread	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: add GPIO device simulation	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: fix brace style	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: handle AZ updates with 16bit adds/subs	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: skip acc/ASTAT updates for moves	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: handle AN (negative overflows) in dsp mult...	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: handle V overflows in dsp mult insns	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: decode ASTAT on failure	blob \| commitdiff \| raw \| diff to current
2011-03-15	Mike Frysinger	sim: bfin: handle saturation with fract multiplications	blob \| commitdiff \| raw \| diff to current
2011-03-14	Mike Frysinger	sim: bfin: forgot to cvs add the changelog	blob \| commitdiff \| raw \| diff to current

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