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23608e23 JL |
1 | /* |
2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
5 | */ |
6 | ||
7 | #include <common.h> | |
5a660169 | 8 | #include <div64.h> |
23608e23 JL |
9 | #include <asm/io.h> |
10 | #include <asm/errno.h> | |
11 | #include <asm/arch/imx-regs.h> | |
6a376046 | 12 | #include <asm/arch/crm_regs.h> |
23608e23 | 13 | #include <asm/arch/clock.h> |
6a376046 | 14 | #include <asm/arch/sys_proto.h> |
23608e23 JL |
15 | |
16 | enum pll_clocks { | |
17 | PLL_SYS, /* System PLL */ | |
18 | PLL_BUS, /* System Bus PLL*/ | |
19 | PLL_USBOTG, /* OTG USB PLL */ | |
20 | PLL_ENET, /* ENET PLL */ | |
21 | }; | |
22 | ||
6a376046 | 23 | struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
23608e23 | 24 | |
112fd2ec BT |
25 | #ifdef CONFIG_MXC_OCOTP |
26 | void enable_ocotp_clk(unsigned char enable) | |
27 | { | |
28 | u32 reg; | |
29 | ||
30 | reg = __raw_readl(&imx_ccm->CCGR2); | |
31 | if (enable) | |
32 | reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; | |
33 | else | |
34 | reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; | |
35 | __raw_writel(reg, &imx_ccm->CCGR2); | |
36 | } | |
37 | #endif | |
38 | ||
224beb83 NK |
39 | #ifdef CONFIG_NAND_MXS |
40 | void setup_gpmi_io_clk(u32 cfg) | |
41 | { | |
42 | /* Disable clocks per ERR007177 from MX6 errata */ | |
43 | clrbits_le32(&imx_ccm->CCGR4, | |
44 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
45 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
46 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
47 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
48 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
49 | ||
50 | clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
51 | ||
52 | clrsetbits_le32(&imx_ccm->cs2cdr, | |
53 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
54 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
55 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
56 | cfg); | |
57 | ||
58 | setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
59 | setbits_le32(&imx_ccm->CCGR4, | |
60 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
61 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
62 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
63 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
64 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
65 | } | |
66 | #endif | |
67 | ||
3f467529 WG |
68 | void enable_usboh3_clk(unsigned char enable) |
69 | { | |
70 | u32 reg; | |
71 | ||
72 | reg = __raw_readl(&imx_ccm->CCGR6); | |
73 | if (enable) | |
0bb7e316 | 74 | reg |= MXC_CCM_CCGR6_USBOH3_MASK; |
3f467529 | 75 | else |
0bb7e316 | 76 | reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); |
3f467529 WG |
77 | __raw_writel(reg, &imx_ccm->CCGR6); |
78 | ||
79 | } | |
80 | ||
3d8f1798 | 81 | #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX) |
224beb83 NK |
82 | void enable_enet_clk(unsigned char enable) |
83 | { | |
84 | u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK; | |
85 | ||
86 | if (enable) | |
87 | setbits_le32(&imx_ccm->CCGR1, mask); | |
88 | else | |
89 | clrbits_le32(&imx_ccm->CCGR1, mask); | |
90 | } | |
91 | #endif | |
92 | ||
93 | #ifdef CONFIG_MXC_UART | |
94 | void enable_uart_clk(unsigned char enable) | |
95 | { | |
96 | u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; | |
97 | ||
98 | if (enable) | |
99 | setbits_le32(&imx_ccm->CCGR5, mask); | |
100 | else | |
101 | clrbits_le32(&imx_ccm->CCGR5, mask); | |
102 | } | |
103 | #endif | |
104 | ||
105 | #ifdef CONFIG_SPI | |
106 | /* spi_num can be from 0 - 4 */ | |
107 | int enable_cspi_clock(unsigned char enable, unsigned spi_num) | |
108 | { | |
109 | u32 mask; | |
110 | ||
111 | if (spi_num > 4) | |
112 | return -EINVAL; | |
113 | ||
114 | mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2); | |
115 | if (enable) | |
116 | setbits_le32(&imx_ccm->CCGR1, mask); | |
117 | else | |
118 | clrbits_le32(&imx_ccm->CCGR1, mask); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | #endif | |
123 | ||
124 | #ifdef CONFIG_MMC | |
125 | int enable_usdhc_clk(unsigned char enable, unsigned bus_num) | |
126 | { | |
127 | u32 mask; | |
128 | ||
129 | if (bus_num > 3) | |
130 | return -EINVAL; | |
131 | ||
132 | mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2); | |
133 | if (enable) | |
134 | setbits_le32(&imx_ccm->CCGR6, mask); | |
135 | else | |
136 | clrbits_le32(&imx_ccm->CCGR6, mask); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | #endif | |
141 | ||
fac96408 | 142 | #ifdef CONFIG_SYS_I2C_MXC |
cc54a0f7 TK |
143 | /* i2c_num can be from 0 - 2 */ |
144 | int enable_i2c_clk(unsigned char enable, unsigned i2c_num) | |
145 | { | |
146 | u32 reg; | |
147 | u32 mask; | |
148 | ||
149 | if (i2c_num > 2) | |
150 | return -EINVAL; | |
0bb7e316 EN |
151 | |
152 | mask = MXC_CCM_CCGR_CG_MASK | |
153 | << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1)); | |
cc54a0f7 TK |
154 | reg = __raw_readl(&imx_ccm->CCGR2); |
155 | if (enable) | |
156 | reg |= mask; | |
157 | else | |
158 | reg &= ~mask; | |
159 | __raw_writel(reg, &imx_ccm->CCGR2); | |
160 | return 0; | |
161 | } | |
162 | #endif | |
163 | ||
a0ae0091 HS |
164 | /* spi_num can be from 0 - SPI_MAX_NUM */ |
165 | int enable_spi_clk(unsigned char enable, unsigned spi_num) | |
166 | { | |
167 | u32 reg; | |
168 | u32 mask; | |
169 | ||
170 | if (spi_num > SPI_MAX_NUM) | |
171 | return -EINVAL; | |
172 | ||
173 | mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1); | |
174 | reg = __raw_readl(&imx_ccm->CCGR1); | |
175 | if (enable) | |
176 | reg |= mask; | |
177 | else | |
178 | reg &= ~mask; | |
179 | __raw_writel(reg, &imx_ccm->CCGR1); | |
180 | return 0; | |
181 | } | |
23608e23 JL |
182 | static u32 decode_pll(enum pll_clocks pll, u32 infreq) |
183 | { | |
184 | u32 div; | |
185 | ||
186 | switch (pll) { | |
187 | case PLL_SYS: | |
188 | div = __raw_readl(&imx_ccm->analog_pll_sys); | |
189 | div &= BM_ANADIG_PLL_SYS_DIV_SELECT; | |
190 | ||
2eb268f6 | 191 | return (infreq * div) >> 1; |
23608e23 JL |
192 | case PLL_BUS: |
193 | div = __raw_readl(&imx_ccm->analog_pll_528); | |
194 | div &= BM_ANADIG_PLL_528_DIV_SELECT; | |
195 | ||
196 | return infreq * (20 + (div << 1)); | |
197 | case PLL_USBOTG: | |
198 | div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); | |
199 | div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; | |
200 | ||
201 | return infreq * (20 + (div << 1)); | |
202 | case PLL_ENET: | |
203 | div = __raw_readl(&imx_ccm->analog_pll_enet); | |
204 | div &= BM_ANADIG_PLL_ENET_DIV_SELECT; | |
205 | ||
89cfd0f5 | 206 | return 25000000 * (div + (div >> 1) + 1); |
23608e23 JL |
207 | default: |
208 | return 0; | |
209 | } | |
210 | /* NOTREACHED */ | |
211 | } | |
762a88cc PA |
212 | static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) |
213 | { | |
214 | u32 div; | |
215 | u64 freq; | |
216 | ||
217 | switch (pll) { | |
218 | case PLL_BUS: | |
219 | if (pfd_num == 3) { | |
220 | /* No PFD3 on PPL2 */ | |
221 | return 0; | |
222 | } | |
223 | div = __raw_readl(&imx_ccm->analog_pfd_528); | |
224 | freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); | |
225 | break; | |
226 | case PLL_USBOTG: | |
227 | div = __raw_readl(&imx_ccm->analog_pfd_480); | |
228 | freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); | |
229 | break; | |
230 | default: | |
231 | /* No PFD on other PLL */ | |
232 | return 0; | |
233 | } | |
234 | ||
5a660169 | 235 | return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> |
762a88cc PA |
236 | ANATOP_PFD_FRAC_SHIFT(pfd_num)); |
237 | } | |
23608e23 JL |
238 | |
239 | static u32 get_mcu_main_clk(void) | |
240 | { | |
241 | u32 reg, freq; | |
242 | ||
243 | reg = __raw_readl(&imx_ccm->cacrr); | |
244 | reg &= MXC_CCM_CACRR_ARM_PODF_MASK; | |
245 | reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; | |
833b6435 | 246 | freq = decode_pll(PLL_SYS, MXC_HCLK); |
23608e23 JL |
247 | |
248 | return freq / (reg + 1); | |
249 | } | |
250 | ||
6a376046 | 251 | u32 get_periph_clk(void) |
23608e23 JL |
252 | { |
253 | u32 reg, freq = 0; | |
254 | ||
255 | reg = __raw_readl(&imx_ccm->cbcdr); | |
256 | if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { | |
257 | reg = __raw_readl(&imx_ccm->cbcmr); | |
258 | reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; | |
259 | reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; | |
260 | ||
261 | switch (reg) { | |
262 | case 0: | |
833b6435 | 263 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 JL |
264 | break; |
265 | case 1: | |
266 | case 2: | |
833b6435 | 267 | freq = MXC_HCLK; |
23608e23 JL |
268 | break; |
269 | default: | |
270 | break; | |
271 | } | |
272 | } else { | |
273 | reg = __raw_readl(&imx_ccm->cbcmr); | |
274 | reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; | |
275 | reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; | |
276 | ||
277 | switch (reg) { | |
278 | case 0: | |
833b6435 | 279 | freq = decode_pll(PLL_BUS, MXC_HCLK); |
23608e23 JL |
280 | break; |
281 | case 1: | |
762a88cc | 282 | freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
283 | break; |
284 | case 2: | |
762a88cc | 285 | freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 JL |
286 | break; |
287 | case 3: | |
762a88cc PA |
288 | /* static / 2 divider */ |
289 | freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; | |
23608e23 JL |
290 | break; |
291 | default: | |
292 | break; | |
293 | } | |
294 | } | |
295 | ||
296 | return freq; | |
297 | } | |
298 | ||
23608e23 JL |
299 | static u32 get_ipg_clk(void) |
300 | { | |
301 | u32 reg, ipg_podf; | |
302 | ||
303 | reg = __raw_readl(&imx_ccm->cbcdr); | |
304 | reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; | |
305 | ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; | |
306 | ||
307 | return get_ahb_clk() / (ipg_podf + 1); | |
308 | } | |
309 | ||
310 | static u32 get_ipg_per_clk(void) | |
311 | { | |
312 | u32 reg, perclk_podf; | |
313 | ||
314 | reg = __raw_readl(&imx_ccm->cscmr1); | |
e68661a3 YL |
315 | #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) |
316 | if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) | |
317 | return MXC_HCLK; /* OSC 24Mhz */ | |
318 | #endif | |
23608e23 JL |
319 | perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; |
320 | ||
321 | return get_ipg_clk() / (perclk_podf + 1); | |
322 | } | |
323 | ||
324 | static u32 get_uart_clk(void) | |
325 | { | |
326 | u32 reg, uart_podf; | |
762a88cc | 327 | u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ |
23608e23 | 328 | reg = __raw_readl(&imx_ccm->cscdr1); |
05d54b82 | 329 | #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) |
25b4aa14 FE |
330 | if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) |
331 | freq = MXC_HCLK; | |
332 | #endif | |
23608e23 JL |
333 | reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; |
334 | uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; | |
335 | ||
25b4aa14 | 336 | return freq / (uart_podf + 1); |
23608e23 JL |
337 | } |
338 | ||
339 | static u32 get_cspi_clk(void) | |
340 | { | |
341 | u32 reg, cspi_podf; | |
342 | ||
343 | reg = __raw_readl(&imx_ccm->cscdr2); | |
344 | reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; | |
345 | cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; | |
346 | ||
762a88cc | 347 | return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); |
23608e23 JL |
348 | } |
349 | ||
350 | static u32 get_axi_clk(void) | |
351 | { | |
352 | u32 root_freq, axi_podf; | |
353 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
354 | ||
355 | axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK; | |
356 | axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET; | |
357 | ||
358 | if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { | |
359 | if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) | |
762a88cc | 360 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 | 361 | else |
762a88cc | 362 | root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); |
23608e23 JL |
363 | } else |
364 | root_freq = get_periph_clk(); | |
365 | ||
366 | return root_freq / (axi_podf + 1); | |
367 | } | |
368 | ||
369 | static u32 get_emi_slow_clk(void) | |
370 | { | |
d55e0dab | 371 | u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; |
23608e23 JL |
372 | |
373 | cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
374 | emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; | |
375 | emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; | |
d55e0dab AG |
376 | emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; |
377 | emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; | |
23608e23 JL |
378 | |
379 | switch (emi_clk_sel) { | |
380 | case 0: | |
381 | root_freq = get_axi_clk(); | |
382 | break; | |
383 | case 1: | |
833b6435 | 384 | root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 JL |
385 | break; |
386 | case 2: | |
762a88cc | 387 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
388 | break; |
389 | case 3: | |
762a88cc | 390 | root_freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 JL |
391 | break; |
392 | } | |
393 | ||
d55e0dab | 394 | return root_freq / (emi_slow_podf + 1); |
23608e23 JL |
395 | } |
396 | ||
05d54b82 | 397 | #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) |
25b4aa14 FE |
398 | static u32 get_mmdc_ch0_clk(void) |
399 | { | |
400 | u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); | |
401 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
402 | u32 freq, podf; | |
403 | ||
404 | podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \ | |
405 | >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; | |
406 | ||
407 | switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >> | |
408 | MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) { | |
409 | case 0: | |
410 | freq = decode_pll(PLL_BUS, MXC_HCLK); | |
411 | break; | |
412 | case 1: | |
762a88cc | 413 | freq = mxc_get_pll_pfd(PLL_BUS, 2); |
25b4aa14 FE |
414 | break; |
415 | case 2: | |
762a88cc | 416 | freq = mxc_get_pll_pfd(PLL_BUS, 0); |
25b4aa14 FE |
417 | break; |
418 | case 3: | |
762a88cc PA |
419 | /* static / 2 divider */ |
420 | freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; | |
25b4aa14 FE |
421 | } |
422 | ||
423 | return freq / (podf + 1); | |
424 | ||
425 | } | |
c655b816 OS |
426 | #else |
427 | static u32 get_mmdc_ch0_clk(void) | |
428 | { | |
429 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
430 | u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> | |
431 | MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; | |
432 | ||
433 | return get_periph_clk() / (mmdc_ch0_podf + 1); | |
434 | } | |
435 | #endif | |
31f07964 | 436 | |
c655b816 | 437 | #ifdef CONFIG_FEC_MXC |
5f98d0b5 | 438 | int enable_fec_anatop_clock(enum enet_freq freq) |
31f07964 FE |
439 | { |
440 | u32 reg = 0; | |
441 | s32 timeout = 100000; | |
442 | ||
443 | struct anatop_regs __iomem *anatop = | |
444 | (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; | |
445 | ||
5f98d0b5 FE |
446 | if (freq < ENET_25MHz || freq > ENET_125MHz) |
447 | return -EINVAL; | |
448 | ||
31f07964 | 449 | reg = readl(&anatop->pll_enet); |
5f98d0b5 FE |
450 | reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; |
451 | reg |= freq; | |
452 | ||
31f07964 FE |
453 | if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || |
454 | (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { | |
455 | reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; | |
456 | writel(reg, &anatop->pll_enet); | |
457 | while (timeout--) { | |
458 | if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) | |
459 | break; | |
460 | } | |
461 | if (timeout < 0) | |
462 | return -ETIMEDOUT; | |
463 | } | |
464 | ||
465 | /* Enable FEC clock */ | |
466 | reg |= BM_ANADIG_PLL_ENET_ENABLE; | |
467 | reg &= ~BM_ANADIG_PLL_ENET_BYPASS; | |
468 | writel(reg, &anatop->pll_enet); | |
469 | ||
5c045cdd FE |
470 | #ifdef CONFIG_MX6SX |
471 | /* | |
472 | * Set enet ahb clock to 200MHz | |
473 | * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB | |
474 | */ | |
475 | reg = readl(&imx_ccm->chsccdr); | |
476 | reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK | |
477 | | MXC_CCM_CHSCCDR_ENET_PODF_MASK | |
478 | | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK); | |
479 | /* PLL2 PFD2 */ | |
480 | reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); | |
481 | /* Div = 2*/ | |
482 | reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); | |
483 | reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); | |
484 | writel(reg, &imx_ccm->chsccdr); | |
485 | ||
486 | /* Enable enet system clock */ | |
487 | reg = readl(&imx_ccm->CCGR3); | |
488 | reg |= MXC_CCM_CCGR3_ENET_MASK; | |
489 | writel(reg, &imx_ccm->CCGR3); | |
490 | #endif | |
31f07964 FE |
491 | return 0; |
492 | } | |
25b4aa14 | 493 | #endif |
23608e23 JL |
494 | |
495 | static u32 get_usdhc_clk(u32 port) | |
496 | { | |
497 | u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; | |
498 | u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
499 | u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); | |
500 | ||
501 | switch (port) { | |
502 | case 0: | |
503 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> | |
504 | MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; | |
505 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; | |
506 | ||
507 | break; | |
508 | case 1: | |
509 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> | |
510 | MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; | |
511 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; | |
512 | ||
513 | break; | |
514 | case 2: | |
515 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> | |
516 | MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; | |
517 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; | |
518 | ||
519 | break; | |
520 | case 3: | |
521 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> | |
522 | MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; | |
523 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; | |
524 | ||
525 | break; | |
526 | default: | |
527 | break; | |
528 | } | |
529 | ||
530 | if (clk_sel) | |
762a88cc | 531 | root_freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 | 532 | else |
762a88cc | 533 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
534 | |
535 | return root_freq / (usdhc_podf + 1); | |
536 | } | |
537 | ||
538 | u32 imx_get_uartclk(void) | |
539 | { | |
540 | return get_uart_clk(); | |
541 | } | |
542 | ||
ff167df5 JL |
543 | u32 imx_get_fecclk(void) |
544 | { | |
adadc915 | 545 | return mxc_get_clock(MXC_IPG_CLK); |
ff167df5 JL |
546 | } |
547 | ||
79814492 | 548 | static int enable_enet_pll(uint32_t en) |
64e7cdb5 | 549 | { |
64e7cdb5 EN |
550 | struct mxc_ccm_reg *const imx_ccm |
551 | = (struct mxc_ccm_reg *) CCM_BASE_ADDR; | |
79814492 MV |
552 | s32 timeout = 100000; |
553 | u32 reg = 0; | |
64e7cdb5 EN |
554 | |
555 | /* Enable PLLs */ | |
556 | reg = readl(&imx_ccm->analog_pll_enet); | |
557 | reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; | |
558 | writel(reg, &imx_ccm->analog_pll_enet); | |
559 | reg |= BM_ANADIG_PLL_SYS_ENABLE; | |
560 | while (timeout--) { | |
561 | if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) | |
562 | break; | |
563 | } | |
564 | if (timeout <= 0) | |
565 | return -EIO; | |
566 | reg &= ~BM_ANADIG_PLL_SYS_BYPASS; | |
567 | writel(reg, &imx_ccm->analog_pll_enet); | |
79814492 | 568 | reg |= en; |
64e7cdb5 | 569 | writel(reg, &imx_ccm->analog_pll_enet); |
79814492 MV |
570 | return 0; |
571 | } | |
64e7cdb5 | 572 | |
d95b6ab8 | 573 | #ifndef CONFIG_MX6SX |
79814492 MV |
574 | static void ungate_sata_clock(void) |
575 | { | |
576 | struct mxc_ccm_reg *const imx_ccm = | |
577 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
578 | ||
579 | /* Enable SATA clock. */ | |
580 | setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); | |
581 | } | |
d95b6ab8 | 582 | #endif |
79814492 MV |
583 | |
584 | static void ungate_pcie_clock(void) | |
585 | { | |
586 | struct mxc_ccm_reg *const imx_ccm = | |
587 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
588 | ||
589 | /* Enable PCIe clock. */ | |
590 | setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); | |
591 | } | |
592 | ||
d95b6ab8 | 593 | #ifndef CONFIG_MX6SX |
79814492 MV |
594 | int enable_sata_clock(void) |
595 | { | |
596 | ungate_sata_clock(); | |
597 | return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); | |
598 | } | |
d95b6ab8 | 599 | #endif |
79814492 MV |
600 | |
601 | int enable_pcie_clock(void) | |
602 | { | |
603 | struct anatop_regs *anatop_regs = | |
604 | (struct anatop_regs *)ANATOP_BASE_ADDR; | |
605 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
1b8ad74a | 606 | u32 lvds1_clk_sel; |
79814492 MV |
607 | |
608 | /* | |
609 | * Here be dragons! | |
610 | * | |
611 | * The register ANATOP_MISC1 is not documented in the Freescale | |
612 | * MX6RM. The register that is mapped in the ANATOP space and | |
613 | * marked as ANATOP_MISC1 is actually documented in the PMU section | |
614 | * of the datasheet as PMU_MISC1. | |
615 | * | |
1b8ad74a FE |
616 | * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on |
617 | * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important | |
618 | * for PCI express link that is clocked from the i.MX6. | |
79814492 MV |
619 | */ |
620 | #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) | |
621 | #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) | |
622 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F | |
1b8ad74a FE |
623 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa |
624 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb | |
625 | ||
626 | if (is_cpu_type(MXC_CPU_MX6SX)) | |
627 | lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; | |
628 | else | |
629 | lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; | |
630 | ||
79814492 MV |
631 | clrsetbits_le32(&anatop_regs->ana_misc1, |
632 | ANADIG_ANA_MISC1_LVDSCLK1_IBEN | | |
633 | ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, | |
1b8ad74a | 634 | ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel); |
79814492 MV |
635 | |
636 | /* PCIe reference clock sourced from AXI. */ | |
637 | clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); | |
638 | ||
639 | /* Party time! Ungate the clock to the PCIe. */ | |
d95b6ab8 | 640 | #ifndef CONFIG_MX6SX |
79814492 | 641 | ungate_sata_clock(); |
d95b6ab8 | 642 | #endif |
79814492 MV |
643 | ungate_pcie_clock(); |
644 | ||
645 | return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | | |
646 | BM_ANADIG_PLL_ENET_ENABLE_PCIE); | |
64e7cdb5 EN |
647 | } |
648 | ||
36c1ca4d NG |
649 | #ifdef CONFIG_SECURE_BOOT |
650 | void hab_caam_clock_enable(unsigned char enable) | |
651 | { | |
652 | u32 reg; | |
653 | ||
654 | /* CG4 ~ CG6, CAAM clocks */ | |
655 | reg = __raw_readl(&imx_ccm->CCGR0); | |
656 | if (enable) | |
657 | reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | | |
658 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | | |
659 | MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); | |
660 | else | |
661 | reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | | |
662 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | | |
663 | MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); | |
664 | __raw_writel(reg, &imx_ccm->CCGR0); | |
665 | ||
666 | /* EMI slow clk */ | |
667 | reg = __raw_readl(&imx_ccm->CCGR6); | |
668 | if (enable) | |
669 | reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
670 | else | |
671 | reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
672 | __raw_writel(reg, &imx_ccm->CCGR6); | |
673 | } | |
674 | #endif | |
675 | ||
23608e23 JL |
676 | unsigned int mxc_get_clock(enum mxc_clock clk) |
677 | { | |
678 | switch (clk) { | |
679 | case MXC_ARM_CLK: | |
680 | return get_mcu_main_clk(); | |
681 | case MXC_PER_CLK: | |
682 | return get_periph_clk(); | |
683 | case MXC_AHB_CLK: | |
684 | return get_ahb_clk(); | |
685 | case MXC_IPG_CLK: | |
686 | return get_ipg_clk(); | |
687 | case MXC_IPG_PERCLK: | |
e7bed5c2 | 688 | case MXC_I2C_CLK: |
23608e23 JL |
689 | return get_ipg_per_clk(); |
690 | case MXC_UART_CLK: | |
691 | return get_uart_clk(); | |
692 | case MXC_CSPI_CLK: | |
693 | return get_cspi_clk(); | |
694 | case MXC_AXI_CLK: | |
695 | return get_axi_clk(); | |
696 | case MXC_EMI_SLOW_CLK: | |
697 | return get_emi_slow_clk(); | |
698 | case MXC_DDR_CLK: | |
699 | return get_mmdc_ch0_clk(); | |
700 | case MXC_ESDHC_CLK: | |
701 | return get_usdhc_clk(0); | |
702 | case MXC_ESDHC2_CLK: | |
703 | return get_usdhc_clk(1); | |
704 | case MXC_ESDHC3_CLK: | |
705 | return get_usdhc_clk(2); | |
706 | case MXC_ESDHC4_CLK: | |
707 | return get_usdhc_clk(3); | |
708 | case MXC_SATA_CLK: | |
709 | return get_ahb_clk(); | |
710 | default: | |
711 | break; | |
712 | } | |
713 | ||
714 | return -1; | |
715 | } | |
716 | ||
717 | /* | |
718 | * Dump some core clockes. | |
719 | */ | |
720 | int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
721 | { | |
722 | u32 freq; | |
833b6435 | 723 | freq = decode_pll(PLL_SYS, MXC_HCLK); |
23608e23 | 724 | printf("PLL_SYS %8d MHz\n", freq / 1000000); |
833b6435 | 725 | freq = decode_pll(PLL_BUS, MXC_HCLK); |
23608e23 | 726 | printf("PLL_BUS %8d MHz\n", freq / 1000000); |
833b6435 | 727 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 | 728 | printf("PLL_OTG %8d MHz\n", freq / 1000000); |
833b6435 | 729 | freq = decode_pll(PLL_ENET, MXC_HCLK); |
23608e23 JL |
730 | printf("PLL_NET %8d MHz\n", freq / 1000000); |
731 | ||
732 | printf("\n"); | |
733 | printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); | |
734 | printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); | |
cc446726 | 735 | #ifdef CONFIG_MXC_SPI |
23608e23 | 736 | printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); |
cc446726 | 737 | #endif |
23608e23 JL |
738 | printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); |
739 | printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); | |
740 | printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); | |
741 | printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); | |
742 | printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); | |
743 | printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); | |
744 | printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); | |
745 | printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); | |
746 | printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); | |
747 | ||
748 | return 0; | |
749 | } | |
750 | ||
d95b6ab8 | 751 | #ifndef CONFIG_MX6SX |
5ea7f0e3 PKS |
752 | void enable_ipu_clock(void) |
753 | { | |
754 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
755 | int reg; | |
756 | reg = readl(&mxc_ccm->CCGR3); | |
a0a0dacf | 757 | reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; |
5ea7f0e3 PKS |
758 | writel(reg, &mxc_ccm->CCGR3); |
759 | } | |
d95b6ab8 | 760 | #endif |
23608e23 JL |
761 | /***************************************************/ |
762 | ||
763 | U_BOOT_CMD( | |
764 | clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, | |
765 | "display clocks", | |
766 | "" | |
767 | ); |