[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / sys_info.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Manikandan Pillai <mani.pillai@ti.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>	/* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/bootm.h>

#include <i2c.h>
#include <linux/compiler.h>

extern omap3_sysinfo sysinfo;
static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;

#ifdef CONFIG_DISPLAY_CPUINFO
static char *rev_s[CPU_3XX_MAX_REV] = {
				"1.0",
				"2.0",
				"2.1",
				"3.0",
				"3.1",
				"UNKNOWN",
				"UNKNOWN",
				"3.1.2"};

/* this is the revision table for 37xx CPUs */
static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
				"1.0",
				"1.1",
				"1.2"};
#endif /* CONFIG_DISPLAY_CPUINFO */

/*****************************************************************
 * get_dieid(u32 *id) - read die ID
 *****************************************************************/
void get_dieid(u32 *id)
{
	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;

	id[3] = readl(&id_base->die_id_0);
	id[2] = readl(&id_base->die_id_1);
	id[1] = readl(&id_base->die_id_2);
	id[0] = readl(&id_base->die_id_3);
}

/*****************************************************************
 * dieid_num_r(void) - read and set die ID
 *****************************************************************/
void dieid_num_r(void)
{
	char *uid_s, die_id[34];
	u32 id[4];

	memset(die_id, 0, sizeof(die_id));

	uid_s = getenv("dieid#");

	if (uid_s == NULL) {
		get_dieid(id);
		sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
		setenv("dieid#", die_id);
		uid_s = die_id;
	}

	printf("Die ID #%s\n", uid_s);
}

/******************************************
 * get_cpu_type(void) - extract cpu info
 ******************************************/
u32 get_cpu_type(void)
{
	return readl(&ctrl_base->ctrl_omap_stat);
}

/******************************************
 * get_cpu_id(void) - extract cpu id
 * returns 0 for ES1.0, cpuid otherwise
 ******************************************/
u32 get_cpu_id(void)
{
	struct ctrl_id *id_base;
	u32 cpuid = 0;

	/*
	 * On ES1.0 the IDCODE register is not exposed on L4
	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
	 */
	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
	if ((cpuid & 0xf) == 0x0) {
		return 0;
	} else {
		/* Decode the IDs on > ES1.0 */
		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;

		cpuid = readl(&id_base->idcode);
	}

	return cpuid;
}

/******************************************
 * get_cpu_family(void) - extract cpu info
 ******************************************/
u32 get_cpu_family(void)
{
	u16 hawkeye;
	u32 cpu_family;
	u32 cpuid = get_cpu_id();

	if (cpuid == 0)
		return CPU_OMAP34XX;

	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
	switch (hawkeye) {
	case HAWKEYE_OMAP34XX:
		cpu_family = CPU_OMAP34XX;
		break;
	case HAWKEYE_AM35XX:
		cpu_family = CPU_AM35XX;
		break;
	case HAWKEYE_OMAP36XX:
		cpu_family = CPU_OMAP36XX;
		break;
	default:
		cpu_family = CPU_OMAP34XX;
	}

	return cpu_family;
}

/******************************************
 * get_cpu_rev(void) - extract version info
 ******************************************/
u32 get_cpu_rev(void)
{
	u32 cpuid = get_cpu_id();

	if (cpuid == 0)
		return CPU_3XX_ES10;
	else
		return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
}

/*****************************************************************
 * get_sku_id(void) - read sku_id to get info on max clock rate
 *****************************************************************/
u32 get_sku_id(void)
{
	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}

/***************************************************************************
 *  get_gpmc0_base() - Return current address hardware will be
 *     fetching from. The below effectively gives what is correct, its a bit
 *   mis-leading compared to the TRM.  For the most general case the mask
 *   needs to be also taken into account this does work in practice.
 *   - for u-boot we currently map:
 *       -- 0 to nothing,
 *       -- 4 to flash
 *       -- 8 to enent
 *       -- c to wifi
 ****************************************************************************/
u32 get_gpmc0_base(void)
{
	u32 b;

	b = readl(&gpmc_cfg->cs[0].config7);
	b &= 0x1F;		/* keep base [5:0] */
	b = b << 24;		/* ret 0x0b000000 */
	return b;
}

/*******************************************************************
 * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 *******************************************************************/
u32 get_gpmc0_width(void)
{
	return WIDTH_16BIT;
}

/*************************************************************************
 * get_board_rev() - setup to pass kernel board revision information
 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 *************************************************************************/
#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	return 0x20;
}
#endif

/********************************************************
 *  get_base(); get upper addr of current execution
 *******************************************************/
static u32 get_base(void)
{
	u32 val;

	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
	val &= 0xF0000000;
	val >>= 28;
	return val;
}

/********************************************************
 *  is_running_in_flash() - tell if currently running in
 *  FLASH.
 *******************************************************/
u32 is_running_in_flash(void)
{
	if (get_base() < 4)
		return 1;	/* in FLASH */

	return 0;		/* running in SRAM or SDRAM */
}

/********************************************************
 *  is_running_in_sram() - tell if currently running in
 *  SRAM.
 *******************************************************/
u32 is_running_in_sram(void)
{
	if (get_base() == 4)
		return 1;	/* in SRAM */

	return 0;		/* running in FLASH or SDRAM */
}

/********************************************************
 *  is_running_in_sdram() - tell if currently running in
 *  SDRAM.
 *******************************************************/
u32 is_running_in_sdram(void)
{
	if (get_base() > 4)
		return 1;	/* in SDRAM */

	return 0;		/* running in SRAM or FLASH */
}

/***************************************************************
 *  get_boot_type() - Is this an XIP type device or a stream one
 *  bits 4-0 specify type. Bit 5 says mem/perif
 ***************************************************************/
u32 get_boot_type(void)
{
	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
}

/*************************************************************
 *  get_device_type(): tell if GP/HS/EMU/TST
 *************************************************************/
u32 get_device_type(void)
{
	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
}

#ifdef CONFIG_DISPLAY_CPUINFO
/**
 * Print CPU information
 */
int print_cpuinfo (void)
{
	char *cpu_family_s, *cpu_s, *sec_s, *max_clk;

	switch (get_cpu_family()) {
	case CPU_OMAP34XX:
		cpu_family_s = "OMAP";
		switch (get_cpu_type()) {
		case OMAP3503:
			cpu_s = "3503";
			break;
		case OMAP3515:
			cpu_s = "3515";
			break;
		case OMAP3525:
			cpu_s = "3525";
			break;
		case OMAP3530:
			cpu_s = "3530";
			break;
		default:
			cpu_s = "35XX";
			break;
		}
		if ((get_cpu_rev() >= CPU_3XX_ES31) &&
		    (get_sku_id() == SKUID_CLK_720MHZ))
			max_clk = "720 MHz";
		else
			max_clk = "600 MHz";

		break;
	case CPU_AM35XX:
		cpu_family_s = "AM";
		switch (get_cpu_type()) {
		case AM3505:
			cpu_s = "3505";
			break;
		case AM3517:
			cpu_s = "3517";
			break;
		default:
			cpu_s = "35XX";
			break;
		}
		max_clk = "600 Mhz";
		break;
	case CPU_OMAP36XX:
		cpu_family_s = "OMAP";
		switch (get_cpu_type()) {
		case OMAP3730:
			cpu_s = "3630/3730";
			break;
		default:
			cpu_s = "36XX/37XX";
			break;
		}
		max_clk = "1 Ghz";
		break;
	default:
		cpu_family_s = "OMAP";
		cpu_s = "35XX";
		max_clk = "600 Mhz";
	}

	switch (get_device_type()) {
	case TST_DEVICE:
		sec_s = "TST";
		break;
	case EMU_DEVICE:
		sec_s = "EMU";
		break;
	case HS_DEVICE:
		sec_s = "HS";
		break;
	case GP_DEVICE:
		sec_s = "GP";
		break;
	default:
		sec_s = "?";
	}

	if (CPU_OMAP36XX == get_cpu_family())
		printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
		       cpu_family_s, cpu_s, sec_s,
		       rev_s_37xx[get_cpu_rev()], max_clk);
	else
		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
			cpu_family_s, cpu_s, sec_s,
			rev_s[get_cpu_rev()], max_clk);

	return 0;
}
#endif	/* CONFIG_DISPLAY_CPUINFO */
Commit	Line	Data
91eee546 DB	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Author :
	6	* Manikandan Pillai <mani.pillai@ti.com>
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
91eee546 DB	13	*/
	14
	15	#include <common.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/mem.h> /* get mem tables */
	18	#include <asm/arch/sys_proto.h>
bf855028 JH	19	#include <asm/bootm.h>
bf855028 JH	20
91eee546	21	#include <i2c.h>
715462dd	22	#include <linux/compiler.h>
91eee546 DB	23
91eee546 DB	24	extern omap3_sysinfo sysinfo;
97a099ea	25	static struct ctrl ctrl_base = (struct ctrl )OMAP34XX_CTRL_BASE;
80bb756d SP	26
80bb756d SP	27	#ifdef CONFIG_DISPLAY_CPUINFO
cba0b778 SP	28	static char *rev_s[CPU_3XX_MAX_REV] = {
	29	"1.0",
	30	"2.0",
	31	"2.1",
	32	"3.0",
b2b9169f SS	33	"3.1",
	34	"UNKNOWN",
	35	"UNKNOWN",
	36	"3.1.2"};
91eee546	37
32b58ce7 HG	38	/* this is the revision table for 37xx CPUs */
	39	static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
	40	"1.0",
	41	"1.1",
	42	"1.2"};
939e7222	43	#endif /* CONFIG_DISPLAY_CPUINFO */
32b58ce7	44
79e7e87f NM	45	/*****************************************************************
	46	* get_dieid(u32 *id) - read die ID
	47	*****************************************************************/
	48	void get_dieid(u32 *id)
	49	{
	50	struct ctrl_id id_base = (struct ctrl_id )OMAP34XX_ID_L4_IO_BASE;
	51
	52	id[3] = readl(&id_base->die_id_0);
	53	id[2] = readl(&id_base->die_id_1);
	54	id[1] = readl(&id_base->die_id_2);
	55	id[0] = readl(&id_base->die_id_3);
	56	}
	57
e6a6a704 DB	58	/*****************************************************************
	59	* dieid_num_r(void) - read and set die ID
	60	*****************************************************************/
	61	void dieid_num_r(void)
	62	{
e6a6a704 DB	63	char *uid_s, die_id[34];
	64	u32 id[4];
	65
	66	memset(die_id, 0, sizeof(die_id));
	67
	68	uid_s = getenv("dieid#");
	69
	70	if (uid_s == NULL) {
79e7e87f	71	get_dieid(id);
e6a6a704 DB	72	sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
	73	setenv("dieid#", die_id);
	74	uid_s = die_id;
	75	}
	76
	77	printf("Die ID #%s\n", uid_s);
	78	}
	79
6530a8bf DB	80	/******************************************
	81	* get_cpu_type(void) - extract cpu info
	82	******************************************/
	83	u32 get_cpu_type(void)
	84	{
	85	return readl(&ctrl_base->ctrl_omap_stat);
	86	}
	87
91eee546	88	/******************************************
b2b9169f SS	89	* get_cpu_id(void) - extract cpu id
b2b9169f SS	90	* returns 0 for ES1.0, cpuid otherwise
91eee546	91	******************************************/
b2b9169f	92	u32 get_cpu_id(void)
91eee546	93	{
97a099ea	94	struct ctrl_id *id_base;
b2b9169f	95	u32 cpuid = 0;
91eee546 DB	96
	97	/*
	98	* On ES1.0 the IDCODE register is not exposed on L4
cba0b778	99	* so using CPU ID to differentiate between ES1.0 and > ES1.0.
91eee546 DB	100	*/
91eee546 DB	101	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
b2b9169f SS	102	if ((cpuid & 0xf) == 0x0) {
	103	return 0;
	104	} else {
cba0b778	105	/* Decode the IDs on > ES1.0 */
97a099ea	106	id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
91eee546	107
b2b9169f SS	108	cpuid = readl(&id_base->idcode);
b2b9169f SS	109	}
cba0b778	110
b2b9169f SS	111	return cpuid;
b2b9169f SS	112	}
cba0b778	113
b2b9169f SS	114	/******************************************
	115	* get_cpu_family(void) - extract cpu info
	116	******************************************/
	117	u32 get_cpu_family(void)
	118	{
	119	u16 hawkeye;
	120	u32 cpu_family;
	121	u32 cpuid = get_cpu_id();
	122
	123	if (cpuid == 0)
	124	return CPU_OMAP34XX;
	125
	126	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
	127	switch (hawkeye) {
	128	case HAWKEYE_OMAP34XX:
	129	cpu_family = CPU_OMAP34XX;
	130	break;
	131	case HAWKEYE_AM35XX:
	132	cpu_family = CPU_AM35XX;
	133	break;
	134	case HAWKEYE_OMAP36XX:
	135	cpu_family = CPU_OMAP36XX;
	136	break;
	137	default:
	138	cpu_family = CPU_OMAP34XX;
cba0b778	139	}
b2b9169f SS	140
	141	return cpu_family;
	142	}
	143
	144	/******************************************
	145	* get_cpu_rev(void) - extract version info
	146	******************************************/
	147	u32 get_cpu_rev(void)
	148	{
	149	u32 cpuid = get_cpu_id();
	150
	151	if (cpuid == 0)
	152	return CPU_3XX_ES10;
	153	else
	154	return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
	155	}
	156
	157	/*****************************************************************
	158	* get_sku_id(void) - read sku_id to get info on max clock rate
	159	*****************************************************************/
	160	u32 get_sku_id(void)
	161	{
	162	struct ctrl_id id_base = (struct ctrl_id )OMAP34XX_ID_L4_IO_BASE;
	163	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
91eee546 DB	164	}
91eee546 DB	165
91eee546 DB	166	/***************************************************************************
	167	* get_gpmc0_base() - Return current address hardware will be
	168	* fetching from. The below effectively gives what is correct, its a bit
	169	* mis-leading compared to the TRM. For the most general case the mask
	170	* needs to be also taken into account this does work in practice.
	171	* - for u-boot we currently map:
	172	* -- 0 to nothing,
	173	* -- 4 to flash
	174	* -- 8 to enent
	175	* -- c to wifi
	176	****************************************************************************/
	177	u32 get_gpmc0_base(void)
	178	{
	179	u32 b;
	180
89411352	181	b = readl(&gpmc_cfg->cs[0].config7);
91eee546 DB	182	b &= 0x1F; /* keep base [5:0] */
	183	b = b << 24; /* ret 0x0b000000 */
	184	return b;
	185	}
	186
	187	/*******************************************************************
	188	* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
	189	*******************************************************************/
	190	u32 get_gpmc0_width(void)
	191	{
	192	return WIDTH_16BIT;
	193	}
	194
	195	/*************************************************************************
	196	* get_board_rev() - setup to pass kernel board revision information
	197	* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
	198	*************************************************************************/
fb9006c3	199	#ifdef CONFIG_REVISION_TAG
715462dd	200	u32 __weak get_board_rev(void)
91eee546 DB	201	{
	202	return 0x20;
	203	}
fb9006c3	204	#endif
91eee546	205
91eee546 DB	206	/********************************************************
	207	* get_base(); get upper addr of current execution
	208	*******************************************************/
98431d58	209	static u32 get_base(void)
91eee546 DB	210	{
	211	u32 val;
	212
	213	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
	214	val &= 0xF0000000;
	215	val >>= 28;
	216	return val;
	217	}
	218
	219	/********************************************************
	220	* is_running_in_flash() - tell if currently running in
	221	* FLASH.
	222	*******************************************************/
	223	u32 is_running_in_flash(void)
	224	{
	225	if (get_base() < 4)
	226	return 1; /* in FLASH */
	227
	228	return 0; /* running in SRAM or SDRAM */
	229	}
	230
	231	/********************************************************
	232	* is_running_in_sram() - tell if currently running in
	233	* SRAM.
	234	*******************************************************/
	235	u32 is_running_in_sram(void)
	236	{
	237	if (get_base() == 4)
	238	return 1; /* in SRAM */
	239
	240	return 0; /* running in FLASH or SDRAM */
	241	}
	242
	243	/********************************************************
	244	* is_running_in_sdram() - tell if currently running in
	245	* SDRAM.
	246	*******************************************************/
	247	u32 is_running_in_sdram(void)
	248	{
	249	if (get_base() > 4)
	250	return 1; /* in SDRAM */
	251
	252	return 0; /* running in SRAM or FLASH */
	253	}
	254
	255	/***************************************************************
	256	* get_boot_type() - Is this an XIP type device or a stream one
	257	* bits 4-0 specify type. Bit 5 says mem/perif
	258	***************************************************************/
	259	u32 get_boot_type(void)
	260	{
	261	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
	262	}
	263
	264	/*************************************************************
	265	* get_device_type(): tell if GP/HS/EMU/TST
	266	*************************************************************/
	267	u32 get_device_type(void)
	268	{
	269	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
	270	}
6a6b62e3 SP	271
	272	#ifdef CONFIG_DISPLAY_CPUINFO
	273	/**
	274	* Print CPU information
	275	*/
	276	int print_cpuinfo (void)
	277	{
b2b9169f SS	278	char cpu_family_s, cpu_s, sec_s, max_clk;
	279
	280	switch (get_cpu_family()) {
	281	case CPU_OMAP34XX:
	282	cpu_family_s = "OMAP";
	283	switch (get_cpu_type()) {
	284	case OMAP3503:
	285	cpu_s = "3503";
	286	break;
	287	case OMAP3515:
	288	cpu_s = "3515";
	289	break;
	290	case OMAP3525:
	291	cpu_s = "3525";
	292	break;
	293	case OMAP3530:
	294	cpu_s = "3530";
	295	break;
	296	default:
	297	cpu_s = "35XX";
	298	break;
	299	}
	300	if ((get_cpu_rev() >= CPU_3XX_ES31) &&
	301	(get_sku_id() == SKUID_CLK_720MHZ))
9d0fd10c	302	max_clk = "720 MHz";
b2b9169f	303	else
9d0fd10c	304	max_clk = "600 MHz";
6a6b62e3	305
6a6b62e3	306	break;
b2b9169f SS	307	case CPU_AM35XX:
	308	cpu_family_s = "AM";
	309	switch (get_cpu_type()) {
	310	case AM3505:
	311	cpu_s = "3505";
	312	break;
	313	case AM3517:
	314	cpu_s = "3517";
	315	break;
	316	default:
	317	cpu_s = "35XX";
	318	break;
	319	}
	320	max_clk = "600 Mhz";
6a6b62e3	321	break;
b2b9169f SS	322	case CPU_OMAP36XX:
	323	cpu_family_s = "OMAP";
	324	switch (get_cpu_type()) {
	325	case OMAP3730:
	326	cpu_s = "3630/3730";
	327	break;
	328	default:
	329	cpu_s = "36XX/37XX";
	330	break;
	331	}
	332	max_clk = "1 Ghz";
6a6b62e3 SP	333	break;
6a6b62e3 SP	334	default:
b2b9169f	335	cpu_family_s = "OMAP";
6a6b62e3	336	cpu_s = "35XX";
b2b9169f	337	max_clk = "600 Mhz";
6a6b62e3 SP	338	}
	339
	340	switch (get_device_type()) {
	341	case TST_DEVICE:
	342	sec_s = "TST";
	343	break;
	344	case EMU_DEVICE:
	345	sec_s = "EMU";
	346	break;
	347	case HS_DEVICE:
	348	sec_s = "HS";
	349	break;
	350	case GP_DEVICE:
	351	sec_s = "GP";
	352	break;
	353	default:
	354	sec_s = "?";
	355	}
	356
32b58ce7	357	if (CPU_OMAP36XX == get_cpu_family())
c4ec2818 AB	358	printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
	359	cpu_family_s, cpu_s, sec_s,
	360	rev_s_37xx[get_cpu_rev()], max_clk);
32b58ce7 HG	361	else
32b58ce7 HG	362	printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
b2b9169f SS	363	cpu_family_s, cpu_s, sec_s,
b2b9169f SS	364	rev_s[get_cpu_rev()], max_clk);
6a6b62e3 SP	365
	366	return 0;
	367	}
	368	#endif /* CONFIG_DISPLAY_CPUINFO */