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ARM: BeagleBoard-x15: Enable i2c5 clocks
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c
CommitLineData
01b753ff
S		 1/*
2 *
3 * HW data initialization for OMAP5
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
01b753ff
S		 11 */
12#include <common.h>
63fc0c77 13#include <palmas.h>
01b753ff 14#include <asm/arch/omap.h>
ee9447bf 15#include <asm/arch/sys_proto.h>
01b753ff 16#include <asm/omap_common.h>
af1d002f 17#include <asm/arch/clock.h>
3fcdd4a5 18#include <asm/omap_gpio.h>
ee9447bf 19#include <asm/io.h>
ef1697e9 20#include <asm/emif.h>
01b753ff
S		 21
22struct prcm_regs const **prcm =
23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
ee9447bf
S		 24struct dplls const **dplls_data =
25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
3fcdd4a5
S		 26struct vcores_data const **omap_vcores =
27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
c43c8339 28struct omap_sys_ctrl_regs const **ctrl =
f92f2277 29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
ee9447bf 30
47abc3df 31/* OPP HIGH FREQUENCY for ES2.0 */
ee9447bf 32static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
47abc3df
S		 33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 40};
41
47abc3df 42/* OPP NOM FREQUENCY for ES1.0 */
ee9447bf 43static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
47abc3df
S		 44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 51};
52
47abc3df 53/* OPP LOW FREQUENCY for ES1.0 */
ee9447bf 54static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
47abc3df
S		 55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 62};
63
47abc3df
S		 64/* OPP LOW FREQUENCY for ES2.0 */
65static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 73};
74
d2c7074b 75/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
ea8eff1f 76static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
97405d84
LV		 77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
ea8eff1f 82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
ea8eff1f
LV		 84};
85
ee9447bf
S		 86static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
47abc3df
S		 88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
95};
96
97static const struct dpll_params
98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
ee9447bf
S		 106};
107
ea8eff1f 108static const struct dpll_params
97405d84
LV		 109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
ea8eff1f 115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
ea8eff1f
LV		 117};
118
ee9447bf
S		 119static const struct dpll_params
120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
47abc3df
S		 121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
128};
129
130static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
ee9447bf
S		 139};
140
141static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
47abc3df
S		 142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
149};
150
151static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 159};
160
ea8eff1f 161static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
5298f21a 162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
62d206dc 163 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
5298f21a
LV		 164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
ea8eff1f 167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
5298f21a 168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
ea8eff1f
LV		 169};
170
ee9447bf 171static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
47abc3df
S		 172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 179};
180
97405d84
LV		 181static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
189};
190
ee9447bf
S		 191/* ABE M & N values with sys_clk as source */
192static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
47abc3df
S		 194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 201};
202
203/* ABE M & N values with 32K clock as source */
204static const struct dpll_params abe_dpll_params_32k_196608khz = {
47abc3df 205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
ee9447bf
S		 206};
207
97405d84
LV		 208/* ABE M & N values with sysclk2(22.5792 MHz) as input */
209static const struct dpll_params
210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
218};
219
ee9447bf 220static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
47abc3df 221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
97405d84 222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
47abc3df
S		 223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
ea8eff1f 227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
ea8eff1f
LV		 228};
229
681f785f
S		 230static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
238};
239
97405d84
LV		 240static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
ea8eff1f 246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
ee9447bf
S		 248};
249
65e9d56f
LV		 250static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
258};
259
ee9447bf
S		 260struct dplls omap5_dplls_es1 = {
261 .mpu = mpu_dpll_params_800mhz,
262 .core = core_dpll_params_2128mhz_ddr532,
263 .per = per_dpll_params_768mhz,
264 .iva = iva_dpll_params_2330mhz,
265#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
266 .abe = abe_dpll_params_sysclk_196608khz,
267#else
268 .abe = &abe_dpll_params_32k_196608khz,
269#endif
ea8eff1f
LV		 270 .usb = usb_dpll_params_1920mhz,
271 .ddr = NULL
ee9447bf
S		 272};
273
47abc3df 274struct dplls omap5_dplls_es2 = {
d2c7074b 275 .mpu = mpu_dpll_params_1ghz,
47abc3df
S		 276 .core = core_dpll_params_2128mhz_ddr532_es2,
277 .per = per_dpll_params_768mhz_es2,
278 .iva = iva_dpll_params_2330mhz,
279#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
280 .abe = abe_dpll_params_sysclk_196608khz,
281#else
282 .abe = &abe_dpll_params_32k_196608khz,
283#endif
ea8eff1f
LV		 284 .usb = usb_dpll_params_1920mhz,
285 .ddr = NULL
286};
287
288struct dplls dra7xx_dplls = {
289 .mpu = mpu_dpll_params_1ghz,
97405d84 290 .core = core_dpll_params_2128mhz_dra7xx,
ea8eff1f 291 .per = per_dpll_params_768mhz_dra7xx,
97405d84
LV		 292 .abe = abe_dpll_params_sysclk2_361267khz,
293 .iva = iva_dpll_params_2330mhz_dra7xx,
ea8eff1f 294 .usb = usb_dpll_params_1920mhz,
97405d84 295 .ddr = ddr_dpll_params_2128mhz,
65e9d56f 296 .gmac = gmac_dpll_params_2000mhz,
47abc3df
S		 297};
298
681f785f
S		 299struct dplls dra72x_dplls = {
300 .mpu = mpu_dpll_params_1ghz,
301 .core = core_dpll_params_2128mhz_dra7xx,
302 .per = per_dpll_params_768mhz_dra7xx,
303 .abe = abe_dpll_params_sysclk2_361267khz,
304 .iva = iva_dpll_params_2330mhz_dra7xx,
305 .usb = usb_dpll_params_1920mhz,
306 .ddr = ddr_dpll_params_2664mhz,
307 .gmac = gmac_dpll_params_2000mhz,
308};
309
3fcdd4a5
S		 310struct pmic_data palmas = {
311 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
312 .step = 10000, /* 10 mV represented in uV */
313 /*
314 * Offset codes 1-6 all give the base voltage in Palmas
315 * Offset code 0 switches OFF the SMPS
316 */
317 .start_code = 6,
4ca94d81
LV		 318 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
319 .pmic_bus_init = sri2c_init,
320 .pmic_write = omap_vc_bypass_send_value,
3fcdd4a5
S		 321};
322
b558af81 323/* The TPS659038 and TPS65917 are software-compatible, use common struct */
63fc0c77
LV		 324struct pmic_data tps659038 = {
325 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
326 .step = 10000, /* 10 mV represented in uV */
327 /*
328 * Offset codes 1-6 all give the base voltage in Palmas
329 * Offset code 0 switches OFF the SMPS
330 */
331 .start_code = 6,
332 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
333 .pmic_bus_init = gpi2c_init,
334 .pmic_write = palmas_i2c_write_u8,
335};
336
3fcdd4a5
S		 337struct vcores_data omap5430_volts = {
338 .mpu.value = VDD_MPU,
339 .mpu.addr = SMPS_REG_ADDR_12_MPU,
340 .mpu.pmic = &palmas,
341
342 .core.value = VDD_CORE,
343 .core.addr = SMPS_REG_ADDR_8_CORE,
344 .core.pmic = &palmas,
345
346 .mm.value = VDD_MM,
347 .mm.addr = SMPS_REG_ADDR_45_IVA,
348 .mm.pmic = &palmas,
349};
350
47abc3df
S		 351struct vcores_data omap5430_volts_es2 = {
352 .mpu.value = VDD_MPU_ES2,
3fcdd4a5
S		 353 .mpu.addr = SMPS_REG_ADDR_12_MPU,
354 .mpu.pmic = &palmas,
355
47abc3df 356 .core.value = VDD_CORE_ES2,
3fcdd4a5
S		 357 .core.addr = SMPS_REG_ADDR_8_CORE,
358 .core.pmic = &palmas,
359
47abc3df 360 .mm.value = VDD_MM_ES2,
3fcdd4a5
S		 361 .mm.addr = SMPS_REG_ADDR_45_IVA,
362 .mm.pmic = &palmas,
363};
364
63fc0c77
LV		 365struct vcores_data dra752_volts = {
366 .mpu.value = VDD_MPU_DRA752,
18c9d55a
NM		 367 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
368 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
c27cd33b 369 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
63fc0c77
LV		 370 .mpu.pmic = &tps659038,
371
372 .eve.value = VDD_EVE_DRA752,
18c9d55a
NM		 373 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
374 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
c27cd33b 375 .eve.addr = TPS659038_REG_ADDR_SMPS45,
63fc0c77
LV		 376 .eve.pmic = &tps659038,
377
378 .gpu.value = VDD_GPU_DRA752,
18c9d55a
NM		 379 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
380 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
c27cd33b 381 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
63fc0c77
LV		 382 .gpu.pmic = &tps659038,
383
384 .core.value = VDD_CORE_DRA752,
18c9d55a
NM		 385 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
386 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
c27cd33b 387 .core.addr = TPS659038_REG_ADDR_SMPS7,
63fc0c77
LV		 388 .core.pmic = &tps659038,
389
390 .iva.value = VDD_IVA_DRA752,
18c9d55a
NM		 391 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
392 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
c27cd33b 393 .iva.addr = TPS659038_REG_ADDR_SMPS8,
63fc0c77
LV		 394 .iva.pmic = &tps659038,
395};
396
8b0d1bbc 397struct vcores_data dra722_volts = {
b558af81 398 .mpu.value = VDD_MPU_DRA72x,
8b0d1bbc 399 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
b558af81
LP		 400 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
401 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
8b0d1bbc
K		 402 .mpu.pmic = &tps659038,
403
b558af81
LP		 404 .core.value = VDD_CORE_DRA72x,
405 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
406 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
407 .core.addr = TPS65917_REG_ADDR_SMPS2,
408 .core.pmic = &tps659038,
8b0d1bbc 409
b558af81
LP		 410 /*
411 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
412 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
413 */
414 .gpu.value = VDD_GPU_DRA72x,
8b0d1bbc 415 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
b558af81
LP		 416 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
417 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
8b0d1bbc
K		 418 .gpu.pmic = &tps659038,
419
b558af81
LP		 420 .eve.value = VDD_EVE_DRA72x,
421 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
422 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
423 .eve.addr = TPS65917_REG_ADDR_SMPS3,
424 .eve.pmic = &tps659038,
8b0d1bbc 425
b558af81 426 .iva.value = VDD_IVA_DRA72x,
8b0d1bbc 427 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
b558af81
LP		 428 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
429 .iva.addr = TPS65917_REG_ADDR_SMPS3,
8b0d1bbc
K		 430 .iva.pmic = &tps659038,
431};
432
ee9447bf
S		 433/*
434 * Enable essential clock domains, modules and
435 * do some additional special settings needed
436 */
437void enable_basic_clocks(void)
438{
439 u32 const clk_domains_essential[] = {
440 (*prcm)->cm_l4per_clkstctrl,
441 (*prcm)->cm_l3init_clkstctrl,
442 (*prcm)->cm_memif_clkstctrl,
443 (*prcm)->cm_l4cfg_clkstctrl,
f986d972
M		 444#ifdef CONFIG_DRIVER_TI_CPSW
445 (*prcm)->cm_gmac_clkstctrl,
446#endif
ee9447bf
S		 447 0
448 };
449
450 u32 const clk_modules_hw_auto_essential[] = {
d4e4129c 451 (*prcm)->cm_l3_gpmc_clkctrl,
ee9447bf
S		 452 (*prcm)->cm_memif_emif_1_clkctrl,
453 (*prcm)->cm_memif_emif_2_clkctrl,
454 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
455 (*prcm)->cm_wkup_gpio1_clkctrl,
456 (*prcm)->cm_l4per_gpio2_clkctrl,
457 (*prcm)->cm_l4per_gpio3_clkctrl,
458 (*prcm)->cm_l4per_gpio4_clkctrl,
459 (*prcm)->cm_l4per_gpio5_clkctrl,
460 (*prcm)->cm_l4per_gpio6_clkctrl,
87bd05d7
AL		 461 (*prcm)->cm_l4per_gpio7_clkctrl,
462 (*prcm)->cm_l4per_gpio8_clkctrl,
4564faea 463#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
d3cfcb3e
KVA		 464 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
465 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
466#endif
ee9447bf
S		 467 0
468 };
469
470 u32 const clk_modules_explicit_en_essential[] = {
471 (*prcm)->cm_wkup_gptimer1_clkctrl,
472 (*prcm)->cm_l3init_hsmmc1_clkctrl,
473 (*prcm)->cm_l3init_hsmmc2_clkctrl,
474 (*prcm)->cm_l4per_gptimer2_clkctrl,
475 (*prcm)->cm_wkup_wdtimer2_clkctrl,
476 (*prcm)->cm_l4per_uart3_clkctrl,
477 (*prcm)->cm_l4per_i2c1_clkctrl,
f986d972
M		 478#ifdef CONFIG_DRIVER_TI_CPSW
479 (*prcm)->cm_gmac_gmac_clkctrl,
480#endif
c97a9b32
MP		 481
482#ifdef CONFIG_TI_QSPI
483 (*prcm)->cm_l4per_qspi_clkctrl,
484#endif
ee9447bf
S		 485 0
486 };
487
488 /* Enable optional additional functional clock for GPIO4 */
489 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
490 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
491
492 /* Enable 96 MHz clock for MMC1 & MMC2 */
493 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
494 HSMMC_CLKCTRL_CLKSEL_MASK);
495 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
496 HSMMC_CLKCTRL_CLKSEL_MASK);
497
4564faea 498#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
d3cfcb3e
KVA		 499 /* Enable 960 MHz clock for dwc3 */
500 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
501 OPTFCLKEN_REFCLK960M);
502
503 /* Enable 32 KHz clock for dwc3 */
504 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
505 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
506#endif
507
ee9447bf
S		 508 /* Set the correct clock dividers for mmc */
509 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
510 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
511 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
512 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
513
514 /* Select 32KHz clock as the source of GPTIMER1 */
515 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
516 GPTIMER1_CLKCTRL_CLKSEL_MASK);
517
518 do_enable_clocks(clk_domains_essential,
519 clk_modules_hw_auto_essential,
520 clk_modules_explicit_en_essential,
521 1);
522
c97a9b32
MP		 523#ifdef CONFIG_TI_QSPI
524 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
525#endif
526
ee9447bf
S		 527 /* Enable SCRM OPT clocks for PER and CORE dpll */
528 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
529 OPTFCLKEN_SCRM_PER_MASK);
530 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
531 OPTFCLKEN_SCRM_CORE_MASK);
532}
533
534void enable_basic_uboot_clocks(void)
535{
536 u32 const clk_domains_essential[] = {
37be54fd
LV		 537#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
538 (*prcm)->cm_ipu_clkstctrl,
539#endif
ee9447bf
S		 540 0
541 };
542
543 u32 const clk_modules_hw_auto_essential[] = {
2bcc785a 544 (*prcm)->cm_l3init_hsusbtll_clkctrl,
ee9447bf
S		 545 0
546 };
547
548 u32 const clk_modules_explicit_en_essential[] = {
549 (*prcm)->cm_l4per_mcspi1_clkctrl,
550 (*prcm)->cm_l4per_i2c2_clkctrl,
551 (*prcm)->cm_l4per_i2c3_clkctrl,
552 (*prcm)->cm_l4per_i2c4_clkctrl,
37be54fd
LV		 553#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
554 (*prcm)->cm_ipu_i2c5_clkctrl,
555#else
3935277d 556 (*prcm)->cm_l4per_i2c5_clkctrl,
37be54fd 557#endif
ee9447bf
S		 558 (*prcm)->cm_l3init_hsusbhost_clkctrl,
559 (*prcm)->cm_l3init_fsusb_clkctrl,
560 0
561 };
ee9447bf
S		 562 do_enable_clocks(clk_domains_essential,
563 clk_modules_hw_auto_essential,
564 clk_modules_explicit_en_essential,
565 1);
566}
567
ef1697e9
LV		 568const struct ctrl_ioregs ioregs_omap5430 = {
569 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
570 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
571 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
572 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
573 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
574};
575
576const struct ctrl_ioregs ioregs_omap5432_es1 = {
577 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
578 .ctrl_lpddr2ch = 0x0,
579 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
580 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
581 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
582 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
583 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
6c70935d 584 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
ef1697e9
LV		 585};
586
9100edec
LV		 587const struct ctrl_ioregs ioregs_omap5432_es2 = {
588 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
589 .ctrl_lpddr2ch = 0x0,
590 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
591 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
592 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
593 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
594 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
6c70935d 595 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
9100edec
LV		 596};
597
92b0482c
S		 598const struct ctrl_ioregs ioregs_dra7xx_es1 = {
599 .ctrl_ddrch = 0x40404040,
600 .ctrl_lpddr2ch = 0x40404040,
601 .ctrl_ddr3ch = 0x80808080,
536d8747
LV		 602 .ctrl_ddrio_0 = 0x00094A40,
603 .ctrl_ddrio_1 = 0x04A52000,
92b0482c 604 .ctrl_ddrio_2 = 0x84210000,
536d8747
LV		 605 .ctrl_emif_sdram_config_ext = 0x0001C127,
606 .ctrl_emif_sdram_config_ext_final = 0x0001C127,
92b0482c
S		 607 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
608};
609
681f785f
S		 610const struct ctrl_ioregs ioregs_dra72x_es1 = {
611 .ctrl_ddrch = 0x40404040,
612 .ctrl_lpddr2ch = 0x40404040,
613 .ctrl_ddr3ch = 0x60606080,
536d8747
LV		 614 .ctrl_ddrio_0 = 0x00094A40,
615 .ctrl_ddrio_1 = 0x04A52000,
681f785f 616 .ctrl_ddrio_2 = 0x84210000,
536d8747
LV		 617 .ctrl_emif_sdram_config_ext = 0x0001C127,
618 .ctrl_emif_sdram_config_ext_final = 0x0001C127,
681f785f
S		 619 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
620};
621
29bc86ad 622void __weak hw_data_init(void)
01b753ff 623{
ee9447bf
S		 624 u32 omap_rev = omap_revision();
625
626 switch (omap_rev) {
627
628 case OMAP5430_ES1_0:
ee9447bf
S		 629 case OMAP5432_ES1_0:
630 *prcm = &omap5_es1_prcm;
631 *dplls_data = &omap5_dplls_es1;
47abc3df 632 *omap_vcores = &omap5430_volts;
8b12f177 633 *ctrl = &omap5_ctrl;
ee9447bf
S		 634 break;
635
afc2f9dc
S		 636 case OMAP5430_ES2_0:
637 case OMAP5432_ES2_0:
638 *prcm = &omap5_es2_prcm;
47abc3df
S		 639 *dplls_data = &omap5_dplls_es2;
640 *omap_vcores = &omap5430_volts_es2;
8b12f177 641 *ctrl = &omap5_ctrl;
afc2f9dc
S		 642 break;
643
d4e4129c 644 case DRA752_ES1_0:
3ac8c0bf 645 case DRA752_ES1_1:
d4e4129c 646 *prcm = &dra7xx_prcm;
ea8eff1f 647 *dplls_data = &dra7xx_dplls;
63fc0c77 648 *omap_vcores = &dra752_volts;
8b12f177 649 *ctrl = &dra7xx_ctrl;
d4e4129c
LV		 650 break;
651
4d6bf554
LV		 652 case DRA722_ES1_0:
653 *prcm = &dra7xx_prcm;
681f785f 654 *dplls_data = &dra72x_dplls;
4d6bf554
LV		 655 *omap_vcores = &dra722_volts;
656 *ctrl = &dra7xx_ctrl;
657 break;
658
ee9447bf
S		 659 default:
660 printf("\n INVALID OMAP REVISION ");
661 }
01b753ff 662}
ef1697e9
LV		 663
664void get_ioregs(const struct ctrl_ioregs **regs)
665{
666 u32 omap_rev = omap_revision();
667
668 switch (omap_rev) {
669 case OMAP5430_ES1_0:
9100edec 670 case OMAP5430_ES2_0:
ef1697e9 671 *regs = &ioregs_omap5430;
92b0482c 672 break;
ef1697e9
LV		 673 case OMAP5432_ES1_0:
674 *regs = &ioregs_omap5432_es1;
92b0482c 675 break;
9100edec
LV		 676 case OMAP5432_ES2_0:
677 *regs = &ioregs_omap5432_es2;
92b0482c
S		 678 break;
679 case DRA752_ES1_0:
3ac8c0bf 680 case DRA752_ES1_1:
92b0482c
S		 681 *regs = &ioregs_dra7xx_es1;
682 break;
681f785f
S		 683 case DRA722_ES1_0:
684 *regs = &ioregs_dra72x_es1;
685 break;
ef1697e9
LV		 686
687 default:
688 printf("\n INVALID OMAP REVISION ");
689 }
690}
"Das U-Boot" Source Tree