[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / board.c

/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>

#include <linux/compiler.h>

struct fel_stash {
	uint32_t sp;
	uint32_t lr;
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
};

struct fel_stash fel_stash __attribute__((section(".data")));

static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
#else
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
#endif
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

void spl_board_load_image(void)
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);
}

void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
	/* Magic (undocmented) value taken from boot0, without this DRAM
	 * access gets messed up (seems cache related) */
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if defined CONFIG_MACH_SUN6I || \
    defined CONFIG_MACH_SUN7I || \
    defined CONFIG_MACH_SUN8I
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n");
#endif

	clock_init();
	timer_init();
	gpio_init();
	i2c_init_board();
}

#ifdef CONFIG_SPL_BUILD
/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 * Unfortunately we can't check how SPL was loaded so assume
 * it's always the first SD/MMC controller
 */
u32 spl_boot_device(void)
{
	/*
	 * When booting from the SD card, the "eGON.BT0" signature is expected
	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
	 * tool, which generates this header).
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
	 * This branch is just making a decision at runtime whether to load
	 * the main u-boot binary from the SD card (if the "eGON.BT0" signature
	 * is found) or return to the FEL code in the BROM to wait and receive
	 * the main u-boot binary over USB.
	 */
	if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
		return BOOT_DEVICE_MMC1;
	else
		return BOOT_DEVICE_BOARD;
}

/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
	return MMCSD_MODE_RAW;
}

void board_init_f(ulong dummy)
{
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	board_init_r(NULL, 0);
}
#endif

void reset_cpu(ulong addr)
{
#ifdef CONFIG_SUNXI_GEN_SUN4I
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
	while (1) { }
#endif
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#ifdef CONFIG_CMD_NET
/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
	__maybe_unused int rc;

#ifdef CONFIG_MACPWR
	gpio_request(CONFIG_MACPWR, "macpwr");
	gpio_direction_output(CONFIG_MACPWR, 1);
	mdelay(200);
#endif

#ifdef CONFIG_SUNXI_GMAC
	rc = sunxi_gmac_initialize(bis);
	if (rc < 0) {
		printf("sunxi: failed to initialize gmac\n");
		return rc;
	}
#endif

	return 0;
}
#endif
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Some init for sunxi platform.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
6620377e	14	#include <i2c.h>
cba69eee IC	15	#include <serial.h>
	16	#ifdef CONFIG_SPL_BUILD
	17	#include <spl.h>
	18	#endif
	19	#include <asm/gpio.h>
	20	#include <asm/io.h>
	21	#include <asm/arch/clock.h>
	22	#include <asm/arch/gpio.h>
	23	#include <asm/arch/sys_proto.h>
	24	#include <asm/arch/timer.h>
	25
799aff38 IC	26	#include <linux/compiler.h>
799aff38 IC	27
942cb0b6 SG	28	struct fel_stash {
	29	uint32_t sp;
	30	uint32_t lr;
840fe95c SS	31	uint32_t cpsr;
	32	uint32_t sctlr;
	33	uint32_t vbar;
	34	uint32_t cr;
942cb0b6 SG	35	};
	36
	37	struct fel_stash fel_stash __attribute__((section(".data")));
	38
f630974c	39	static int gpio_init(void)
cba69eee	40	{
ff2b47f6	41	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
ed41e62f	42	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
ff2b47f6 CYT	43	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	44	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	45	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	46	#endif
487b3277 PK	47	#if defined(CONFIG_MACH_SUN8I)
	48	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
	49	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
	50	#else
	51	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
	52	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
	53	#endif
ff2b47f6	54	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
ed41e62f	55	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I))
487b3277 PK	56	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
487b3277 PK	57	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
ea520947	58	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
ed41e62f	59	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	60	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
487b3277 PK	61	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
ea520947	62	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
ed41e62f	63	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
487b3277 PK	64	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
487b3277 PK	65	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
77115397	66	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
1871a8ca HG	67	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	68	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	69	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	70	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
ed41e62f	71	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	72	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
487b3277 PK	73	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
ea520947	74	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
5cd83b11 LI	75	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	76	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	77	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	78	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
ed41e62f	79	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
487b3277 PK	80	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
487b3277 PK	81	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
c757a50b	82	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	83	#else
	84	#error Unsupported console port number. Please fix pin mux settings in board.c
	85	#endif
cba69eee IC	86
	87	return 0;
	88	}
	89
942cb0b6 SG	90	void spl_board_load_image(void)
	91	{
	92	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	93	return_to_fel(fel_stash.sp, fel_stash.lr);
	94	}
	95
b56f6e2b	96	void s_init(void)
f630974c	97	{
5e6bacdb	98	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_A23
f630974c SG	99	/* Magic (undocmented) value taken from boot0, without this DRAM
	100	* access gets messed up (seems cache related) */
	101	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	102	#endif
92bcc6cb HG	103	#if defined CONFIG_MACH_SUN6I \|\| \
	104	defined CONFIG_MACH_SUN7I \|\| \
	105	defined CONFIG_MACH_SUN8I
f630974c SG	106	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	107	asm volatile(
	108	"mrc p15, 0, r0, c1, c0, 1\n"
	109	"orr r0, r0, #1 << 6\n"
	110	"mcr p15, 0, r0, c1, c0, 1\n");
	111	#endif
	112
	113	clock_init();
	114	timer_init();
	115	gpio_init();
	116	i2c_init_board();
b56f6e2b	117	}
f630974c	118
b56f6e2b HG	119	#ifdef CONFIG_SPL_BUILD
	120	/* The sunxi internal brom will try to loader external bootloader
	121	* from mmc0, nand flash, mmc2.
da9971d1 IC	122	* Unfortunately we can't check how SPL was loaded so assume
da9971d1 IC	123	* it's always the first SD/MMC controller
b56f6e2b HG	124	*/
	125	u32 spl_boot_device(void)
	126	{
840fe95c SS	127	/*
	128	* When booting from the SD card, the "eGON.BT0" signature is expected
	129	* to be found in memory at the address 0x0004 (see the "mksunxiboot"
	130	* tool, which generates this header).
	131	*
	132	* When booting in the FEL mode over USB, this signature is patched in
	133	* memory and replaced with something else by the 'fel' tool. This other
	134	* signature is selected in such a way, that it can't be present in a
	135	* valid bootable SD card image (because the BROM would refuse to
	136	* execute the SPL in this case).
	137	*
	138	* This branch is just making a decision at runtime whether to load
	139	* the main u-boot binary from the SD card (if the "eGON.BT0" signature
	140	* is found) or return to the FEL code in the BROM to wait and receive
	141	* the main u-boot binary over USB.
	142	*/
	143	if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
	144	return BOOT_DEVICE_MMC1;
	145	else
942cb0b6	146	return BOOT_DEVICE_BOARD;
b56f6e2b HG	147	}
	148
	149	/* No confirmation data available in SPL yet. Hardcode bootmode */
	150	u32 spl_boot_mode(void)
	151	{
	152	return MMCSD_MODE_RAW;
	153	}
	154
	155	void board_init_f(ulong dummy)
	156	{
f630974c SG	157	preloader_console_init();
	158
	159	#ifdef CONFIG_SPL_I2C_SUPPORT
	160	/* Needed early by sunxi_board_init if PMU is enabled */
	161	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	162	#endif
	163	sunxi_board_init();
	164
	165	/* Clear the BSS. */
	166	memset(__bss_start, 0, __bss_end - __bss_start);
	167
	168	board_init_r(NULL, 0);
	169	}
	170	#endif
	171
cba69eee IC	172	void reset_cpu(ulong addr)
cba69eee IC	173	{
44d8ae5b	174	#ifdef CONFIG_SUNXI_GEN_SUN4I
c7e79dec HG	175	static const struct sunxi_wdog *wdog =
	176	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	177
	178	/* Set the watchdog for its shortest interval (.5s) and wait */
	179	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	180	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	181
	182	while (1) {
	183	/* sun5i sometimes gets stuck without this */
	184	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	185	}
44d8ae5b HG	186	#endif
44d8ae5b HG	187	#ifdef CONFIG_SUNXI_GEN_SUN6I
78c396a1 CYT	188	static const struct sunxi_wdog *wdog =
	189	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	190
	191	/* Set the watchdog for its shortest interval (.5s) and wait */
	192	writel(WDT_CFG_RESET, &wdog->cfg);
	193	writel(WDT_MODE_EN, &wdog->mode);
	194	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
fc175434	195	while (1) { }
78c396a1	196	#endif
cba69eee IC	197	}
cba69eee IC	198
cba69eee IC	199	#ifndef CONFIG_SYS_DCACHE_OFF
	200	void enable_caches(void)
	201	{
	202	/* Enable D-cache. I-cache is already enabled in start.S */
	203	dcache_enable();
	204	}
	205	#endif
5835823d IC	206
	207	#ifdef CONFIG_CMD_NET
	208	/*
	209	* Initializes on-chip ethernet controllers.
	210	* to override, implement board_eth_init()
	211	*/
	212	int cpu_eth_init(bd_t *bis)
	213	{
799aff38	214	__maybe_unused int rc;
5835823d	215
fc703001	216	#ifdef CONFIG_MACPWR
8aeed956	217	gpio_request(CONFIG_MACPWR, "macpwr");
fc703001 HG	218	gpio_direction_output(CONFIG_MACPWR, 1);
	219	mdelay(200);
	220	#endif
	221
5835823d IC	222	#ifdef CONFIG_SUNXI_GMAC
	223	rc = sunxi_gmac_initialize(bis);
	224	if (rc < 0) {
	225	printf("sunxi: failed to initialize gmac\n");
	226	return rc;
	227	}
	228	#endif
	229
	230	return 0;
	231	}
	232	#endif