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44303dfa MS |
1 | /* |
2 | * dts file for Xilinx ZynqMP | |
3 | * | |
4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
5 | * | |
6 | * Michal Simek <michal.simek@xilinx.com> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
91d11536 | 10 | |
44303dfa MS |
11 | / { |
12 | compatible = "xlnx,zynqmp"; | |
13 | #address-cells = <2>; | |
85d1142e | 14 | #size-cells = <2>; |
44303dfa MS |
15 | |
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
585ca873 | 20 | cpu0: cpu@0 { |
44303dfa MS |
21 | compatible = "arm,cortex-a53", "arm,armv8"; |
22 | device_type = "cpu"; | |
23 | enable-method = "psci"; | |
941f61fe | 24 | operating-points-v2 = <&cpu_opp_table>; |
44303dfa | 25 | reg = <0x0>; |
2e15b071 | 26 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
27 | }; |
28 | ||
585ca873 | 29 | cpu1: cpu@1 { |
44303dfa MS |
30 | compatible = "arm,cortex-a53", "arm,armv8"; |
31 | device_type = "cpu"; | |
32 | enable-method = "psci"; | |
33 | reg = <0x1>; | |
941f61fe | 34 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 | 35 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
36 | }; |
37 | ||
585ca873 | 38 | cpu2: cpu@2 { |
44303dfa MS |
39 | compatible = "arm,cortex-a53", "arm,armv8"; |
40 | device_type = "cpu"; | |
41 | enable-method = "psci"; | |
42 | reg = <0x2>; | |
941f61fe | 43 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 | 44 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
45 | }; |
46 | ||
585ca873 | 47 | cpu3: cpu@3 { |
44303dfa MS |
48 | compatible = "arm,cortex-a53", "arm,armv8"; |
49 | device_type = "cpu"; | |
50 | enable-method = "psci"; | |
51 | reg = <0x3>; | |
941f61fe | 52 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 SK |
53 | cpu-idle-states = <&CPU_SLEEP_0>; |
54 | }; | |
55 | ||
56 | idle-states { | |
fec54739 | 57 | entry-method = "arm,psci"; |
2e15b071 SK |
58 | |
59 | CPU_SLEEP_0: cpu-sleep-0 { | |
60 | compatible = "arm,idle-state"; | |
61 | arm,psci-suspend-param = <0x40000000>; | |
62 | local-timer-stop; | |
63 | entry-latency-us = <300>; | |
64 | exit-latency-us = <600>; | |
6a097b0d | 65 | min-residency-us = <10000>; |
2e15b071 | 66 | }; |
44303dfa MS |
67 | }; |
68 | }; | |
69 | ||
941f61fe SD |
70 | cpu_opp_table: cpu_opp_table { |
71 | compatible = "operating-points-v2"; | |
72 | opp-shared; | |
73 | opp00 { | |
74 | opp-hz = /bits/ 64 <1199999988>; | |
75 | opp-microvolt = <1000000>; | |
76 | clock-latency-ns = <500000>; | |
77 | }; | |
78 | opp01 { | |
79 | opp-hz = /bits/ 64 <599999994>; | |
80 | opp-microvolt = <1000000>; | |
81 | clock-latency-ns = <500000>; | |
82 | }; | |
83 | opp02 { | |
84 | opp-hz = /bits/ 64 <399999996>; | |
85 | opp-microvolt = <1000000>; | |
86 | clock-latency-ns = <500000>; | |
87 | }; | |
88 | opp03 { | |
89 | opp-hz = /bits/ 64 <299999997>; | |
90 | opp-microvolt = <1000000>; | |
91 | clock-latency-ns = <500000>; | |
92 | }; | |
93 | }; | |
94 | ||
69d09dd7 MS |
95 | dcc: dcc { |
96 | compatible = "arm,dcc"; | |
97 | status = "disabled"; | |
98 | u-boot,dm-pre-reloc; | |
99 | }; | |
100 | ||
8f4e3972 SB |
101 | power-domains { |
102 | compatible = "xlnx,zynqmp-genpd"; | |
103 | ||
104 | pd_usb0: pd-usb0 { | |
105 | #power-domain-cells = <0x0>; | |
106 | pd-id = <0x16>; | |
107 | }; | |
108 | ||
109 | pd_usb1: pd-usb1 { | |
110 | #power-domain-cells = <0x0>; | |
111 | pd-id = <0x17>; | |
112 | }; | |
113 | ||
114 | pd_sata: pd-sata { | |
115 | #power-domain-cells = <0x0>; | |
116 | pd-id = <0x1c>; | |
117 | }; | |
118 | ||
119 | pd_spi0: pd-spi0 { | |
120 | #power-domain-cells = <0x0>; | |
121 | pd-id = <0x23>; | |
122 | }; | |
123 | ||
124 | pd_spi1: pd-spi1 { | |
125 | #power-domain-cells = <0x0>; | |
126 | pd-id = <0x24>; | |
127 | }; | |
128 | ||
129 | pd_uart0: pd-uart0 { | |
130 | #power-domain-cells = <0x0>; | |
131 | pd-id = <0x21>; | |
132 | }; | |
133 | ||
134 | pd_uart1: pd-uart1 { | |
135 | #power-domain-cells = <0x0>; | |
136 | pd-id = <0x22>; | |
137 | }; | |
138 | ||
139 | pd_eth0: pd-eth0 { | |
140 | #power-domain-cells = <0x0>; | |
141 | pd-id = <0x1d>; | |
142 | }; | |
143 | ||
144 | pd_eth1: pd-eth1 { | |
145 | #power-domain-cells = <0x0>; | |
146 | pd-id = <0x1e>; | |
147 | }; | |
148 | ||
149 | pd_eth2: pd-eth2 { | |
150 | #power-domain-cells = <0x0>; | |
151 | pd-id = <0x1f>; | |
152 | }; | |
153 | ||
154 | pd_eth3: pd-eth3 { | |
155 | #power-domain-cells = <0x0>; | |
156 | pd-id = <0x20>; | |
157 | }; | |
158 | ||
159 | pd_i2c0: pd-i2c0 { | |
160 | #power-domain-cells = <0x0>; | |
161 | pd-id = <0x25>; | |
162 | }; | |
163 | ||
164 | pd_i2c1: pd-i2c1 { | |
165 | #power-domain-cells = <0x0>; | |
166 | pd-id = <0x26>; | |
167 | }; | |
168 | ||
169 | pd_dp: pd-dp { | |
8f4e3972 SB |
170 | #power-domain-cells = <0x0>; |
171 | pd-id = <0x29>; | |
172 | }; | |
173 | ||
174 | pd_gdma: pd-gdma { | |
175 | #power-domain-cells = <0x0>; | |
176 | pd-id = <0x2a>; | |
177 | }; | |
178 | ||
179 | pd_adma: pd-adma { | |
180 | #power-domain-cells = <0x0>; | |
181 | pd-id = <0x2b>; | |
182 | }; | |
183 | ||
184 | pd_ttc0: pd-ttc0 { | |
185 | #power-domain-cells = <0x0>; | |
186 | pd-id = <0x18>; | |
187 | }; | |
188 | ||
189 | pd_ttc1: pd-ttc1 { | |
190 | #power-domain-cells = <0x0>; | |
191 | pd-id = <0x19>; | |
192 | }; | |
193 | ||
194 | pd_ttc2: pd-ttc2 { | |
195 | #power-domain-cells = <0x0>; | |
196 | pd-id = <0x1a>; | |
197 | }; | |
198 | ||
199 | pd_ttc3: pd-ttc3 { | |
200 | #power-domain-cells = <0x0>; | |
201 | pd-id = <0x1b>; | |
202 | }; | |
203 | ||
204 | pd_sd0: pd-sd0 { | |
205 | #power-domain-cells = <0x0>; | |
206 | pd-id = <0x27>; | |
207 | }; | |
208 | ||
209 | pd_sd1: pd-sd1 { | |
210 | #power-domain-cells = <0x0>; | |
211 | pd-id = <0x28>; | |
212 | }; | |
213 | ||
214 | pd_nand: pd-nand { | |
215 | #power-domain-cells = <0x0>; | |
216 | pd-id = <0x2c>; | |
217 | }; | |
218 | ||
219 | pd_qspi: pd-qspi { | |
220 | #power-domain-cells = <0x0>; | |
221 | pd-id = <0x2d>; | |
222 | }; | |
223 | ||
224 | pd_gpio: pd-gpio { | |
225 | #power-domain-cells = <0x0>; | |
226 | pd-id = <0x2e>; | |
227 | }; | |
228 | ||
229 | pd_can0: pd-can0 { | |
230 | #power-domain-cells = <0x0>; | |
231 | pd-id = <0x2f>; | |
232 | }; | |
233 | ||
234 | pd_can1: pd-can1 { | |
235 | #power-domain-cells = <0x0>; | |
236 | pd-id = <0x30>; | |
237 | }; | |
2af3932f FD |
238 | |
239 | pd_pcie: pd-pcie { | |
240 | #power-domain-cells = <0x0>; | |
241 | pd-id = <0x3b>; | |
242 | }; | |
243 | ||
244 | pd_gpu: pd-gpu { | |
245 | #power-domain-cells = <0x0>; | |
a4d7d560 | 246 | pd-id = <0x3a 0x14 0x15>; |
2af3932f | 247 | }; |
8f4e3972 SB |
248 | }; |
249 | ||
44303dfa MS |
250 | pmu { |
251 | compatible = "arm,armv8-pmuv3"; | |
14cd9eab | 252 | interrupt-parent = <&gic>; |
44303dfa MS |
253 | interrupts = <0 143 4>, |
254 | <0 144 4>, | |
255 | <0 145 4>, | |
256 | <0 146 4>; | |
257 | }; | |
258 | ||
259 | psci { | |
260 | compatible = "arm,psci-0.2"; | |
261 | method = "smc"; | |
262 | }; | |
263 | ||
264 | firmware { | |
265 | compatible = "xlnx,zynqmp-pm"; | |
266 | method = "smc"; | |
19ee402d SB |
267 | interrupt-parent = <&gic>; |
268 | interrupts = <0 35 4>; | |
44303dfa MS |
269 | }; |
270 | ||
271 | timer { | |
272 | compatible = "arm,armv8-timer"; | |
273 | interrupt-parent = <&gic>; | |
6db82e09 MS |
274 | interrupts = <1 13 0xf08>, |
275 | <1 14 0xf08>, | |
276 | <1 11 0xf08>, | |
277 | <1 10 0xf08>; | |
44303dfa MS |
278 | }; |
279 | ||
aaf232f3 NSR |
280 | edac { |
281 | compatible = "arm,cortex-a53-edac"; | |
282 | }; | |
283 | ||
7689dce7 NM |
284 | fpga_full: fpga-full { |
285 | compatible = "fpga-region"; | |
286 | fpga-mgr = <&pcap>; | |
287 | #address-cells = <2>; | |
288 | #size-cells = <2>; | |
289 | }; | |
290 | ||
0d87c4fd NM |
291 | nvmem_firmware { |
292 | compatible = "xlnx,zynqmp-nvmem-fw"; | |
293 | #address-cells = <1>; | |
294 | #size-cells = <1>; | |
295 | ||
296 | soc_revision: soc_revision@0 { | |
297 | reg = <0x0 0x4>; | |
298 | }; | |
299 | }; | |
300 | ||
7689dce7 | 301 | pcap: pcap { |
d64e43f1 NM |
302 | compatible = "xlnx,zynqmp-pcap-fpga"; |
303 | }; | |
304 | ||
98ad47bf AKV |
305 | rst: reset-controller { |
306 | compatible = "xlnx,zynqmp-reset"; | |
307 | #reset-cells = <1>; | |
308 | }; | |
309 | ||
c926e6fb | 310 | amba_apu: amba_apu@0 { |
44303dfa MS |
311 | compatible = "simple-bus"; |
312 | #address-cells = <2>; | |
313 | #size-cells = <1>; | |
85d1142e | 314 | ranges = <0 0 0 0 0xffffffff>; |
44303dfa MS |
315 | |
316 | gic: interrupt-controller@f9010000 { | |
317 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
318 | #interrupt-cells = <3>; | |
319 | reg = <0x0 0xf9010000 0x10000>, | |
0a8c4f67 | 320 | <0x0 0xf9020000 0x20000>, |
44303dfa | 321 | <0x0 0xf9040000 0x20000>, |
0a8c4f67 | 322 | <0x0 0xf9060000 0x20000>; |
44303dfa MS |
323 | interrupt-controller; |
324 | interrupt-parent = <&gic>; | |
325 | interrupts = <1 9 0xf04>; | |
326 | }; | |
327 | }; | |
328 | ||
b976fd63 | 329 | amba: amba { |
44303dfa | 330 | compatible = "simple-bus"; |
c9811e14 | 331 | u-boot,dm-pre-reloc; |
44303dfa | 332 | #address-cells = <2>; |
b976fd63 MS |
333 | #size-cells = <2>; |
334 | ranges; | |
44303dfa MS |
335 | |
336 | can0: can@ff060000 { | |
337 | compatible = "xlnx,zynq-can-1.0"; | |
338 | status = "disabled"; | |
339 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 340 | reg = <0x0 0xff060000 0x0 0x1000>; |
44303dfa MS |
341 | interrupts = <0 23 4>; |
342 | interrupt-parent = <&gic>; | |
343 | tx-fifo-depth = <0x40>; | |
344 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 345 | power-domains = <&pd_can0>; |
44303dfa MS |
346 | }; |
347 | ||
348 | can1: can@ff070000 { | |
349 | compatible = "xlnx,zynq-can-1.0"; | |
350 | status = "disabled"; | |
351 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 352 | reg = <0x0 0xff070000 0x0 0x1000>; |
44303dfa MS |
353 | interrupts = <0 24 4>; |
354 | interrupt-parent = <&gic>; | |
355 | tx-fifo-depth = <0x40>; | |
356 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 357 | power-domains = <&pd_can1>; |
44303dfa MS |
358 | }; |
359 | ||
ff50d21b MS |
360 | cci: cci@fd6e0000 { |
361 | compatible = "arm,cci-400"; | |
b976fd63 | 362 | reg = <0x0 0xfd6e0000 0x0 0x9000>; |
ff50d21b MS |
363 | ranges = <0x0 0x0 0xfd6e0000 0x10000>; |
364 | #address-cells = <1>; | |
365 | #size-cells = <1>; | |
366 | ||
367 | pmu@9000 { | |
368 | compatible = "arm,cci-400-pmu,r1"; | |
369 | reg = <0x9000 0x5000>; | |
370 | interrupt-parent = <&gic>; | |
371 | interrupts = <0 123 4>, | |
372 | <0 123 4>, | |
373 | <0 123 4>, | |
374 | <0 123 4>, | |
375 | <0 123 4>; | |
376 | }; | |
377 | }; | |
378 | ||
44303dfa MS |
379 | /* GDMA */ |
380 | fpd_dma_chan1: dma@fd500000 { | |
381 | status = "disabled"; | |
382 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 383 | reg = <0x0 0xfd500000 0x0 0x1000>; |
44303dfa MS |
384 | interrupt-parent = <&gic>; |
385 | interrupts = <0 124 4>; | |
b34d11de | 386 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 387 | xlnx,bus-width = <128>; |
ba6ad317 MS |
388 | #stream-id-cells = <1>; |
389 | iommus = <&smmu 0x14e8>; | |
8f4e3972 | 390 | power-domains = <&pd_gdma>; |
44303dfa MS |
391 | }; |
392 | ||
393 | fpd_dma_chan2: dma@fd510000 { | |
394 | status = "disabled"; | |
395 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 396 | reg = <0x0 0xfd510000 0x0 0x1000>; |
44303dfa MS |
397 | interrupt-parent = <&gic>; |
398 | interrupts = <0 125 4>; | |
b34d11de | 399 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 400 | xlnx,bus-width = <128>; |
ba6ad317 MS |
401 | #stream-id-cells = <1>; |
402 | iommus = <&smmu 0x14e9>; | |
8f4e3972 | 403 | power-domains = <&pd_gdma>; |
44303dfa MS |
404 | }; |
405 | ||
406 | fpd_dma_chan3: dma@fd520000 { | |
407 | status = "disabled"; | |
408 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 409 | reg = <0x0 0xfd520000 0x0 0x1000>; |
44303dfa MS |
410 | interrupt-parent = <&gic>; |
411 | interrupts = <0 126 4>; | |
b34d11de | 412 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 413 | xlnx,bus-width = <128>; |
ba6ad317 MS |
414 | #stream-id-cells = <1>; |
415 | iommus = <&smmu 0x14ea>; | |
8f4e3972 | 416 | power-domains = <&pd_gdma>; |
44303dfa MS |
417 | }; |
418 | ||
419 | fpd_dma_chan4: dma@fd530000 { | |
420 | status = "disabled"; | |
421 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 422 | reg = <0x0 0xfd530000 0x0 0x1000>; |
44303dfa MS |
423 | interrupt-parent = <&gic>; |
424 | interrupts = <0 127 4>; | |
b34d11de | 425 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 426 | xlnx,bus-width = <128>; |
ba6ad317 MS |
427 | #stream-id-cells = <1>; |
428 | iommus = <&smmu 0x14eb>; | |
8f4e3972 | 429 | power-domains = <&pd_gdma>; |
44303dfa MS |
430 | }; |
431 | ||
432 | fpd_dma_chan5: dma@fd540000 { | |
433 | status = "disabled"; | |
434 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 435 | reg = <0x0 0xfd540000 0x0 0x1000>; |
44303dfa MS |
436 | interrupt-parent = <&gic>; |
437 | interrupts = <0 128 4>; | |
b34d11de | 438 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 439 | xlnx,bus-width = <128>; |
ba6ad317 MS |
440 | #stream-id-cells = <1>; |
441 | iommus = <&smmu 0x14ec>; | |
8f4e3972 | 442 | power-domains = <&pd_gdma>; |
44303dfa MS |
443 | }; |
444 | ||
445 | fpd_dma_chan6: dma@fd550000 { | |
446 | status = "disabled"; | |
447 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 448 | reg = <0x0 0xfd550000 0x0 0x1000>; |
44303dfa MS |
449 | interrupt-parent = <&gic>; |
450 | interrupts = <0 129 4>; | |
b34d11de | 451 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 452 | xlnx,bus-width = <128>; |
ba6ad317 MS |
453 | #stream-id-cells = <1>; |
454 | iommus = <&smmu 0x14ed>; | |
8f4e3972 | 455 | power-domains = <&pd_gdma>; |
44303dfa MS |
456 | }; |
457 | ||
458 | fpd_dma_chan7: dma@fd560000 { | |
459 | status = "disabled"; | |
460 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 461 | reg = <0x0 0xfd560000 0x0 0x1000>; |
44303dfa MS |
462 | interrupt-parent = <&gic>; |
463 | interrupts = <0 130 4>; | |
b34d11de | 464 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 465 | xlnx,bus-width = <128>; |
ba6ad317 MS |
466 | #stream-id-cells = <1>; |
467 | iommus = <&smmu 0x14ee>; | |
8f4e3972 | 468 | power-domains = <&pd_gdma>; |
44303dfa MS |
469 | }; |
470 | ||
471 | fpd_dma_chan8: dma@fd570000 { | |
472 | status = "disabled"; | |
473 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 474 | reg = <0x0 0xfd570000 0x0 0x1000>; |
44303dfa MS |
475 | interrupt-parent = <&gic>; |
476 | interrupts = <0 131 4>; | |
b34d11de | 477 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 478 | xlnx,bus-width = <128>; |
ba6ad317 MS |
479 | #stream-id-cells = <1>; |
480 | iommus = <&smmu 0x14ef>; | |
8f4e3972 | 481 | power-domains = <&pd_gdma>; |
44303dfa MS |
482 | }; |
483 | ||
484 | gpu: gpu@fd4b0000 { | |
485 | status = "disabled"; | |
486 | compatible = "arm,mali-400", "arm,mali-utgard"; | |
834ec8e9 | 487 | reg = <0x0 0xfd4b0000 0x0 0x10000>; |
44303dfa MS |
488 | interrupt-parent = <&gic>; |
489 | interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; | |
490 | interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; | |
59206dd1 | 491 | clock-names = "gpu", "gpu_pp0", "gpu_pp1"; |
2af3932f | 492 | power-domains = <&pd_gpu>; |
44303dfa MS |
493 | }; |
494 | ||
6af57737 KA |
495 | /* LPDDMA default allows only secured access. inorder to enable |
496 | * These dma channels, Users should ensure that these dma | |
497 | * Channels are allowed for non secure access. | |
498 | */ | |
44303dfa MS |
499 | lpd_dma_chan1: dma@ffa80000 { |
500 | status = "disabled"; | |
501 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 502 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 503 | reg = <0x0 0xffa80000 0x0 0x1000>; |
44303dfa MS |
504 | interrupt-parent = <&gic>; |
505 | interrupts = <0 77 4>; | |
44303dfa | 506 | xlnx,bus-width = <64>; |
ba6ad317 MS |
507 | #stream-id-cells = <1>; |
508 | iommus = <&smmu 0x868>; | |
8f4e3972 | 509 | power-domains = <&pd_adma>; |
44303dfa MS |
510 | }; |
511 | ||
512 | lpd_dma_chan2: dma@ffa90000 { | |
513 | status = "disabled"; | |
514 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 515 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 516 | reg = <0x0 0xffa90000 0x0 0x1000>; |
44303dfa MS |
517 | interrupt-parent = <&gic>; |
518 | interrupts = <0 78 4>; | |
44303dfa | 519 | xlnx,bus-width = <64>; |
ba6ad317 MS |
520 | #stream-id-cells = <1>; |
521 | iommus = <&smmu 0x869>; | |
8f4e3972 | 522 | power-domains = <&pd_adma>; |
44303dfa MS |
523 | }; |
524 | ||
525 | lpd_dma_chan3: dma@ffaa0000 { | |
526 | status = "disabled"; | |
527 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 528 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 529 | reg = <0x0 0xffaa0000 0x0 0x1000>; |
44303dfa MS |
530 | interrupt-parent = <&gic>; |
531 | interrupts = <0 79 4>; | |
44303dfa | 532 | xlnx,bus-width = <64>; |
ba6ad317 MS |
533 | #stream-id-cells = <1>; |
534 | iommus = <&smmu 0x86a>; | |
8f4e3972 | 535 | power-domains = <&pd_adma>; |
44303dfa MS |
536 | }; |
537 | ||
538 | lpd_dma_chan4: dma@ffab0000 { | |
539 | status = "disabled"; | |
540 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 541 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 542 | reg = <0x0 0xffab0000 0x0 0x1000>; |
44303dfa MS |
543 | interrupt-parent = <&gic>; |
544 | interrupts = <0 80 4>; | |
44303dfa | 545 | xlnx,bus-width = <64>; |
ba6ad317 MS |
546 | #stream-id-cells = <1>; |
547 | iommus = <&smmu 0x86b>; | |
8f4e3972 | 548 | power-domains = <&pd_adma>; |
44303dfa MS |
549 | }; |
550 | ||
551 | lpd_dma_chan5: dma@ffac0000 { | |
552 | status = "disabled"; | |
553 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 554 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 555 | reg = <0x0 0xffac0000 0x0 0x1000>; |
44303dfa MS |
556 | interrupt-parent = <&gic>; |
557 | interrupts = <0 81 4>; | |
44303dfa | 558 | xlnx,bus-width = <64>; |
ba6ad317 MS |
559 | #stream-id-cells = <1>; |
560 | iommus = <&smmu 0x86c>; | |
8f4e3972 | 561 | power-domains = <&pd_adma>; |
44303dfa MS |
562 | }; |
563 | ||
564 | lpd_dma_chan6: dma@ffad0000 { | |
565 | status = "disabled"; | |
566 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 567 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 568 | reg = <0x0 0xffad0000 0x0 0x1000>; |
44303dfa MS |
569 | interrupt-parent = <&gic>; |
570 | interrupts = <0 82 4>; | |
44303dfa | 571 | xlnx,bus-width = <64>; |
ba6ad317 MS |
572 | #stream-id-cells = <1>; |
573 | iommus = <&smmu 0x86d>; | |
8f4e3972 | 574 | power-domains = <&pd_adma>; |
44303dfa MS |
575 | }; |
576 | ||
577 | lpd_dma_chan7: dma@ffae0000 { | |
578 | status = "disabled"; | |
579 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 580 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 581 | reg = <0x0 0xffae0000 0x0 0x1000>; |
44303dfa MS |
582 | interrupt-parent = <&gic>; |
583 | interrupts = <0 83 4>; | |
44303dfa | 584 | xlnx,bus-width = <64>; |
ba6ad317 MS |
585 | #stream-id-cells = <1>; |
586 | iommus = <&smmu 0x86e>; | |
8f4e3972 | 587 | power-domains = <&pd_adma>; |
44303dfa MS |
588 | }; |
589 | ||
590 | lpd_dma_chan8: dma@ffaf0000 { | |
591 | status = "disabled"; | |
592 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 593 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 594 | reg = <0x0 0xffaf0000 0x0 0x1000>; |
44303dfa MS |
595 | interrupt-parent = <&gic>; |
596 | interrupts = <0 84 4>; | |
44303dfa | 597 | xlnx,bus-width = <64>; |
ba6ad317 MS |
598 | #stream-id-cells = <1>; |
599 | iommus = <&smmu 0x86f>; | |
8f4e3972 | 600 | power-domains = <&pd_adma>; |
44303dfa MS |
601 | }; |
602 | ||
90869009 NSR |
603 | mc: memory-controller@fd070000 { |
604 | compatible = "xlnx,zynqmp-ddrc-2.40a"; | |
b976fd63 | 605 | reg = <0x0 0xfd070000 0x0 0x30000>; |
90869009 NSR |
606 | interrupt-parent = <&gic>; |
607 | interrupts = <0 112 4>; | |
608 | }; | |
609 | ||
44303dfa MS |
610 | nand0: nand@ff100000 { |
611 | compatible = "arasan,nfc-v3p10"; | |
612 | status = "disabled"; | |
b976fd63 | 613 | reg = <0x0 0xff100000 0x0 0x1000>; |
44303dfa MS |
614 | clock-names = "clk_sys", "clk_flash"; |
615 | interrupt-parent = <&gic>; | |
616 | interrupts = <0 14 4>; | |
617 | #address-cells = <2>; | |
618 | #size-cells = <1>; | |
ba6ad317 MS |
619 | #stream-id-cells = <1>; |
620 | iommus = <&smmu 0x872>; | |
8f4e3972 | 621 | power-domains = <&pd_nand>; |
44303dfa MS |
622 | }; |
623 | ||
624 | gem0: ethernet@ff0b0000 { | |
da2ad784 | 625 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
626 | status = "disabled"; |
627 | interrupt-parent = <&gic>; | |
628 | interrupts = <0 57 4>, <0 57 4>; | |
b976fd63 | 629 | reg = <0x0 0xff0b0000 0x0 0x1000>; |
44303dfa MS |
630 | clock-names = "pclk", "hclk", "tx_clk"; |
631 | #address-cells = <1>; | |
632 | #size-cells = <0>; | |
7f1d7d97 | 633 | #stream-id-cells = <1>; |
ba6ad317 | 634 | iommus = <&smmu 0x874>; |
8f4e3972 | 635 | power-domains = <&pd_eth0>; |
44303dfa MS |
636 | }; |
637 | ||
638 | gem1: ethernet@ff0c0000 { | |
da2ad784 | 639 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
640 | status = "disabled"; |
641 | interrupt-parent = <&gic>; | |
642 | interrupts = <0 59 4>, <0 59 4>; | |
b976fd63 | 643 | reg = <0x0 0xff0c0000 0x0 0x1000>; |
44303dfa MS |
644 | clock-names = "pclk", "hclk", "tx_clk"; |
645 | #address-cells = <1>; | |
646 | #size-cells = <0>; | |
7f1d7d97 | 647 | #stream-id-cells = <1>; |
ba6ad317 | 648 | iommus = <&smmu 0x875>; |
8f4e3972 | 649 | power-domains = <&pd_eth1>; |
44303dfa MS |
650 | }; |
651 | ||
652 | gem2: ethernet@ff0d0000 { | |
da2ad784 | 653 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
654 | status = "disabled"; |
655 | interrupt-parent = <&gic>; | |
656 | interrupts = <0 61 4>, <0 61 4>; | |
b976fd63 | 657 | reg = <0x0 0xff0d0000 0x0 0x1000>; |
44303dfa MS |
658 | clock-names = "pclk", "hclk", "tx_clk"; |
659 | #address-cells = <1>; | |
660 | #size-cells = <0>; | |
7f1d7d97 | 661 | #stream-id-cells = <1>; |
ba6ad317 | 662 | iommus = <&smmu 0x876>; |
8f4e3972 | 663 | power-domains = <&pd_eth2>; |
44303dfa MS |
664 | }; |
665 | ||
666 | gem3: ethernet@ff0e0000 { | |
da2ad784 | 667 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
668 | status = "disabled"; |
669 | interrupt-parent = <&gic>; | |
670 | interrupts = <0 63 4>, <0 63 4>; | |
b976fd63 | 671 | reg = <0x0 0xff0e0000 0x0 0x1000>; |
44303dfa MS |
672 | clock-names = "pclk", "hclk", "tx_clk"; |
673 | #address-cells = <1>; | |
674 | #size-cells = <0>; | |
7f1d7d97 | 675 | #stream-id-cells = <1>; |
ba6ad317 | 676 | iommus = <&smmu 0x877>; |
8f4e3972 | 677 | power-domains = <&pd_eth3>; |
44303dfa MS |
678 | }; |
679 | ||
680 | gpio: gpio@ff0a0000 { | |
681 | compatible = "xlnx,zynqmp-gpio-1.0"; | |
682 | status = "disabled"; | |
683 | #gpio-cells = <0x2>; | |
684 | interrupt-parent = <&gic>; | |
685 | interrupts = <0 16 4>; | |
9e826b68 MS |
686 | interrupt-controller; |
687 | #interrupt-cells = <2>; | |
b976fd63 | 688 | reg = <0x0 0xff0a0000 0x0 0x1000>; |
0b33e0b1 | 689 | gpio-controller; |
8f4e3972 | 690 | power-domains = <&pd_gpio>; |
44303dfa MS |
691 | }; |
692 | ||
693 | i2c0: i2c@ff020000 { | |
de4914b4 | 694 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
695 | status = "disabled"; |
696 | interrupt-parent = <&gic>; | |
697 | interrupts = <0 17 4>; | |
b976fd63 | 698 | reg = <0x0 0xff020000 0x0 0x1000>; |
44303dfa MS |
699 | #address-cells = <1>; |
700 | #size-cells = <0>; | |
8f4e3972 | 701 | power-domains = <&pd_i2c0>; |
44303dfa MS |
702 | }; |
703 | ||
704 | i2c1: i2c@ff030000 { | |
de4914b4 | 705 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
706 | status = "disabled"; |
707 | interrupt-parent = <&gic>; | |
708 | interrupts = <0 18 4>; | |
b976fd63 | 709 | reg = <0x0 0xff030000 0x0 0x1000>; |
44303dfa MS |
710 | #address-cells = <1>; |
711 | #size-cells = <0>; | |
8f4e3972 | 712 | power-domains = <&pd_i2c1>; |
44303dfa MS |
713 | }; |
714 | ||
5534480a NSR |
715 | ocm: memory-controller@ff960000 { |
716 | compatible = "xlnx,zynqmp-ocmc-1.0"; | |
b976fd63 | 717 | reg = <0x0 0xff960000 0x0 0x1000>; |
5534480a NSR |
718 | interrupt-parent = <&gic>; |
719 | interrupts = <0 10 4>; | |
720 | }; | |
721 | ||
44303dfa MS |
722 | pcie: pcie@fd0e0000 { |
723 | compatible = "xlnx,nwl-pcie-2.11"; | |
724 | status = "disabled"; | |
725 | #address-cells = <3>; | |
726 | #size-cells = <2>; | |
727 | #interrupt-cells = <1>; | |
7d6ca73a | 728 | msi-controller; |
44303dfa MS |
729 | device_type = "pci"; |
730 | interrupt-parent = <&gic>; | |
91a8b0ee | 731 | interrupts = <0 118 4>, |
7d6ca73a | 732 | <0 117 4>, |
91a8b0ee MS |
733 | <0 116 4>, |
734 | <0 115 4>, /* MSI_1 [63...32] */ | |
735 | <0 114 4>; /* MSI_0 [31...0] */ | |
7d6ca73a BKG |
736 | interrupt-names = "misc","dummy","intx", "msi1", "msi0"; |
737 | msi-parent = <&pcie>; | |
b976fd63 MS |
738 | reg = <0x0 0xfd0e0000 0x0 0x1000>, |
739 | <0x0 0xfd480000 0x0 0x1000>, | |
688d1be5 | 740 | <0x80 0x00000000 0x0 0x1000000>; |
44303dfa | 741 | reg-names = "breg", "pcireg", "cfg"; |
688d1be5 BKG |
742 | ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ |
743 | 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ | |
ec2b2d4c | 744 | bus-range = <0x00 0xff>; |
33aec517 BKG |
745 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
746 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, | |
747 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, | |
748 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, | |
749 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; | |
2af3932f | 750 | power-domains = <&pd_pcie>; |
33aec517 BKG |
751 | pcie_intc: legacy-interrupt-controller { |
752 | interrupt-controller; | |
753 | #address-cells = <0>; | |
754 | #interrupt-cells = <1>; | |
755 | }; | |
44303dfa MS |
756 | }; |
757 | ||
758 | qspi: spi@ff0f0000 { | |
759 | compatible = "xlnx,zynqmp-qspi-1.0"; | |
760 | status = "disabled"; | |
761 | clock-names = "ref_clk", "pclk"; | |
762 | interrupts = <0 15 4>; | |
763 | interrupt-parent = <&gic>; | |
764 | num-cs = <1>; | |
b976fd63 MS |
765 | reg = <0x0 0xff0f0000 0x0 0x1000>, |
766 | <0x0 0xc0000000 0x0 0x8000000>; | |
44303dfa MS |
767 | #address-cells = <1>; |
768 | #size-cells = <0>; | |
ba6ad317 MS |
769 | #stream-id-cells = <1>; |
770 | iommus = <&smmu 0x873>; | |
8f4e3972 | 771 | power-domains = <&pd_qspi>; |
44303dfa MS |
772 | }; |
773 | ||
774 | rtc: rtc@ffa60000 { | |
775 | compatible = "xlnx,zynqmp-rtc"; | |
776 | status = "disabled"; | |
b976fd63 | 777 | reg = <0x0 0xffa60000 0x0 0x100>; |
44303dfa MS |
778 | interrupt-parent = <&gic>; |
779 | interrupts = <0 26 4>, <0 27 4>; | |
780 | interrupt-names = "alarm", "sec"; | |
4d9d6985 | 781 | calibration = <0x8000>; |
44303dfa MS |
782 | }; |
783 | ||
db6c62e1 AKV |
784 | serdes: zynqmp_phy@fd400000 { |
785 | compatible = "xlnx,zynqmp-psgtr"; | |
786 | status = "disabled"; | |
b976fd63 MS |
787 | reg = <0x0 0xfd400000 0x0 0x40000>, |
788 | <0x0 0xfd3d0000 0x0 0x1000>, | |
b976fd63 | 789 | <0x0 0xff5e0000 0x0 0x1000>; |
0aada397 | 790 | reg-names = "serdes", "siou", "lpd"; |
3940bca4 MS |
791 | nvmem-cells = <&soc_revision>; |
792 | nvmem-cell-names = "soc_revision"; | |
98ad47bf AKV |
793 | resets = <&rst 16>, <&rst 59>, <&rst 60>, |
794 | <&rst 61>, <&rst 62>, <&rst 63>, | |
795 | <&rst 64>, <&rst 3>, <&rst 29>, | |
796 | <&rst 30>, <&rst 31>, <&rst 32>; | |
797 | reset-names = "sata_rst", "usb0_crst", "usb1_crst", | |
798 | "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", | |
799 | "usb1_apbrst", "dp_rst", "gem0_rst", | |
800 | "gem1_rst", "gem2_rst", "gem3_rst"; | |
db6c62e1 AKV |
801 | lane0: lane0 { |
802 | #phy-cells = <4>; | |
803 | }; | |
804 | lane1: lane1 { | |
805 | #phy-cells = <4>; | |
806 | }; | |
807 | lane2: lane2 { | |
808 | #phy-cells = <4>; | |
809 | }; | |
810 | lane3: lane3 { | |
811 | #phy-cells = <4>; | |
812 | }; | |
813 | }; | |
814 | ||
44303dfa MS |
815 | sata: ahci@fd0c0000 { |
816 | compatible = "ceva,ahci-1v84"; | |
817 | status = "disabled"; | |
b976fd63 | 818 | reg = <0x0 0xfd0c0000 0x0 0x2000>; |
44303dfa MS |
819 | interrupt-parent = <&gic>; |
820 | interrupts = <0 133 4>; | |
8f4e3972 | 821 | power-domains = <&pd_sata>; |
110d06b2 AKV |
822 | #stream-id-cells = <4>; |
823 | iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, | |
824 | <&smmu 0x4c2>, <&smmu 0x4c3>; | |
825 | /* dma-coherent; */ | |
44303dfa MS |
826 | }; |
827 | ||
828 | sdhci0: sdhci@ff160000 { | |
c9811e14 | 829 | u-boot,dm-pre-reloc; |
0488a5e1 | 830 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
831 | status = "disabled"; |
832 | interrupt-parent = <&gic>; | |
833 | interrupts = <0 48 4>; | |
b976fd63 | 834 | reg = <0x0 0xff160000 0x0 0x1000>; |
44303dfa | 835 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 836 | xlnx,device_id = <0>; |
ba6ad317 MS |
837 | #stream-id-cells = <1>; |
838 | iommus = <&smmu 0x870>; | |
8f4e3972 | 839 | power-domains = <&pd_sd0>; |
5e3c90d2 MN |
840 | nvmem-cells = <&soc_revision>; |
841 | nvmem-cell-names = "soc_revision"; | |
44303dfa MS |
842 | }; |
843 | ||
844 | sdhci1: sdhci@ff170000 { | |
c9811e14 | 845 | u-boot,dm-pre-reloc; |
0488a5e1 | 846 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
847 | status = "disabled"; |
848 | interrupt-parent = <&gic>; | |
849 | interrupts = <0 49 4>; | |
b976fd63 | 850 | reg = <0x0 0xff170000 0x0 0x1000>; |
44303dfa | 851 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 852 | xlnx,device_id = <1>; |
ba6ad317 MS |
853 | #stream-id-cells = <1>; |
854 | iommus = <&smmu 0x871>; | |
8f4e3972 | 855 | power-domains = <&pd_sd1>; |
5e3c90d2 MN |
856 | nvmem-cells = <&soc_revision>; |
857 | nvmem-cell-names = "soc_revision"; | |
44303dfa MS |
858 | }; |
859 | ||
9c77cb73 MS |
860 | pinctrl0: pinctrl@ff180000 { |
861 | compatible = "xlnx,pinctrl-zynqmp"; | |
862 | status = "disabled"; | |
863 | reg = <0x0 0xff180000 0x0 0x1000>; | |
864 | }; | |
865 | ||
44303dfa MS |
866 | smmu: smmu@fd800000 { |
867 | compatible = "arm,mmu-500"; | |
b976fd63 | 868 | reg = <0x0 0xfd800000 0x0 0x20000>; |
ba6ad317 | 869 | #iommu-cells = <1>; |
10f2a292 | 870 | status = "disabled"; |
44303dfa MS |
871 | #global-interrupts = <1>; |
872 | interrupt-parent = <&gic>; | |
88a85aac EI |
873 | interrupts = <0 155 4>, |
874 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
875 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
876 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
877 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; | |
44303dfa MS |
878 | }; |
879 | ||
880 | spi0: spi@ff040000 { | |
881 | compatible = "cdns,spi-r1p6"; | |
882 | status = "disabled"; | |
883 | interrupt-parent = <&gic>; | |
884 | interrupts = <0 19 4>; | |
b976fd63 | 885 | reg = <0x0 0xff040000 0x0 0x1000>; |
44303dfa MS |
886 | clock-names = "ref_clk", "pclk"; |
887 | #address-cells = <1>; | |
888 | #size-cells = <0>; | |
8f4e3972 | 889 | power-domains = <&pd_spi0>; |
44303dfa MS |
890 | }; |
891 | ||
892 | spi1: spi@ff050000 { | |
893 | compatible = "cdns,spi-r1p6"; | |
894 | status = "disabled"; | |
895 | interrupt-parent = <&gic>; | |
896 | interrupts = <0 20 4>; | |
b976fd63 | 897 | reg = <0x0 0xff050000 0x0 0x1000>; |
44303dfa MS |
898 | clock-names = "ref_clk", "pclk"; |
899 | #address-cells = <1>; | |
900 | #size-cells = <0>; | |
8f4e3972 | 901 | power-domains = <&pd_spi1>; |
44303dfa MS |
902 | }; |
903 | ||
904 | ttc0: timer@ff110000 { | |
905 | compatible = "cdns,ttc"; | |
906 | status = "disabled"; | |
907 | interrupt-parent = <&gic>; | |
908 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; | |
b976fd63 | 909 | reg = <0x0 0xff110000 0x0 0x1000>; |
44303dfa | 910 | timer-width = <32>; |
8f4e3972 | 911 | power-domains = <&pd_ttc0>; |
44303dfa MS |
912 | }; |
913 | ||
914 | ttc1: timer@ff120000 { | |
915 | compatible = "cdns,ttc"; | |
916 | status = "disabled"; | |
917 | interrupt-parent = <&gic>; | |
918 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; | |
b976fd63 | 919 | reg = <0x0 0xff120000 0x0 0x1000>; |
44303dfa | 920 | timer-width = <32>; |
8f4e3972 | 921 | power-domains = <&pd_ttc1>; |
44303dfa MS |
922 | }; |
923 | ||
924 | ttc2: timer@ff130000 { | |
925 | compatible = "cdns,ttc"; | |
926 | status = "disabled"; | |
927 | interrupt-parent = <&gic>; | |
928 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; | |
b976fd63 | 929 | reg = <0x0 0xff130000 0x0 0x1000>; |
44303dfa | 930 | timer-width = <32>; |
8f4e3972 | 931 | power-domains = <&pd_ttc2>; |
44303dfa MS |
932 | }; |
933 | ||
934 | ttc3: timer@ff140000 { | |
935 | compatible = "cdns,ttc"; | |
936 | status = "disabled"; | |
937 | interrupt-parent = <&gic>; | |
938 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; | |
b976fd63 | 939 | reg = <0x0 0xff140000 0x0 0x1000>; |
44303dfa | 940 | timer-width = <32>; |
8f4e3972 | 941 | power-domains = <&pd_ttc3>; |
44303dfa MS |
942 | }; |
943 | ||
944 | uart0: serial@ff000000 { | |
c9811e14 | 945 | u-boot,dm-pre-reloc; |
ca2f5878 | 946 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
947 | status = "disabled"; |
948 | interrupt-parent = <&gic>; | |
949 | interrupts = <0 21 4>; | |
b976fd63 | 950 | reg = <0x0 0xff000000 0x0 0x1000>; |
44303dfa | 951 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 952 | power-domains = <&pd_uart0>; |
44303dfa MS |
953 | }; |
954 | ||
955 | uart1: serial@ff010000 { | |
c9811e14 | 956 | u-boot,dm-pre-reloc; |
ca2f5878 | 957 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
958 | status = "disabled"; |
959 | interrupt-parent = <&gic>; | |
960 | interrupts = <0 22 4>; | |
b976fd63 | 961 | reg = <0x0 0xff010000 0x0 0x1000>; |
44303dfa | 962 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 963 | power-domains = <&pd_uart1>; |
44303dfa MS |
964 | }; |
965 | ||
c926e6fb | 966 | usb0: usb0 { |
a84de48e | 967 | #address-cells = <2>; |
b976fd63 | 968 | #size-cells = <2>; |
44303dfa | 969 | status = "disabled"; |
a84de48e MS |
970 | compatible = "xlnx,zynqmp-dwc3"; |
971 | clock-names = "bus_clk", "ref_clk"; | |
972 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
973 | #stream-id-cells = <1>; |
974 | iommus = <&smmu 0x860>; | |
8f4e3972 | 975 | power-domains = <&pd_usb0>; |
a84de48e MS |
976 | ranges; |
977 | ||
978 | dwc3_0: dwc3@fe200000 { | |
979 | compatible = "snps,dwc3"; | |
980 | status = "disabled"; | |
b976fd63 | 981 | reg = <0x0 0xfe200000 0x0 0x40000>; |
a84de48e MS |
982 | interrupt-parent = <&gic>; |
983 | interrupts = <0 65 4>; | |
984 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
985 | snps,refclk_fladj; | |
986 | }; | |
44303dfa MS |
987 | }; |
988 | ||
c926e6fb | 989 | usb1: usb1 { |
a84de48e | 990 | #address-cells = <2>; |
b976fd63 | 991 | #size-cells = <2>; |
44303dfa | 992 | status = "disabled"; |
a84de48e MS |
993 | compatible = "xlnx,zynqmp-dwc3"; |
994 | clock-names = "bus_clk", "ref_clk"; | |
995 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
996 | #stream-id-cells = <1>; |
997 | iommus = <&smmu 0x861>; | |
8f4e3972 | 998 | power-domains = <&pd_usb1>; |
a84de48e MS |
999 | ranges; |
1000 | ||
1001 | dwc3_1: dwc3@fe300000 { | |
1002 | compatible = "snps,dwc3"; | |
1003 | status = "disabled"; | |
b976fd63 | 1004 | reg = <0x0 0xfe300000 0x0 0x40000>; |
a84de48e MS |
1005 | interrupt-parent = <&gic>; |
1006 | interrupts = <0 70 4>; | |
1007 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
1008 | snps,refclk_fladj; | |
1009 | }; | |
44303dfa MS |
1010 | }; |
1011 | ||
1012 | watchdog0: watchdog@fd4d0000 { | |
1013 | compatible = "cdns,wdt-r1p2"; | |
1014 | status = "disabled"; | |
1015 | interrupt-parent = <&gic>; | |
d3fd433f | 1016 | interrupts = <0 113 1>; |
b976fd63 | 1017 | reg = <0x0 0xfd4d0000 0x0 0x1000>; |
44303dfa MS |
1018 | timeout-sec = <10>; |
1019 | }; | |
1020 | ||
795ebc0e MS |
1021 | xilinx_ams: ams@ffa50000 { |
1022 | compatible = "xlnx,zynqmp-ams"; | |
1023 | status = "disabled"; | |
1024 | interrupt-parent = <&gic>; | |
1025 | interrupts = <0 56 4>; | |
1026 | interrupt-names = "ams-irq"; | |
1027 | reg = <0x0 0xffa50000 0x0 0x800>; | |
1028 | reg-names = "ams-base"; | |
1029 | #address-cells = <2>; | |
1030 | #size-cells = <2>; | |
1031 | #io-channel-cells = <1>; | |
1032 | ranges; | |
1033 | ||
1034 | ams_ps: ams_ps@ffa50800 { | |
1035 | compatible = "xlnx,zynqmp-ams-ps"; | |
1036 | status = "disabled"; | |
1037 | reg = <0x0 0xffa50800 0x0 0x400>; | |
1038 | }; | |
1039 | ||
1040 | ams_pl: ams_pl@ffa50c00 { | |
1041 | compatible = "xlnx,zynqmp-ams-pl"; | |
1042 | status = "disabled"; | |
1043 | reg = <0x0 0xffa50c00 0x0 0x400>; | |
1044 | }; | |
1045 | }; | |
1046 | ||
44303dfa MS |
1047 | xilinx_drm: xilinx_drm { |
1048 | compatible = "xlnx,drm"; | |
1049 | status = "disabled"; | |
1050 | xlnx,encoder-slave = <&xlnx_dp>; | |
1051 | xlnx,connector-type = "DisplayPort"; | |
1052 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
1053 | planes { | |
1054 | xlnx,pixel-format = "rgb565"; | |
1055 | plane0 { | |
1056 | dmas = <&xlnx_dpdma 3>; | |
bfe27980 | 1057 | dma-names = "dma0"; |
44303dfa MS |
1058 | }; |
1059 | plane1 { | |
bfe27980 HK |
1060 | dmas = <&xlnx_dpdma 0>, |
1061 | <&xlnx_dpdma 1>, | |
1062 | <&xlnx_dpdma 2>; | |
1063 | dma-names = "dma0", "dma1", "dma2"; | |
44303dfa MS |
1064 | }; |
1065 | }; | |
1066 | }; | |
1067 | ||
695d75a1 | 1068 | xlnx_dp: dp@fd4a0000 { |
44303dfa MS |
1069 | compatible = "xlnx,v-dp"; |
1070 | status = "disabled"; | |
b976fd63 | 1071 | reg = <0x0 0xfd4a0000 0x0 0x1000>; |
44303dfa MS |
1072 | interrupts = <0 119 4>; |
1073 | interrupt-parent = <&gic>; | |
1074 | clock-names = "aclk", "aud_clk"; | |
5f9b083c | 1075 | power-domains = <&pd_dp>; |
44303dfa MS |
1076 | xlnx,dp-version = "v1.2"; |
1077 | xlnx,max-lanes = <2>; | |
1078 | xlnx,max-link-rate = <540000>; | |
1079 | xlnx,max-bpc = <16>; | |
1080 | xlnx,enable-ycrcb; | |
1081 | xlnx,colormetry = "rgb"; | |
1082 | xlnx,bpc = <8>; | |
1083 | xlnx,audio-chan = <2>; | |
1084 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
939cfeaf | 1085 | xlnx,max-pclock-frequency = <300000>; |
44303dfa MS |
1086 | }; |
1087 | ||
1088 | xlnx_dp_snd_card: dp_snd_card { | |
1089 | compatible = "xlnx,dp-snd-card"; | |
1090 | status = "disabled"; | |
1091 | xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; | |
1092 | xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; | |
1093 | }; | |
1094 | ||
1095 | xlnx_dp_snd_codec0: dp_snd_codec0 { | |
1096 | compatible = "xlnx,dp-snd-codec"; | |
1097 | status = "disabled"; | |
1098 | clock-names = "aud_clk"; | |
1099 | }; | |
1100 | ||
1101 | xlnx_dp_snd_pcm0: dp_snd_pcm0 { | |
1102 | compatible = "xlnx,dp-snd-pcm"; | |
1103 | status = "disabled"; | |
1104 | dmas = <&xlnx_dpdma 4>; | |
1105 | dma-names = "tx"; | |
1106 | }; | |
1107 | ||
1108 | xlnx_dp_snd_pcm1: dp_snd_pcm1 { | |
1109 | compatible = "xlnx,dp-snd-pcm"; | |
1110 | status = "disabled"; | |
1111 | dmas = <&xlnx_dpdma 5>; | |
1112 | dma-names = "tx"; | |
1113 | }; | |
1114 | ||
695d75a1 | 1115 | xlnx_dp_sub: dp_sub@fd4aa000 { |
44303dfa MS |
1116 | compatible = "xlnx,dp-sub"; |
1117 | status = "disabled"; | |
b976fd63 MS |
1118 | reg = <0x0 0xfd4aa000 0x0 0x1000>, |
1119 | <0x0 0xfd4ab000 0x0 0x1000>, | |
1120 | <0x0 0xfd4ac000 0x0 0x1000>; | |
44303dfa MS |
1121 | reg-names = "blend", "av_buf", "aud"; |
1122 | xlnx,output-fmt = "rgb"; | |
939cfeaf HK |
1123 | xlnx,vid-fmt = "yuyv"; |
1124 | xlnx,gfx-fmt = "rgb565"; | |
5f9b083c | 1125 | power-domains = <&pd_dp>; |
44303dfa MS |
1126 | }; |
1127 | ||
1128 | xlnx_dpdma: dma@fd4c0000 { | |
1129 | compatible = "xlnx,dpdma"; | |
1130 | status = "disabled"; | |
b976fd63 | 1131 | reg = <0x0 0xfd4c0000 0x0 0x1000>; |
44303dfa MS |
1132 | interrupts = <0 122 4>; |
1133 | interrupt-parent = <&gic>; | |
1134 | clock-names = "axi_clk"; | |
5f9b083c | 1135 | power-domains = <&pd_dp>; |
44303dfa MS |
1136 | dma-channels = <6>; |
1137 | #dma-cells = <1>; | |
c926e6fb | 1138 | dma-video0channel { |
44303dfa MS |
1139 | compatible = "xlnx,video0"; |
1140 | }; | |
c926e6fb | 1141 | dma-video1channel { |
44303dfa MS |
1142 | compatible = "xlnx,video1"; |
1143 | }; | |
c926e6fb | 1144 | dma-video2channel { |
44303dfa MS |
1145 | compatible = "xlnx,video2"; |
1146 | }; | |
c926e6fb | 1147 | dma-graphicschannel { |
44303dfa MS |
1148 | compatible = "xlnx,graphics"; |
1149 | }; | |
c926e6fb | 1150 | dma-audio0channel { |
44303dfa MS |
1151 | compatible = "xlnx,audio0"; |
1152 | }; | |
c926e6fb | 1153 | dma-audio1channel { |
44303dfa MS |
1154 | compatible = "xlnx,audio1"; |
1155 | }; | |
1156 | }; | |
1157 | }; | |
1158 | }; |