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secure_boot: enable chain of trust for ARM platforms
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c
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42d1f039 1/*
a09b9b68 2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
29372ff3 3 *
42d1f039
WD		 4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
42d1f039
WD		 11 */
12
13#include <common.h>
14#include <watchdog.h>
15#include <asm/processor.h>
16#include <ioports.h>
f54fe87a 17#include <sata.h>
c916d7c9 18#include <fm_eth.h>
42d1f039 19#include <asm/io.h>
fd3c9bef 20#include <asm/cache.h>
87163180 21#include <asm/mmu.h>
a07bdad7 22#include <fsl_errata.h>
83d40dfd 23#include <asm/fsl_law.h>
f54fe87a 24#include <asm/fsl_serdes.h>
5ffa88ec 25#include <asm/fsl_srio.h>
9dee205d 26#include <fsl_usb.h>
57125f22 27#include <hwconfig.h>
fbc20aab 28#include <linux/compiler.h>
ec2b74ff 29#include "mp.h"
b9eebfad
RG		 30#ifdef CONFIG_FSL_CAAM
31#include <fsl_sec.h>
32#endif
f2717b47 33#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
a7b1e1b7
HW		 34#include <nand.h>
35#include <errno.h>
36#endif
42d1f039 37
fbc20aab 38#include "../../../../drivers/block/fsl_sata.h"
2a44efeb
ZQ		 39#ifdef CONFIG_U_QE
40#include "../../../../drivers/qe/qe.h"
41#endif
fbc20aab 42
d87080b7
WD		 43DECLARE_GLOBAL_DATA_PTR;
44
d1c561cd
NB		 45#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
46/*
47 * For deriving usb clock from 100MHz sysclk, reference divisor is set
48 * to a value of 5, which gives an intermediate value 20(100/5). The
49 * multiplication factor integer is set to 24, which when multiplied to
50 * above intermediate value provides clock for usb ip.
51 */
52void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
53{
54 sys_info_t sysinfo;
55
56 get_sys_info(&sysinfo);
57 if (sysinfo.diff_sysclk == 1) {
58 clrbits_be32(&usb_phy->pllprg[1],
59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
60 setbits_be32(&usb_phy->pllprg[1],
61 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
62 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
63 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
64 }
65}
66#endif
67
9c641a87
SG		 68#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
69void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
70{
71#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
72 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
73
74 /* Increase Disconnect Threshold by 50mV */
75 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
76 INC_DCNT_THRESHOLD_50MV;
77 /* Enable programming of USB High speed Disconnect threshold */
78 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
79 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
80
81 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
82 /* Increase Disconnect Threshold by 50mV */
83 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
84 INC_DCNT_THRESHOLD_50MV;
85 /* Enable programming of USB High speed Disconnect threshold */
86 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
87 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
88#else
89
90 u32 temp = 0;
91 u32 status = in_be32(&usb_phy->status1);
92
93 u32 squelch_prog_rd_0_2 =
94 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
95 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
96
97 u32 squelch_prog_rd_3_5 =
98 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
99 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
100
101 setbits_be32(&usb_phy->config1,
102 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
103 setbits_be32(&usb_phy->config2,
104 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
105
106 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
108
109 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
110 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
111#endif
112}
113#endif
114
115
2a44efeb 116#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
da9d4610
AF		 117extern qe_iop_conf_t qe_iop_conf_tab[];
118extern void qe_config_iopin(u8 port, u8 pin, int dir,
119 int open_drain, int assign);
120extern void qe_init(uint qe_base);
121extern void qe_reset(void);
122
123static void config_qe_ioports(void)
124{
125 u8 port, pin;
126 int dir, open_drain, assign;
127 int i;
128
129 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
130 port = qe_iop_conf_tab[i].port;
131 pin = qe_iop_conf_tab[i].pin;
132 dir = qe_iop_conf_tab[i].dir;
133 open_drain = qe_iop_conf_tab[i].open_drain;
134 assign = qe_iop_conf_tab[i].assign;
135 qe_config_iopin(port, pin, dir, open_drain, assign);
136 }
137}
138#endif
40d5fa35 139
9c4c5ae3 140#ifdef CONFIG_CPM2
aafeefbd 141void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039
WD		 142{
143 int portnum;
144
145 for (portnum = 0; portnum < 4; portnum++) {
146 uint pmsk = 0,
147 ppar = 0,
148 psor = 0,
149 pdir = 0,
150 podr = 0,
151 pdat = 0;
152 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
153 iop_conf_t *eiopc = iopc + 32;
154 uint msk = 1;
155
156 /*
157 * NOTE:
158 * index 0 refers to pin 31,
159 * index 31 refers to pin 0
160 */
161 while (iopc < eiopc) {
162 if (iopc->conf) {
163 pmsk |= msk;
164 if (iopc->ppar)
165 ppar |= msk;
166 if (iopc->psor)
167 psor |= msk;
168 if (iopc->pdir)
169 pdir |= msk;
170 if (iopc->podr)
171 podr |= msk;
172 if (iopc->pdat)
173 pdat |= msk;
174 }
175
176 msk <<= 1;
177 iopc++;
178 }
179
180 if (pmsk != 0) {
aafeefbd 181 volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039
WD		 182 uint tpmsk = ~pmsk;
183
184 /*
185 * the (somewhat confused) paragraph at the
186 * bottom of page 35-5 warns that there might
187 * be "unknown behaviour" when programming
188 * PSORx and PDIRx, if PPARx = 1, so I
189 * decided this meant I had to disable the
190 * dedicated function first, and enable it
191 * last.
192 */
193 iop->ppar &= tpmsk;
194 iop->psor = (iop->psor & tpmsk) | psor;
195 iop->podr = (iop->podr & tpmsk) | podr;
196 iop->pdat = (iop->pdat & tpmsk) | pdat;
197 iop->pdir = (iop->pdir & tpmsk) | pdir;
198 iop->ppar |= ppar;
199 }
200 }
201}
202#endif
203
6aba33e9 204#ifdef CONFIG_SYS_FSL_CPC
fb4a2409 205#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
7cb72723 206void disable_cpc_sram(void)
6aba33e9
KG		 207{
208 int i;
6aba33e9
KG		 209
210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
211
212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
2a9fab82
SX		 213 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
214 /* find and disable LAW of SRAM */
215 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
216
217 if (law.index == -1) {
218 printf("\nFatal error happened\n");
219 return;
220 }
221 disable_law(law.index);
222
223 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
224 out_be32(&cpc->cpccsr0, 0);
225 out_be32(&cpc->cpcsrcr0, 0);
226 }
fb4a2409
AB		 227 }
228}
2a9fab82 229#endif
6aba33e9 230
377ffcfa
SS		 231#if defined(T1040_TDM_QUIRK_CCSR_BASE)
232#ifdef CONFIG_POST
233#error POST memory test cannot be enabled with TDM
234#endif
235static void enable_tdm_law(void)
236{
237 int ret;
238 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
239 int tdm_hwconfig_enabled = 0;
240
241 /*
242 * Extract hwconfig from environment since environment
243 * is not setup properly yet. Search for tdm entry in
244 * hwconfig.
245 */
246 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
247 if (ret > 0) {
248 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
249 /* If tdm is defined in hwconfig, set law for tdm workaround */
250 if (tdm_hwconfig_enabled)
251 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
252 LAW_TRGT_IF_CCSR);
253 }
254}
255#endif
256
7cb72723 257void enable_cpc(void)
fb4a2409
AB		 258{
259 int i;
390619dd 260 int ret;
fb4a2409 261 u32 size = 0;
390619dd
SL		 262 u32 cpccfg0;
263 char buffer[HWCONFIG_BUFFER_SIZE];
264 char cpc_subarg[16];
265 bool have_hwconfig = false;
266 int cpc_args = 0;
fb4a2409
AB		 267 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
268
390619dd
SL		 269 /* Extract hwconfig from environment */
270 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
271 if (ret > 0) {
272 /*
273 * If "en_cpc" is not defined in hwconfig then by default all
274 * cpcs are enable. If this config is defined then individual
275 * cpcs which have to be enabled should also be defined.
276 * e.g en_cpc:cpc1,cpc2;
277 */
278 if (hwconfig_f("en_cpc", buffer))
279 have_hwconfig = true;
280 }
281
fb4a2409 282 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
390619dd
SL		 283 if (have_hwconfig) {
284 sprintf(cpc_subarg, "cpc%u", i + 1);
285 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
286 if (cpc_args == 0)
287 continue;
288 }
289 cpccfg0 = in_be32(&cpc->cpccfg0);
fb4a2409
AB		 290 size += CPC_CFG0_SZ_K(cpccfg0);
291
1d2c2a62
KG		 292#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
293 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
294#endif
868da593
KG		 295#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
296 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
297#endif
82125192
SW		 298#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
299 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
300#endif
133fbfa9
YS		 301#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
302 if (has_erratum_a006379()) {
303 setbits_be32(&cpc->cpchdbcr0,
304 CPC_HDBCR0_SPLRU_LEVEL_EN);
305 }
306#endif
1d2c2a62 307
6aba33e9
KG		 308 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
309 /* Read back to sync write */
310 in_be32(&cpc->cpccsr0);
311
312 }
313
2f848f97
SK		 314 puts("Corenet Platform Cache: ");
315 print_size(size * 1024, " enabled\n");
6aba33e9
KG		 316}
317
e56143e5 318static void invalidate_cpc(void)
6aba33e9
KG		 319{
320 int i;
321 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
322
323 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
2a9fab82
SX		 324 /* skip CPC when it used as all SRAM */
325 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
326 continue;
6aba33e9
KG		 327 /* Flash invalidate the CPC and clear all the locks */
328 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
329 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
330 ;
331 }
332}
333#else
334#define enable_cpc()
335#define invalidate_cpc()
7cb72723 336#define disable_cpc_sram()
6aba33e9
KG		 337#endif /* CONFIG_SYS_FSL_CPC */
338
42d1f039
WD		 339/*
340 * Breathe some life into the CPU...
341 *
342 * Set up the memory map
343 * initialize a bunch of registers
344 */
345
3c2a67ee
KG		 346#ifdef CONFIG_FSL_CORENET
347static void corenet_tb_init(void)
348{
349 volatile ccsr_rcpm_t *rcpm =
350 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
351 volatile ccsr_pic_t *pic =
680c613a 352 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
3c2a67ee
KG		 353 u32 whoami = in_be32(&pic->whoami);
354
355 /* Enable the timebase register for this core */
356 out_be32(&rcpm->ctbenrl, (1 << whoami));
357}
358#endif
359
c3678b09
YS		 360#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
361void fsl_erratum_a007212_workaround(void)
362{
363 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
364 u32 ddr_pll_ratio;
365 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
366 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
367 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
368#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
369 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
370 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
371#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
372 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
373 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
374#endif
375#endif
376 /*
377 * Even this workaround applies to selected version of SoCs, it is
378 * safe to apply to all versions, with the limitation of odd ratios.
379 * If RCW has disabled DDR PLL, we have to apply this workaround,
380 * otherwise DDR will not work.
381 */
382 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
383 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
384 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
385 /* check if RCW sets ratio to 0, required by this workaround */
386 if (ddr_pll_ratio != 0)
387 return;
388 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
389 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
390 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
391 /* check if reserved bits have the desired ratio */
392 if (ddr_pll_ratio == 0) {
393 printf("Error: Unknown DDR PLL ratio!\n");
394 return;
395 }
396 ddr_pll_ratio >>= 1;
397
398 setbits_be32(plldadcr1, 0x02000001);
399#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
400 setbits_be32(plldadcr2, 0x02000001);
401#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
402 setbits_be32(plldadcr3, 0x02000001);
403#endif
404#endif
405 setbits_be32(dpdovrcr4, 0xe0000000);
406 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
407#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
408 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
409#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
410 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
411#endif
412#endif
413 udelay(100);
414 clrbits_be32(plldadcr1, 0x02000001);
415#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
416 clrbits_be32(plldadcr2, 0x02000001);
417#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
418 clrbits_be32(plldadcr3, 0x02000001);
419#endif
420#endif
421 clrbits_be32(dpdovrcr4, 0xe0000000);
422}
423#endif
424
701e6401 425ulong cpu_init_f(void)
42d1f039 426{
42d1f039 427 extern void m8560_cpm_reset (void);
7cad2e38
RG		 428#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
429 (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
f110fe94
SG		 430 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
431#endif
7065b7d4
RG		 432#if defined(CONFIG_SECURE_BOOT)
433 struct law_entry law;
434#endif
a2cd50ed
PT		 435#ifdef CONFIG_MPC8548
436 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
437 uint svr = get_svr();
438
439 /*
440 * CPU2 errata workaround: A core hang possible while executing
441 * a msync instruction and a snoopable transaction from an I/O
442 * master tagged to make quick forward progress is present.
443 * Fixed in silicon rev 2.1.
444 */
445 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
446 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
447#endif
42d1f039 448
87163180
KG		 449 disable_tlb(14);
450 disable_tlb(15);
451
7065b7d4
RG		 452#if defined(CONFIG_SECURE_BOOT)
453 /* Disable the LAW created for NOR flash by the PBI commands */
454 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
455 if (law.index != -1)
456 disable_law(law.index);
fb4a2409
AB		 457
458#if defined(CONFIG_SYS_CPC_REINIT_F)
459 disable_cpc_sram();
460#endif
7cad2e38
RG		 461
462#if defined(CONFIG_FSL_CORENET)
463 /* Put PAMU in bypass mode */
464 out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
465#endif
466
7065b7d4
RG		 467#endif
468
9c4c5ae3 469#ifdef CONFIG_CPM2
6d0f6bcf 470 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039
WD		 471#endif
472
f51cdaf1 473 init_early_memctl_regs();
42d1f039 474
9c4c5ae3 475#if defined(CONFIG_CPM2)
42d1f039
WD		 476 m8560_cpm_reset();
477#endif
2a44efeb
ZQ		 478
479#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
da9d4610
AF		 480 /* Config QE ioports */
481 config_qe_ioports();
482#endif
2a44efeb 483
79f4333c
PT		 484#if defined(CONFIG_FSL_DMA)
485 dma_init();
486#endif
3c2a67ee
KG		 487#ifdef CONFIG_FSL_CORENET
488 corenet_tb_init();
489#endif
94e9411b 490 init_used_tlb_cams();
6aba33e9
KG		 491
492 /* Invalidate the CPC before DDR gets enabled */
493 invalidate_cpc();
f110fe94
SG		 494
495 #ifdef CONFIG_SYS_DCSRBAR_PHYS
496 /* set DCSRCR so that DCSR space is 1G */
497 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
498 in_be32(&gur->dcsrcr);
499#endif
500
c3678b09
YS		 501#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
502 fsl_erratum_a007212_workaround();
503#endif
504
59d34ed0 505 return 0;
42d1f039
WD		 506}
507
35079aa9
KG		 508/* Implement a dummy function for those platforms w/o SERDES */
509static void __fsl_serdes__init(void)
510{
511 return ;
512}
513__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
d9b94f28 514
e9827468 515#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
6d2b9da1
YS		 516int enable_cluster_l2(void)
517{
518 int i = 0;
5122dfae 519 u32 cluster, svr = get_svr();
6d2b9da1
YS		 520 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
521 struct ccsr_cluster_l2 __iomem *l2cache;
522
5122dfae
SL		 523 /* only the L2 of first cluster should be enabled as expected on T4080,
524 * but there is no EOC in the first cluster as HW sake, so return here
525 * to skip enabling L2 cache of the 2nd cluster.
526 */
527 if (SVR_SOC_VER(svr) == SVR_T4080)
528 return 0;
529
6d2b9da1
YS		 530 cluster = in_be32(&gur->tp_cluster[i].lower);
531 if (cluster & TP_CLUSTER_EOC)
532 return 0;
533
534 /* The first cache has already been set up, so skip it */
535 i++;
536
537 /* Look through the remaining clusters, and set up their caches */
538 do {
db9a8070
PK		 539 int j, cluster_valid = 0;
540
6d2b9da1 541 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
db9a8070 542
6d2b9da1
YS		 543 cluster = in_be32(&gur->tp_cluster[i].lower);
544
db9a8070
PK		 545 /* check that at least one core/accel is enabled in cluster */
546 for (j = 0; j < 4; j++) {
547 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
548 u32 type = in_be32(&gur->tp_ityp[idx]);
6d2b9da1 549
a1399a91
SL		 550 if ((type & TP_ITYP_AV) &&
551 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
db9a8070
PK		 552 cluster_valid = 1;
553 }
6d2b9da1 554
db9a8070
PK		 555 if (cluster_valid) {
556 /* set stash ID to (cluster) * 2 + 32 + 1 */
557 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
558
559 printf("enable l2 for cluster %d %p\n", i, l2cache);
560
561 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
562 while ((in_be32(&l2cache->l2csr0)
563 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
564 ;
9cd95ac7 565 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
db9a8070 566 }
6d2b9da1
YS		 567 i++;
568 } while (!(cluster & TP_CLUSTER_EOC));
569
570 return 0;
571}
572#endif
573
42d1f039 574/*
d9b94f28 575 * Initialize L2 as cache.
42d1f039 576 */
7cb72723 577int l2cache_init(void)
42d1f039 578{
fbc20aab 579 __maybe_unused u32 svr = get_svr();
6d2b9da1
YS		 580#ifdef CONFIG_L2_CACHE
581 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
e9827468 582#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
6d2b9da1 583 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
3f0202ed 584#endif
2a5fcb83 585
6beecfbb
WG		 586 puts ("L2: ");
587
42d1f039 588#if defined(CONFIG_L2_CACHE)
d9b94f28 589 volatile uint cache_ctl;
fbc20aab 590 uint ver;
73f15a06 591 u32 l2siz_field;
d9b94f28 592
f3e04bdc 593 ver = SVR_SOC_VER(svr);
42d1f039 594
d65cfe89 595 asm("msync;isync");
d9b94f28 596 cache_ctl = l2cache->l2ctl;
7da53351
MH		 597
598#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
599 if (cache_ctl & MPC85xx_L2CTL_L2E) {
600 /* Clear L2 SRAM memory-mapped base address */
601 out_be32(&l2cache->l2srbar0, 0x0);
602 out_be32(&l2cache->l2srbar1, 0x0);
603
604 /* set MBECCDIS=0, SBECCDIS=0 */
605 clrbits_be32(&l2cache->l2errdis,
606 (MPC85xx_L2ERRDIS_MBECC |
607 MPC85xx_L2ERRDIS_SBECC));
608
609 /* set L2E=0, L2SRAM=0 */
610 clrbits_be32(&l2cache->l2ctl,
611 (MPC85xx_L2CTL_L2E |
612 MPC85xx_L2CTL_L2SRAM_ENTIRE));
613 }
614#endif
615
73f15a06 616 l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28 617
73f15a06
KG		 618 switch (l2siz_field) {
619 case 0x0:
620 printf(" unknown size (0x%08x)\n", cache_ctl);
621 return -1;
622 break;
623 case 0x1:
624 if (ver == SVR_8540 || ver == SVR_8560 ||
48f6a5c3 625 ver == SVR_8541 || ver == SVR_8555) {
6b44d9e5
SK		 626 puts("128 KiB ");
627 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
73f15a06 628 cache_ctl = 0xc4000000;
d9b94f28 629 } else {
6b44d9e5 630 puts("256 KiB ");
73f15a06
KG		 631 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
632 }
633 break;
634 case 0x2:
635 if (ver == SVR_8540 || ver == SVR_8560 ||
48f6a5c3 636 ver == SVR_8541 || ver == SVR_8555) {
6b44d9e5
SK		 637 puts("256 KiB ");
638 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
29372ff3 639 cache_ctl = 0xc8000000;
73f15a06 640 } else {
6b44d9e5 641 puts("512 KiB ");
73f15a06
KG		 642 /* set L2E=1, L2I=1, & L2SRAM=0 */
643 cache_ctl = 0xc0000000;
d9b94f28 644 }
d65cfe89 645 break;
73f15a06 646 case 0x3:
6b44d9e5 647 puts("1024 KiB ");
73f15a06
KG		 648 /* set L2E=1, L2I=1, & L2SRAM=0 */
649 cache_ctl = 0xc0000000;
29372ff3 650 break;
d65cfe89
JL		 651 }
652
76b474e2 653 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb 654 puts("already enabled");
888279b5 655#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
e4c9a35d 656 u32 l2srbar = l2cache->l2srbar0;
76b474e2
MH		 657 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
658 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf 659 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3 660 l2cache->l2srbar0 = l2srbar;
9a511bd6 661 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3 662 }
6d0f6bcf 663#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3
ES		 664 puts("\n");
665 } else {
666 asm("msync;isync");
667 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
668 asm("msync;isync");
6beecfbb 669 puts("enabled\n");
29372ff3 670 }
1b3e4044 671#elif defined(CONFIG_BACKSIDE_L2_CACHE)
48f6a5c3 672 if (SVR_SOC_VER(svr) == SVR_P2040) {
acf3f8da
KG		 673 puts("N/A\n");
674 goto skip_l2;
675 }
676
1b3e4044
KG		 677 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
678
679 /* invalidate the L2 cache */
25bacf7a
KG		 680 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
681 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
1b3e4044
KG		 682 ;
683
82fd1f8d
KG		 684#ifdef CONFIG_SYS_CACHE_STASHING
685 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
686 mtspr(SPRN_L2CSR1, (32 + 1));
687#endif
688
1b3e4044
KG		 689 /* enable the cache */
690 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
691
654ea1f3
DL		 692 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
693 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
694 ;
2f848f97 695 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
654ea1f3 696 }
acf3f8da
KG		 697
698skip_l2:
e9827468 699#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
6d2b9da1 700 if (l2cache->l2csr0 & L2CSR0_L2E)
2f848f97
SK		 701 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
702 " enabled\n");
6d2b9da1
YS		 703
704 enable_cluster_l2();
42d1f039 705#else
6beecfbb 706 puts("disabled\n");
42d1f039 707#endif
6aba33e9 708
7cb72723
TY		 709 return 0;
710}
711
712/*
713 *
714 * The newer 8548, etc, parts have twice as much cache, but
715 * use the same bit-encoding as the older 8555, etc, parts.
716 *
717 */
718int cpu_init_r(void)
719{
720 __maybe_unused u32 svr = get_svr();
721#ifdef CONFIG_SYS_LBC_LCRR
722 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
723#endif
724#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
725 extern int spin_table_compat;
726 const char *spin;
727#endif
728#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
729 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
730#endif
731#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
732 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
733 /*
734 * CPU22 and NMG_CPU_A011 share the same workaround.
735 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
736 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
737 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
738 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
739 * be disabled by hwconfig with syntax:
740 *
741 * fsl_cpu_a011:disable
742 */
743 extern int enable_cpu_a011_workaround;
744#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
745 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
746#else
747 char buffer[HWCONFIG_BUFFER_SIZE];
748 char *buf = NULL;
749 int n, res;
750
751 n = getenv_f("hwconfig", buffer, sizeof(buffer));
752 if (n > 0)
753 buf = buffer;
754
755 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
756 if (res > 0) {
757 enable_cpu_a011_workaround = 0;
758 } else {
759 if (n >= HWCONFIG_BUFFER_SIZE) {
760 printf("fsl_cpu_a011 was not found. hwconfig variable "
761 "may be too long\n");
762 }
763 enable_cpu_a011_workaround =
764 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
765 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
766 }
767#endif
768 if (enable_cpu_a011_workaround) {
769 flush_dcache();
770 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
771 sync();
772 }
773#endif
774#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
775 /*
776 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
777 * in write shadow mode. Checking DCWS before setting SPR 976.
778 */
779 if (mfspr(L1CSR2) & L1CSR2_DCWS)
780 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
781#endif
782
783#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
784 spin = getenv("spin_table_compat");
785 if (spin && (*spin == 'n'))
786 spin_table_compat = 0;
787 else
788 spin_table_compat = 1;
789#endif
790
791 l2cache_init();
fb4a2409
AB		 792#if defined(CONFIG_RAMBOOT_PBL)
793 disable_cpc_sram();
794#endif
6aba33e9 795 enable_cpc();
377ffcfa
SS		 796#if defined(T1040_TDM_QUIRK_CCSR_BASE)
797 enable_tdm_law();
798#endif
6aba33e9 799
cb93071b 800#ifndef CONFIG_SYS_FSL_NO_SERDES
af025065
KG		 801 /* needs to be in ram since code uses global static vars */
802 fsl_serdes_init();
cb93071b 803#endif
af025065 804
424bf942
SL		 805#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
806#define MCFGR_AXIPIPE 0x000000f0
807 if (IS_SVR_REV(svr, 1, 0))
028dbb8d 808 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
424bf942
SL		 809#endif
810
72bd83cd
SL		 811#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
812 if (IS_SVR_REV(svr, 1, 0)) {
813 int i;
814 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
815
816 for (i = 0; i < 12; i++) {
817 p += i + (i > 5 ? 11 : 0);
818 out_be32(p, 0x2);
819 }
820 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
821 out_be32(p, 0x34);
822 }
823#endif
824
a09b9b68
KG		 825#ifdef CONFIG_SYS_SRIO
826 srio_init();
c8b28152 827#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
ff65f126
LG		 828 char *s = getenv("bootmaster");
829 if (s) {
830 if (!strcmp(s, "SRIO1")) {
831 srio_boot_master(1);
832 srio_boot_master_release_slave(1);
833 }
834 if (!strcmp(s, "SRIO2")) {
835 srio_boot_master(2);
836 srio_boot_master_release_slave(2);
837 }
838 }
5ffa88ec 839#endif
a09b9b68
KG		 840#endif
841
ec2b74ff
KG		 842#if defined(CONFIG_MP)
843 setup_mp();
844#endif
3f0202ed 845
4e0be34a 846#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
ae026ffd 847 {
4e0be34a
ZRR		 848 if (SVR_MAJ(svr) < 3) {
849 void *p;
850 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
851 setbits_be32(p, 1 << (31 - 14));
852 }
ae026ffd
RZ		 853 }
854#endif
855
3f0202ed
LC		 856#ifdef CONFIG_SYS_LBC_LCRR
857 /*
858 * Modify the CLKDIV field of LCRR register to improve the writing
859 * speed for NOR flash.
860 */
861 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
862 __raw_readl(&lbc->lcrr);
863 isync();
2b3a1cdd
KG		 864#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
865 udelay(100);
866#endif
3f0202ed
LC		 867#endif
868
86221f09
RZ		 869#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
870 {
9dee205d 871 struct ccsr_usb_phy __iomem *usb_phy1 =
86221f09 872 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
9c641a87
SG		 873#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
874 if (has_erratum_a006261())
875 fsl_erratum_a006261_workaround(usb_phy1);
876#endif
86221f09
RZ		 877 out_be32(&usb_phy1->usb_enable_override,
878 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
879 }
880#endif
881#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
882 {
9dee205d 883 struct ccsr_usb_phy __iomem *usb_phy2 =
86221f09 884 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
9c641a87
SG		 885#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
886 if (has_erratum_a006261())
887 fsl_erratum_a006261_workaround(usb_phy2);
888#endif
86221f09
RZ		 889 out_be32(&usb_phy2->usb_enable_override,
890 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
891 }
892#endif
893
99d7b0a4
X		 894#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
895 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
896 * multi-bit ECC errors which has impact on performance, so software
897 * should disable all ECC reporting from USB1 and USB2.
898 */
899 if (IS_SVR_REV(get_svr(), 1, 0)) {
900 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
901 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
902 setbits_be32(&dcfg->ecccr1,
903 (DCSR_DCFG_ECC_DISABLE_USB1 |
904 DCSR_DCFG_ECC_DISABLE_USB2));
905 }
906#endif
907
3fa75c87 908#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
9dee205d 909 struct ccsr_usb_phy __iomem *usb_phy =
3fa75c87
RZ		 910 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
911 setbits_be32(&usb_phy->pllprg[1],
912 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
913 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
914 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
915 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
d1c561cd
NB		 916#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
917 usb_single_source_clk_configure(usb_phy);
918#endif
3fa75c87
RZ		 919 setbits_be32(&usb_phy->port1.ctrl,
920 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
921 setbits_be32(&usb_phy->port1.drvvbuscfg,
922 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
923 setbits_be32(&usb_phy->port1.pwrfltcfg,
924 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
925 setbits_be32(&usb_phy->port2.ctrl,
926 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
927 setbits_be32(&usb_phy->port2.drvvbuscfg,
928 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
929 setbits_be32(&usb_phy->port2.pwrfltcfg,
930 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
9c641a87
SG		 931
932#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
933 if (has_erratum_a006261())
934 fsl_erratum_a006261_workaround(usb_phy);
3fa75c87
RZ		 935#endif
936
9c641a87
SG		 937#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
938
c916d7c9
KG		 939#ifdef CONFIG_FMAN_ENET
940 fman_enet_init();
941#endif
942
b9eebfad
RG		 943#ifdef CONFIG_FSL_CAAM
944 sec_init();
945#endif
946
fbc20aab
TT		 947#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
948 /*
949 * For P1022/1013 Rev1.0 silicon, after power on SATA host
950 * controller is configured in legacy mode instead of the
951 * expected enterprise mode. Software needs to clear bit[28]
952 * of HControl register to change to enterprise mode from
953 * legacy mode. We assume that the controller is offline.
954 */
955 if (IS_SVR_REV(svr, 1, 0) &&
956 ((SVR_SOC_VER(svr) == SVR_P1022) ||
48f6a5c3 957 (SVR_SOC_VER(svr) == SVR_P1013))) {
fbc20aab
TT		 958 fsl_sata_reg_t *reg;
959
960 /* first SATA controller */
961 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
962 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
963
964 /* second SATA controller */
965 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
966 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
967 }
968#endif
969
f13c9156 970 init_used_tlb_cams();
fbc20aab 971
42d1f039
WD		 972 return 0;
973}
26f4cdba 974
26f4cdba
KG		 975void arch_preboot_os(void)
976{
15fba327
KG		 977 u32 msr;
978
979 /*
980 * We are changing interrupt offsets and are about to boot the OS so
981 * we need to make sure we disable all async interrupts. EE is already
982 * disabled by the time we get called.
983 */
984 msr = mfmsr();
5344f7a2 985 msr &= ~(MSR_ME|MSR_CE);
15fba327 986 mtmsr(msr);
26f4cdba 987}
f54fe87a
KG		 988
989#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
990int sata_initialize(void)
991{
992 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
993 return __sata_initialize();
994
995 return 1;
996}
997#endif
f9a33f1c
KG		 998
999void cpu_secondary_init_r(void)
1000{
2a44efeb
ZQ		 1001#ifdef CONFIG_U_QE
1002 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1003#elif defined CONFIG_QE
f9a33f1c 1004 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
2a44efeb
ZQ		 1005#endif
1006
1007#ifdef CONFIG_QE
f9a33f1c
KG		 1008 qe_init(qe_base);
1009 qe_reset();
1010#endif
1011}
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