[people/ms/u-boot.git] / board / amcc / canyonlands / canyonlands.c

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/errno.h>

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */

DECLARE_GLOBAL_DATA_PTR;

struct board_bcsr {
	u8	board_id;
	u8	cpld_rev;
	u8	led_user;
	u8	board_status;
	u8	reset_ctrl;
	u8	flash_ctrl;
	u8	eth_ctrl;
	u8	usb_ctrl;
	u8	irq_ctrl;
};

#define BOARD_CANYONLANDS_PCIE	1
#define BOARD_CANYONLANDS_SATA	2
#define BOARD_GLACIER		3
#define BOARD_ARCHES		4

/*
 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
 * board specific values.
 */
#if defined(CONFIG_ARCHES)
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
}
#else
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}

u32 ddr_clktr(u32 default_val) {
	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#endif

#if defined(CONFIG_ARCHES)
/*
 * FPGA read/write helper macros
 */
static inline int board_fpga_read(int offset)
{
	int data;

	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));

	return data;
}

static inline void board_fpga_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
}

/*
 * CPLD read/write helper macros
 */
static inline int board_cpld_read(int offset)
{
	int data;

	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));

	return data;
}

static inline void board_cpld_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
#else
static int pvr_460ex(void)
{
	u32 pvr = get_pvr();

	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
	    (pvr == PVR_460EX_RB))
		return 1;

	return 0;
}
#endif	/* defined(CONFIG_ARCHES) */

int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
	u32 sdr0_cust0;
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;

#endif

	/*
	 * Setup the interrupt controller polarities, triggers, etc.
	 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
	mtdcr(UIC0ER, 0x00000000);	/* disable all */
	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */

	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
	mtdcr(UIC1ER, 0x00000000);	/* disable all */
	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC1SR, 0xffffffff);	/* clear all */

	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
	mtdcr(UIC2ER, 0x00000000);	/* disable all */
	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC2SR, 0xffffffff);	/* clear all */

	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
	mtdcr(UIC3ER, 0x00000000);	/* disable all */
	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC3SR, 0xffffffff);	/* clear all */

#if !defined(CONFIG_ARCHES)
	/* SDR Setting - enable NDFC */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);
#endif

	/*
	 * Configure PFC (Pin Function Control) registers
	 * UART0: 4 pins
	 */
	mtsdr(SDR0_PFC1, 0x00040000);

	/* Enable PCI host functionality in SDR0_PCI0 */
	mtsdr(SDR0_PCI0, 0xe0000000);

#if !defined(CONFIG_ARCHES)
	/* Enable ethernet and take out of reset */
	out_8(&bcsr_data->eth_ctrl, 0) ;

	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	out_8(&bcsr_data->flash_ctrl, 0) ;
	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */

	/* Setup PLB4-AHB bridge based on the system address map */
	mtdcr(AHB_TOP, 0x8000004B);
	mtdcr(AHB_BOT, 0x8000004B);

#endif

	return 0;
}

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Enable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	/*
	 * Configure USB-STP pins as alternate and not GPIO
	 * It seems to be neccessary to configure the STP pins as GPIO
	 * input at powerup (perhaps while USB reset is asserted). So
	 * we configure those pins to their "real" function now.
	 */
	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);

	return 0;
}

int usb_board_stop(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Disable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	/* Reconfigure USB-STP pins as input */
	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);

	return 0;
}

int usb_board_init_fail(void)
{
	return usb_board_stop();
}
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */

#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
	u32 reg;

	if (board_type == BOARD_CANYONLANDS_SATA) {
		/* Put SATA in reset */
		SDR_WRITE(SDR0_SRST1, 0x00020001);

		/* Set the phy for SATA, not PCI-E port 0 */
		reg = SDR_READ(PESDR0_PHY_CTL_RST);
		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
		reg = SDR_READ(PESDR0_L0CLK);
		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
		SDR_WRITE(PESDR0_L0DRV, 0x00000104);

		/* Bring SATA out of reset */
		SDR_WRITE(SDR0_SRST1, 0x00000000);
	}
}
#endif	/* !defined(CONFIG_ARCHES) */

int get_cpu_num(void)
{
	int cpu = NA_OR_UNKNOWN_CPU;

#if defined(CONFIG_ARCHES)
	int cpu_num;

	cpu_num = board_fpga_read(0x3);

	/* sanity check; assume cpu numbering starts and increments from 0 */
	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
		cpu = cpu_num;
#endif

	return cpu;
}

#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	if (pvr_460ex()) {
		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
			gd->board_type = BOARD_CANYONLANDS_PCIE;
		else
			gd->board_type = BOARD_CANYONLANDS_SATA;
	} else {
		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
		gd->board_type = BOARD_GLACIER;
	}

	switch (gd->board_type) {
	case BOARD_CANYONLANDS_PCIE:
	case BOARD_GLACIER:
		puts(", 2*PCIe");
		break;

	case BOARD_CANYONLANDS_SATA:
		puts(", 1*PCIe/1*SATA");
		break;
	}

	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));

	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

	canyonlands_sata_init(gd->board_type);

	return (0);
}

#else	/* defined(CONFIG_ARCHES) */

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	printf("       Revision %02x.%02x ",
				board_fpga_read(0x0), board_fpga_read(0x1));

	gd->board_type = BOARD_ARCHES;

	/* Only CPU0 has access to CPLD registers */
	if (get_cpu_num() == 0) {
		u8 cfg_sw = board_cpld_read(0x1);
		printf("(FPGA=%02x, CPLD=%02x)\n",
				board_fpga_read(0x2), board_cpld_read(0x0));
		printf("       Configuration Switch %d%d%d%d\n",
				((cfg_sw >> 3) & 0x01),
				((cfg_sw >> 2) & 0x01),
				((cfg_sw >> 1) & 0x01),
				((cfg_sw >> 0) & 0x01));
	} else
		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));


	if (s != NULL)
		printf("       Serial# %s\n", s);

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_PCI)
int board_pcie_first(void)
{
	/*
	 * Canyonlands with SATA enabled has only one PCIe slot
	 * (2nd one).
	 */
	if (gd->board_type == BOARD_CANYONLANDS_SATA)
		return 1;

	return 0;
}
#endif /* CONFIG_PCI */

int board_early_init_r (void)
{
	/*
	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	 * boot EBC mapping only supports a maximum of 16MBytes
	 * (4.ff00.0000 - 4.ffff.ffff).
	 * To solve this problem, the FLASH has to get remapped to another
	 * EBC address which accepts bigger regions:
	 *
	 * 0xfc00.0000 -> 4.cc00.0000
	 */

	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
	mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif

	/* Remove TLB entry of boot EBC mapping */
	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);

	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
		    TLB_WORD2_I_ENABLE);

	/*
	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	 * 0xfc00.0000 is possible
	 */

	/*
	 * Clear potential errors resulting from auto-calibration.
	 * If not done, then we could get an interrupt later on when
	 * exceptions are enabled.
	 */
	set_mcsr(get_mcsr());

	return 0;
}

#if !defined(CONFIG_ARCHES)
int misc_init_r(void)
{
	u32 sdr0_srst1 = 0;
	u32 eth_cfg;
	u8 val;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	/* disable SGMII mode */
	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
		     SDR0_ETH_CFG_SGMII1_ENABLE |
		     SDR0_ETH_CFG_SGMII0_ENABLE);
	/* Set the for 2 RGMII mode */
	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
	if (pvr_460ex())
		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	else
		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/*
	 * The AHB Bridge core is held in reset after power-on or reset
	 * so enable it now
	 */
	mfsdr(SDR0_SRST1, sdr0_srst1);
	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	mtsdr(SDR0_SRST1, sdr0_srst1);

	/*
	 * RTC/M41T62:
	 * Disable square wave output: Batterie will be drained
	 * quickly, when this output is not disabled
	 */
	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
	val &= ~0x40;
	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);

	return 0;
}

#else	/* defined(CONFIG_ARCHES) */

int misc_init_r(void)
{
	u32 eth_cfg = 0;
	u32 eth_pll;
	u32 reg;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */

	/* enable SGMII mode */
	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
			SDR0_ETH_CFG_SGMII1_ENABLE |
			SDR0_ETH_CFG_SGMII2_ENABLE);

	/* Set EMAC for MDIO */
	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;

	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);

	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/* reset all SGMII interfaces */
	mfsdr(SDR0_SRST1,   reg);
	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
	mtsdr(SDR0_SRST1, reg);
	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	mtsdr(SDR0_SRST1,   0x00000000);

	do {
		mfsdr(SDR0_ETH_PLL, eth_pll);
	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
extern void __ft_board_setup(void *blob, bd_t *bd);

void ft_board_setup(void *blob, bd_t *bd)
{
	__ft_board_setup(blob, bd);

	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
		/*
		 * When SATA is selected we need to disable the first PCIe
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
				     "disabled", sizeof("disabled"), 1);
	}

	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
		/*
		 * When PCIe is selected we need to disable the SATA
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
				     "disabled", sizeof("disabled"), 1);
	}
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8e1a3fe5 SR	1	/*
	2	* (C) Copyright 2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
8e1a3fe5 SR	6	*/
	7
	8	#include <common.h>
b36df561	9	#include <asm/ppc440.h>
8e1a3fe5 SR	10	#include <libfdt.h>
8e1a3fe5 SR	11	#include <fdt_support.h>
212ed906	12	#include <i2c.h>
8e1a3fe5 SR	13	#include <asm/processor.h>
	14	#include <asm/io.h>
	15	#include <asm/mmu.h>
	16	#include <asm/4xx_pcie.h>
09887762	17	#include <asm/ppc4xx-gpio.h>
06dfaeef	18	#include <asm/errno.h>
8e1a3fe5	19
6d0f6bcf	20	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
8e1a3fe5 SR	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
98303292 SR	24	struct board_bcsr {
	25	u8 board_id;
	26	u8 cpld_rev;
	27	u8 led_user;
	28	u8 board_status;
	29	u8 reset_ctrl;
	30	u8 flash_ctrl;
	31	u8 eth_ctrl;
	32	u8 usb_ctrl;
	33	u8 irq_ctrl;
17a68444	34	};
cc8e839a SR	35
	36	#define BOARD_CANYONLANDS_PCIE 1
	37	#define BOARD_CANYONLANDS_SATA 2
	38	#define BOARD_GLACIER 3
f09f09d3 AG	39	#define BOARD_ARCHES 4
f09f09d3 AG	40
f3ed3c9b	41	/*
a47a12be	42	* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
f3ed3c9b SR	43	* board specific values.
	44	*/
	45	#if defined(CONFIG_ARCHES)
	46	u32 ddr_wrdtr(u32 default_val) {
	47	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_0_DEG \| 0x823);
	48	}
	49	#else
	50	u32 ddr_wrdtr(u32 default_val) {
	51	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_180_DEG_ADV \| 0x823);
	52	}
	53
	54	u32 ddr_clktr(u32 default_val) {
	55	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
	56	}
	57	#endif
	58
f09f09d3 AG	59	#if defined(CONFIG_ARCHES)
	60	/*
	61	* FPGA read/write helper macros
	62	*/
	63	static inline int board_fpga_read(int offset)
	64	{
	65	int data;
	66
	67	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
	68
	69	return data;
	70	}
	71
	72	static inline void board_fpga_write(int offset, int data)
	73	{
	74	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
	75	}
	76
	77	/*
	78	* CPLD read/write helper macros
	79	*/
	80	static inline int board_cpld_read(int offset)
	81	{
	82	int data;
	83
	84	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	85	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
	86
	87	return data;
	88	}
	89
	90	static inline void board_cpld_write(int offset, int data)
	91	{
	92	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	93	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
	94	}
c3fa4f0c SR	95	#else
	96	static int pvr_460ex(void)
	97	{
	98	u32 pvr = get_pvr();
	99
	100	if ((pvr == PVR_460EX_RA) \|\| (pvr == PVR_460EX_SE_RA) \|\|
	101	(pvr == PVR_460EX_RB))
	102	return 1;
	103
	104	return 0;
	105	}
f09f09d3	106	#endif /* defined(CONFIG_ARCHES) */
cc8e839a	107
8e1a3fe5 SR	108	int board_early_init_f(void)
8e1a3fe5 SR	109	{
f09f09d3	110	#if !defined(CONFIG_ARCHES)
8e1a3fe5	111	u32 sdr0_cust0;
17a68444 RS	112	struct board_bcsr *bcsr_data =
	113	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	114
f09f09d3	115	#endif
8e1a3fe5	116
1c2926ab	117	/*
8e1a3fe5	118	* Setup the interrupt controller polarities, triggers, etc.
1c2926ab	119	*/
952e7760 SR	120	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	121	mtdcr(UIC0ER, 0x00000000); /* disable all */
	122	mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
	123	mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
	124	mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
	125	mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
	126	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	127
	128	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	129	mtdcr(UIC1ER, 0x00000000); /* disable all */
	130	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	131	mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
	132	mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
	133	mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
	134	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	135
	136	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	137	mtdcr(UIC2ER, 0x00000000); /* disable all */
	138	mtdcr(UIC2CR, 0x00000000); /* all non-critical */
	139	mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
	140	mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
	141	mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
	142	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	143
	144	mtdcr(UIC3SR, 0xffffffff); /* clear all */
	145	mtdcr(UIC3ER, 0x00000000); /* disable all */
	146	mtdcr(UIC3CR, 0x00000000); /* all non-critical */
	147	mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
	148	mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
	149	mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
	150	mtdcr(UIC3SR, 0xffffffff); /* clear all */
8e1a3fe5	151
f09f09d3	152	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	153	/* SDR Setting - enable NDFC */
	154	mfsdr(SDR0_CUST0, sdr0_cust0);
	155	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
	156	SDR0_CUST0_NDFC_ENABLE \|
	157	SDR0_CUST0_NDFC_BW_8_BIT \|
	158	SDR0_CUST0_NDFC_ARE_MASK \|
	159	SDR0_CUST0_NDFC_BAC_ENCODE(3) \|
6d0f6bcf	160	(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
8e1a3fe5	161	mtsdr(SDR0_CUST0, sdr0_cust0);
f09f09d3	162	#endif
8e1a3fe5 SR	163
	164	/*
	165	* Configure PFC (Pin Function Control) registers
	166	* UART0: 4 pins
	167	*/
	168	mtsdr(SDR0_PFC1, 0x00040000);
	169
	170	/* Enable PCI host functionality in SDR0_PCI0 */
	171	mtsdr(SDR0_PCI0, 0xe0000000);
	172
f09f09d3	173	#if !defined(CONFIG_ARCHES)
8e1a3fe5	174	/* Enable ethernet and take out of reset */
17a68444	175	out_8(&bcsr_data->eth_ctrl, 0) ;
8e1a3fe5 SR	176
8e1a3fe5 SR	177	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
17a68444	178	out_8(&bcsr_data->flash_ctrl, 0) ;
8e1a3fe5 SR	179	mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
8e1a3fe5 SR	180
41712b4e SR	181	/* Setup PLB4-AHB bridge based on the system address map */
	182	mtdcr(AHB_TOP, 0x8000004B);
	183	mtdcr(AHB_BOT, 0x8000004B);
	184
f09f09d3	185	#endif
41712b4e	186
8e1a3fe5 SR	187	return 0;
	188	}
	189
17a68444 RS	190	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
	191	int usb_board_init(void)
	192	{
	193	struct board_bcsr *bcsr_data =
	194	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	195	u8 val;
	196
	197	/* Enable USB host & USB-OTG */
	198	val = in_8(&bcsr_data->usb_ctrl);
	199	val &= ~(BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	200	out_8(&bcsr_data->usb_ctrl, val);
	201
709d9481 RS	202	/*
	203	* Configure USB-STP pins as alternate and not GPIO
	204	* It seems to be neccessary to configure the STP pins as GPIO
	205	* input at powerup (perhaps while USB reset is asserted). So
	206	* we configure those pins to their "real" function now.
	207	*/
	208	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	209	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	210
17a68444 RS	211	return 0;
	212	}
	213
	214	int usb_board_stop(void)
	215	{
	216	struct board_bcsr *bcsr_data =
	217	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	218	u8 val;
	219
	220	/* Disable USB host & USB-OTG */
	221	val = in_8(&bcsr_data->usb_ctrl);
	222	val \|= (BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	223	out_8(&bcsr_data->usb_ctrl, val);
	224
709d9481 RS	225	/* Reconfigure USB-STP pins as input */
	226	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	227	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	228
17a68444 RS	229	return 0;
	230	}
	231
	232	int usb_board_init_fail(void)
	233	{
	234	return usb_board_stop();
	235	}
	236	#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
	237
f09f09d3	238	#if !defined(CONFIG_ARCHES)
1c2926ab SR	239	static void canyonlands_sata_init(int board_type)
	240	{
	241	u32 reg;
	242
	243	if (board_type == BOARD_CANYONLANDS_SATA) {
	244	/* Put SATA in reset */
	245	SDR_WRITE(SDR0_SRST1, 0x00020001);
	246
	247	/* Set the phy for SATA, not PCI-E port 0 */
	248	reg = SDR_READ(PESDR0_PHY_CTL_RST);
	249	SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) \| 0x00000001);
	250	reg = SDR_READ(PESDR0_L0CLK);
	251	SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) \| 0x00000007);
	252	SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
	253	SDR_WRITE(PESDR0_L0DRV, 0x00000104);
	254
	255	/* Bring SATA out of reset */
	256	SDR_WRITE(SDR0_SRST1, 0x00000000);
	257	}
	258	}
f09f09d3 AG	259	#endif /* !defined(CONFIG_ARCHES) */
	260
	261	int get_cpu_num(void)
	262	{
	263	int cpu = NA_OR_UNKNOWN_CPU;
	264
	265	#if defined(CONFIG_ARCHES)
	266	int cpu_num;
	267
	268	cpu_num = board_fpga_read(0x3);
	269
	270	/* sanity check; assume cpu numbering starts and increments from 0 */
	271	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
	272	cpu = cpu_num;
	273	#endif
	274
	275	return cpu;
	276	}
1c2926ab	277
f09f09d3	278	#if !defined(CONFIG_ARCHES)
1c2926ab	279	int checkboard(void)
8e1a3fe5	280	{
17a68444 RS	281	struct board_bcsr *bcsr_data =
17a68444 RS	282	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
f0c0b3a9 WD	283	char buf[64];
f0c0b3a9 WD	284	int i = getenv_f("serial#", buf, sizeof(buf));
8e1a3fe5	285
c3fa4f0c	286	if (pvr_460ex()) {
8e1a3fe5	287	printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
17a68444	288	if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
cc8e839a SR	289	gd->board_type = BOARD_CANYONLANDS_PCIE;
	290	else
	291	gd->board_type = BOARD_CANYONLANDS_SATA;
c3fa4f0c SR	292	} else {
	293	printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	294	gd->board_type = BOARD_GLACIER;
cc8e839a SR	295	}
	296
	297	switch (gd->board_type) {
	298	case BOARD_CANYONLANDS_PCIE:
	299	case BOARD_GLACIER:
	300	puts(", 2*PCIe");
	301	break;
	302
	303	case BOARD_CANYONLANDS_SATA:
	304	puts(", 1PCIe/1SATA");
	305	break;
	306	}
	307
17a68444	308	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
8e1a3fe5	309
f0c0b3a9	310	if (i > 0) {
8e1a3fe5	311	puts(", serial# ");
f0c0b3a9	312	puts(buf);
8e1a3fe5 SR	313	}
	314	putc('\n');
	315
1c2926ab SR	316	canyonlands_sata_init(gd->board_type);
1c2926ab SR	317
8e1a3fe5 SR	318	return (0);
	319	}
	320
f09f09d3 AG	321	#else /* defined(CONFIG_ARCHES) */
	322
	323	int checkboard(void)
	324	{
	325	char *s = getenv("serial#");
	326
	327	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	328	printf(" Revision %02x.%02x ",
	329	board_fpga_read(0x0), board_fpga_read(0x1));
	330
	331	gd->board_type = BOARD_ARCHES;
	332
	333	/* Only CPU0 has access to CPLD registers */
	334	if (get_cpu_num() == 0) {
	335	u8 cfg_sw = board_cpld_read(0x1);
	336	printf("(FPGA=%02x, CPLD=%02x)\n",
	337	board_fpga_read(0x2), board_cpld_read(0x0));
	338	printf(" Configuration Switch %d%d%d%d\n",
	339	((cfg_sw >> 3) & 0x01),
	340	((cfg_sw >> 2) & 0x01),
	341	((cfg_sw >> 1) & 0x01),
	342	((cfg_sw >> 0) & 0x01));
	343	} else
	344	printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
	345
	346
	347	if (s != NULL)
	348	printf(" Serial# %s\n", s);
	349
	350	return 0;
	351	}
	352	#endif /* !defined(CONFIG_ARCHES) */
	353
8e1a3fe5	354	#if defined(CONFIG_PCI)
b0b86746	355	int board_pcie_first(void)
8e1a3fe5	356	{
cc8e839a SR	357	/*
	358	* Canyonlands with SATA enabled has only one PCIe slot
	359	* (2nd one).
	360	*/
	361	if (gd->board_type == BOARD_CANYONLANDS_SATA)
b0b86746	362	return 1;
8e1a3fe5	363
b0b86746	364	return 0;
8e1a3fe5 SR	365	}
	366	#endif /* CONFIG_PCI */
	367
	368	int board_early_init_r (void)
	369	{
	370	/*
	371	* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	372	* boot EBC mapping only supports a maximum of 16MBytes
	373	* (4.ff00.0000 - 4.ffff.ffff).
	374	* To solve this problem, the FLASH has to get remapped to another
	375	* EBC address which accepts bigger regions:
	376	*
	377	* 0xfc00.0000 -> 4.cc00.0000
8e1a3fe5 SR	378	*/
	379
	380	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
71665ebf	381	#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_NAND_SPL)
d1c3b275	382	mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L \| 0xda000);
71665ebf	383	#else
d1c3b275	384	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L \| 0xda000);
71665ebf	385	#endif
8e1a3fe5 SR	386
8e1a3fe5 SR	387	/* Remove TLB entry of boot EBC mapping */
6d0f6bcf	388	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
8e1a3fe5 SR	389
8e1a3fe5 SR	390	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
6d0f6bcf	391	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
8e1a3fe5 SR	392	TLB_WORD2_I_ENABLE);
	393
	394	/*
	395	* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	396	* 0xfc00.0000 is possible
	397	*/
	398
71665ebf SR	399	/*
	400	* Clear potential errors resulting from auto-calibration.
	401	* If not done, then we could get an interrupt later on when
	402	* exceptions are enabled.
	403	*/
	404	set_mcsr(get_mcsr());
	405
8e1a3fe5 SR	406	return 0;
	407	}
	408
f09f09d3	409	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	410	int misc_init_r(void)
	411	{
	412	u32 sdr0_srst1 = 0;
	413	u32 eth_cfg;
212ed906	414	u8 val;
8e1a3fe5 SR	415
	416	/*
	417	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	418	* This is board specific, so let's do it here.
	419	*/
	420	mfsdr(SDR0_ETH_CFG, eth_cfg);
	421	/* disable SGMII mode */
	422	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE \|
	423	SDR0_ETH_CFG_SGMII1_ENABLE \|
	424	SDR0_ETH_CFG_SGMII0_ENABLE);
	425	/* Set the for 2 RGMII mode */
	426	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	427	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
c3fa4f0c	428	if (pvr_460ex())
4c9e8557 SR	429	eth_cfg \|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	430	else
	431	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
8e1a3fe5 SR	432	mtsdr(SDR0_ETH_CFG, eth_cfg);
	433
	434	/*
	435	* The AHB Bridge core is held in reset after power-on or reset
	436	* so enable it now
	437	*/
	438	mfsdr(SDR0_SRST1, sdr0_srst1);
	439	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	440	mtsdr(SDR0_SRST1, sdr0_srst1);
	441
212ed906 SR	442	/*
	443	* RTC/M41T62:
	444	* Disable square wave output: Batterie will be drained
	445	* quickly, when this output is not disabled
	446	*/
6d0f6bcf	447	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
212ed906	448	val &= ~0x40;
6d0f6bcf	449	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
212ed906	450
8e1a3fe5 SR	451	return 0;
	452	}
	453
f09f09d3 AG	454	#else /* defined(CONFIG_ARCHES) */
	455
	456	int misc_init_r(void)
	457	{
	458	u32 eth_cfg = 0;
	459	u32 eth_pll;
	460	u32 reg;
	461
	462	/*
	463	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	464	* This is board specific, so let's do it here.
	465	*/
	466
	467	/* enable SGMII mode */
	468	eth_cfg \|= (SDR0_ETH_CFG_SGMII0_ENABLE \|
	469	SDR0_ETH_CFG_SGMII1_ENABLE \|
	470	SDR0_ETH_CFG_SGMII2_ENABLE);
	471
	472	/* Set EMAC for MDIO */
	473	eth_cfg \|= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
	474
	475	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	476	eth_cfg \|= (SDR0_ETH_CFG_TAHOE0_BYPASS \| SDR0_ETH_CFG_TAHOE1_BYPASS);
	477
	478	mtsdr(SDR0_ETH_CFG, eth_cfg);
	479
	480	/* reset all SGMII interfaces */
	481	mfsdr(SDR0_SRST1, reg);
	482	reg \|= (SDR0_SRST1_SGMII0 \| SDR0_SRST1_SGMII1 \| SDR0_SRST1_SGMII2);
	483	mtsdr(SDR0_SRST1, reg);
	484	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	485	mtsdr(SDR0_SRST1, 0x00000000);
	486
	487	do {
	488	mfsdr(SDR0_ETH_PLL, eth_pll);
	489	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
	490
	491	return 0;
	492	}
	493	#endif /* !defined(CONFIG_ARCHES) */
	494
8e1a3fe5	495	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
26d37f00 FR	496	extern void __ft_board_setup(void blob, bd_t bd);
26d37f00 FR	497
8e1a3fe5 SR	498	void ft_board_setup(void blob, bd_t bd)
8e1a3fe5 SR	499	{
26d37f00	500	__ft_board_setup(blob, bd);
8e1a3fe5	501
16bedc66 SR	502	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
	503	/*
	504	* When SATA is selected we need to disable the first PCIe
	505	* node in the device tree, so that Linux doesn't initialize
	506	* it.
	507	*/
8fd4166c SR	508	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
8fd4166c SR	509	"disabled", sizeof("disabled"), 1);
16bedc66 SR	510	}
	511
	512	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
	513	/*
	514	* When PCIe is selected we need to disable the SATA
	515	* node in the device tree, so that Linux doesn't initialize
	516	* it.
	517	*/
8fd4166c SR	518	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
8fd4166c SR	519	"disabled", sizeof("disabled"), 1);
16bedc66	520	}
8e1a3fe5 SR	521	}
8e1a3fe5 SR	522	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */