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Commit | Line | Data |
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887e2ec9 | 1 | /* |
83a49c8d MF |
2 | * (C) Copyright 2008 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
887e2ec9 | 4 | * |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
887e2ec9 SR |
6 | */ |
7 | ||
25ddd1fb | 8 | #include <asm-offsets.h> |
887e2ec9 | 9 | #include <ppc_asm.tmpl> |
61f2b38a | 10 | #include <asm/mmu.h> |
887e2ec9 SR |
11 | #include <config.h> |
12 | ||
83a49c8d | 13 | /* |
887e2ec9 SR |
14 | * TLB TABLE |
15 | * | |
16 | * This table is used by the cpu boot code to setup the initial tlb | |
17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
18 | * this table lets each board set things up however they like. | |
19 | * | |
20 | * Pointer to the table is returned in r1 | |
83a49c8d | 21 | */ |
887e2ec9 SR |
22 | .section .bootpg,"ax" |
23 | .globl tlbtab | |
24 | ||
25 | tlbtab: | |
26 | tlbtab_start | |
27 | ||
4d332dbe | 28 | /* vxWorks needs this as first entry for the Machine Check interrupt */ |
cf6eb6da | 29 | tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) |
887e2ec9 | 30 | |
d873133f SR |
31 | /* |
32 | * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This | |
33 | * entry is already configured for SDRAM via the JTAG debugger and mustn't | |
34 | * be re-initialized by this RAM-booting U-Boot version. | |
35 | */ | |
36 | #ifndef CONFIG_SYS_RAMBOOT | |
887e2ec9 | 37 | /* TLB-entry for DDR SDRAM (Up to 2GB) */ |
ea2e1428 | 38 | #ifdef CONFIG_4xx_DCACHE |
cf6eb6da | 39 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G) |
ea2e1428 | 40 | #else |
cf6eb6da | 41 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) |
ea2e1428 | 42 | #endif |
d873133f | 43 | #endif /* CONFIG_SYS_RAMBOOT */ |
887e2ec9 | 44 | |
4d332dbe | 45 | /* TLB-entry for EBC */ |
cf6eb6da | 46 | tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG ) |
4d332dbe NG |
47 | |
48 | /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the | |
49 | * speed up boot process. It is patched after relocation to enable SA_I | |
50 | */ | |
51 | #ifndef CONFIG_NAND_SPL | |
cf6eb6da | 52 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) |
4d332dbe | 53 | #else |
cf6eb6da | 54 | tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) |
4d332dbe NG |
55 | #endif |
56 | ||
6d0f6bcf | 57 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
887e2ec9 | 58 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
cf6eb6da | 59 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
887e2ec9 SR |
60 | #endif |
61 | ||
62 | /* TLB-entry for PCI Memory */ | |
cf6eb6da SR |
63 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) |
64 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) | |
65 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) | |
66 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) | |
887e2ec9 | 67 | |
887e2ec9 | 68 | /* TLB-entry for NAND */ |
cf6eb6da | 69 | tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) |
887e2ec9 SR |
70 | |
71 | /* TLB-entry for Internal Registers & OCM */ | |
cf6eb6da | 72 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) |
887e2ec9 SR |
73 | |
74 | /*TLB-entry PCI registers*/ | |
cf6eb6da | 75 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) |
887e2ec9 SR |
76 | |
77 | /* TLB-entry for peripherals */ | |
cf6eb6da | 78 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
887e2ec9 | 79 | |
81b73dec | 80 | /* TLB-entry PCI IO Space - from sr@denx.de */ |
cf6eb6da | 81 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) |
81b73dec | 82 | |
887e2ec9 SR |
83 | tlbtab_end |
84 | ||
85 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
86 | /* | |
87 | * For NAND booting the first TLB has to be reconfigured to full size | |
88 | * and with caching disabled after running from RAM! | |
89 | */ | |
6d0f6bcf JCPV |
90 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
91 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) | |
cf6eb6da | 92 | #define TLB02 TLB2(AC_RWX | SA_IG) |
887e2ec9 SR |
93 | |
94 | .globl reconfig_tlb0 | |
95 | reconfig_tlb0: | |
96 | sync | |
97 | isync | |
3edf68c4 | 98 | addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */ |
887e2ec9 SR |
99 | lis r5,TLB00@h |
100 | ori r5,r5,TLB00@l | |
101 | tlbwe r5,r4,0x0000 /* Save it out */ | |
102 | lis r5,TLB01@h | |
103 | ori r5,r5,TLB01@l | |
104 | tlbwe r5,r4,0x0001 /* Save it out */ | |
105 | lis r5,TLB02@h | |
106 | ori r5,r5,TLB02@l | |
107 | tlbwe r5,r4,0x0002 /* Save it out */ | |
108 | sync | |
109 | isync | |
110 | blr | |
111 | #endif |