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[FIX] XUPV2P change command handling
[people/ms/u-boot.git] / board / amcc / sequoia / sequoia.c
CommitLineData
887e2ec9
SR		 1/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
511d0c72 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <ppc440.h>
887e2ec9
SR		 28
29DECLARE_GLOBAL_DATA_PTR;
30
31extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
32
1b3c360c
SR		 33ulong flash_get_size (ulong base, int banknum);
34
887e2ec9
SR		 35int board_early_init_f(void)
36{
a78bc443
SR		 37 u32 sdr0_cust0;
38 u32 sdr0_pfc1, sdr0_pfc2;
39 u32 reg;
887e2ec9
SR		 40
41 mtdcr(ebccfga, xbcfg);
42 mtdcr(ebccfgd, 0xb8400000);
43
44 /*--------------------------------------------------------------------
45 * Setup the GPIO pins
46 *-------------------------------------------------------------------*/
47 /* test-only: take GPIO init from pcs440ep ???? in config file */
48 out32(GPIO0_OR, 0x00000000);
49 out32(GPIO0_TCR, 0x0000000f);
50 out32(GPIO0_OSRL, 0x50015400);
51 out32(GPIO0_OSRH, 0x550050aa);
52 out32(GPIO0_TSRL, 0x50015400);
53 out32(GPIO0_TSRH, 0x55005000);
54 out32(GPIO0_ISR1L, 0x50000000);
55 out32(GPIO0_ISR1H, 0x00000000);
56 out32(GPIO0_ISR2L, 0x00000000);
57 out32(GPIO0_ISR2H, 0x00000100);
58 out32(GPIO0_ISR3L, 0x00000000);
59 out32(GPIO0_ISR3H, 0x00000000);
60
61 out32(GPIO1_OR, 0x00000000);
62 out32(GPIO1_TCR, 0xc2000000);
63 out32(GPIO1_OSRL, 0x5c280000);
64 out32(GPIO1_OSRH, 0x00000000);
65 out32(GPIO1_TSRL, 0x0c000000);
66 out32(GPIO1_TSRH, 0x00000000);
67 out32(GPIO1_ISR1L, 0x00005550);
68 out32(GPIO1_ISR1H, 0x00000000);
69 out32(GPIO1_ISR2L, 0x00050000);
70 out32(GPIO1_ISR2H, 0x00000000);
71 out32(GPIO1_ISR3L, 0x01400000);
72 out32(GPIO1_ISR3H, 0x00000000);
73
74 /*--------------------------------------------------------------------
75 * Setup the interrupt controller polarities, triggers, etc.
76 *-------------------------------------------------------------------*/
77 mtdcr(uic0sr, 0xffffffff); /* clear all */
78 mtdcr(uic0er, 0x00000000); /* disable all */
79 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
80 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
81 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
82 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
83 mtdcr(uic0sr, 0xffffffff); /* clear all */
84
85 mtdcr(uic1sr, 0xffffffff); /* clear all */
86 mtdcr(uic1er, 0x00000000); /* disable all */
87 mtdcr(uic1cr, 0x00000000); /* all non-critical */
88 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
89 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
90 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
91 mtdcr(uic1sr, 0xffffffff); /* clear all */
92
93 mtdcr(uic2sr, 0xffffffff); /* clear all */
94 mtdcr(uic2er, 0x00000000); /* disable all */
95 mtdcr(uic2cr, 0x00000000); /* all non-critical */
96 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
97 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
98 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
99 mtdcr(uic2sr, 0xffffffff); /* clear all */
100
101 /* 50MHz tmrclk */
102 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
103
104 /* clear write protects */
105 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
106
107 /* enable Ethernet */
108 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
109
110 /* enable USB device */
111 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
112
113 /* select Ethernet pins */
114 mfsdr(SDR0_PFC1, sdr0_pfc1);
115 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
116 mfsdr(SDR0_PFC2, sdr0_pfc2);
117 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
118 mtsdr(SDR0_PFC2, sdr0_pfc2);
119 mtsdr(SDR0_PFC1, sdr0_pfc1);
120
121 /* PCI arbiter enabled */
122 mfsdr(sdr_pci0, reg);
123 mtsdr(sdr_pci0, 0x80000000 | reg);
124
125 /* setup NAND FLASH */
126 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 127 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR		 128 SDR0_CUST0_NDFC_ENABLE |
129 SDR0_CUST0_NDFC_BW_8_BIT |
130 SDR0_CUST0_NDFC_ARE_MASK |
131 (0x80000000 >> (28 + CFG_NAND_CS));
511d0c72 132 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR		 133
134 return 0;
135}
136
137/*---------------------------------------------------------------------------+
138 | misc_init_r.
139 +---------------------------------------------------------------------------*/
140int misc_init_r(void)
141{
142 uint pbcr;
143 int size_val = 0;
a78bc443 144 u32 reg;
854bc8da 145#ifdef CONFIG_440EPX
887e2ec9
SR		 146 unsigned long usb2d0cr = 0;
147 unsigned long usb2phy0cr, usb2h0cr = 0;
148 unsigned long sdr0_pfc1;
149 char *act = getenv("usbact");
854bc8da 150#endif
887e2ec9
SR		 151
152 /*
153 * FLASH stuff...
154 */
155
156 /* Re-do sizing to get full correct info */
1b3c360c
SR		 157
158 /* adjust flash start and offset */
159 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
160 gd->bd->bi_flashoffset = 0;
161
887e2ec9
SR		 162#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
163 mtdcr(ebccfga, pb3cr);
164#else
165 mtdcr(ebccfga, pb0cr);
166#endif
167 pbcr = mfdcr(ebccfgd);
168 switch (gd->bd->bi_flashsize) {
169 case 1 << 20:
170 size_val = 0;
171 break;
172 case 2 << 20:
173 size_val = 1;
174 break;
175 case 4 << 20:
176 size_val = 2;
177 break;
178 case 8 << 20:
179 size_val = 3;
180 break;
181 case 16 << 20:
182 size_val = 4;
183 break;
184 case 32 << 20:
185 size_val = 5;
186 break;
187 case 64 << 20:
188 size_val = 6;
189 break;
190 case 128 << 20:
191 size_val = 7;
192 break;
193 }
194 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
195#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
196 mtdcr(ebccfga, pb3cr);
197#else
198 mtdcr(ebccfga, pb0cr);
199#endif
200 mtdcr(ebccfgd, pbcr);
201
1b3c360c
SR		 202 /*
203 * Re-check to get correct base address
204 */
205 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9
SR		 206
207#ifdef CFG_ENV_IS_IN_FLASH
208 /* Monitor protection ON by default */
209 (void)flash_protect(FLAG_PROTECT_SET,
210 -CFG_MONITOR_LEN,
211 0xffffffff,
212 &flash_info[0]);
213
214 /* Env protection ON by default */
215 (void)flash_protect(FLAG_PROTECT_SET,
216 CFG_ENV_ADDR_REDUND,
217 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
218 &flash_info[0]);
219#endif
220
221 /*
222 * USB suff...
223 */
854bc8da 224#ifdef CONFIG_440EPX
887e2ec9
SR		 225 if (act == NULL || strcmp(act, "hostdev") == 0) {
226 /* SDR Setting */
511d0c72 227 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 228 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 229 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
230 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 231
232 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
233 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
511d0c72
WD		 234 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
235 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
887e2ec9 236 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 237 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
887e2ec9 238 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 239 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
887e2ec9 240 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 241 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
887e2ec9
SR		 242
243 /* An 8-bit/60MHz interface is the only possible alternative
244 when connecting the Device to the PHY */
511d0c72
WD		 245 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
246 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
887e2ec9 247
511d0c72
WD		 248 /* To enable the USB 2.0 Device function through the UTMI interface */
249 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
250 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
887e2ec9 251
511d0c72
WD		 252 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
253 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
887e2ec9 254
511d0c72 255 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 256 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 257 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
258 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 259
260 /*clear resets*/
261 udelay (1000);
262 mtsdr(SDR0_SRST1, 0x00000000);
263 udelay (1000);
264 mtsdr(SDR0_SRST0, 0x00000000);
265
266 printf("USB: Host(int phy) Device(ext phy)\n");
267
268 } else if (strcmp(act, "dev") == 0) {
269 /*-------------------PATCH-------------------------------*/
270 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
271
272 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
273 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
274 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 275 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
887e2ec9 276 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 277 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
887e2ec9 278 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 279 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
887e2ec9
SR		 280 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
281
282 udelay (1000);
283 mtsdr(SDR0_SRST1, 0x672c6000);
284
285 udelay (1000);
286 mtsdr(SDR0_SRST0, 0x00000080);
287
288 udelay (1000);
289 mtsdr(SDR0_SRST1, 0x60206000);
290
291 *(unsigned int *)(0xe0000350) = 0x00000001;
292
293 udelay (1000);
294 mtsdr(SDR0_SRST1, 0x60306000);
295 /*-------------------PATCH-------------------------------*/
296
297 /* SDR Setting */
511d0c72 298 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 299 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 300 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 301 mfsdr(SDR0_PFC1, sdr0_pfc1);
302
303 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
304 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
511d0c72 305 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
887e2ec9
SR		 306 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
307 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 308 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
887e2ec9 309 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 310 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
887e2ec9 311 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 312 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
887e2ec9
SR		 313
314 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
511d0c72 315 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
887e2ec9
SR		 316
317 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
511d0c72 318 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
887e2ec9
SR		 319
320 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
511d0c72 321 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
887e2ec9 322
511d0c72
WD		 323 mtsdr(SDR0_USB2H0CR, usb2h0cr);
324 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 325 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 326 mtsdr(SDR0_PFC1, sdr0_pfc1);
327
328 /*clear resets*/
329 udelay (1000);
330 mtsdr(SDR0_SRST1, 0x00000000);
331 udelay (1000);
332 mtsdr(SDR0_SRST0, 0x00000000);
333
334 printf("USB: Device(int phy)\n");
335 }
854bc8da 336#endif /* CONFIG_440EPX */
887e2ec9 337
8ce16f55
JO		 338 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
339 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
340 mtsdr(SDR0_SRST1, reg);
341
a78bc443
SR		 342 /*
343 * Clear PLB4A0_ACR[WRP]
344 * This fix will make the MAL burst disabling patch for the Linux
345 * EMAC driver obsolete.
346 */
347 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
348 mtdcr(plb4_acr, reg);
349
887e2ec9
SR		 350 return 0;
351}
352
353int checkboard(void)
354{
355 char *s = getenv("serial#");
e0b9ea8c
SR		 356 u8 rev;
357 u8 val;
887e2ec9 358
854bc8da 359#ifdef CONFIG_440EPX
887e2ec9 360 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR		 361#else
362 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
363#endif
e0b9ea8c 364
ada4697d
JM		 365 rev = in8(CFG_BCSR_BASE + 0);
366 val = in8(CFG_BCSR_BASE + 5) & 0x01;
e0b9ea8c
SR		 367 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
368
887e2ec9
SR		 369 if (s != NULL) {
370 puts(", serial# ");
371 puts(s);
372 }
373 putc('\n');
374
375 return (0);
376}
377
378#if defined(CFG_DRAM_TEST)
379int testdram(void)
380{
381 unsigned long *mem = (unsigned long *)0;
382 const unsigned long kend = (1024 / sizeof(unsigned long));
383 unsigned long k, n;
384
385 mtmsr(0);
386
387 for (k = 0; k < CFG_MBYTES_SDRAM;
388 ++k, mem += (1024 / sizeof(unsigned long))) {
389 if ((k & 1023) == 0) {
390 printf("%3d MB\r", k / 1024);
391 }
392
393 memset(mem, 0xaaaaaaaa, 1024);
394 for (n = 0; n < kend; ++n) {
395 if (mem[n] != 0xaaaaaaaa) {
396 printf("SDRAM test fails at: %08x\n",
397 (uint) & mem[n]);
398 return 1;
399 }
400 }
401
402 memset(mem, 0x55555555, 1024);
403 for (n = 0; n < kend; ++n) {
404 if (mem[n] != 0x55555555) {
405 printf("SDRAM test fails at: %08x\n",
406 (uint) & mem[n]);
407 return 1;
408 }
409 }
410 }
411 printf("SDRAM test passes\n");
412 return 0;
413}
414#endif
415
416/*************************************************************************
417 * pci_pre_init
418 *
419 * This routine is called just prior to registering the hose and gives
420 * the board the opportunity to check things. Returning a value of zero
421 * indicates that things are bad & PCI initialization should be aborted.
422 *
423 * Different boards may wish to customize the pci controller structure
424 * (add regions, override default access routines, etc) or perform
425 * certain pre-initialization actions.
426 *
427 ************************************************************************/
466fff1a 428#if defined(CONFIG_PCI)
887e2ec9
SR		 429int pci_pre_init(struct pci_controller *hose)
430{
431 unsigned long addr;
887e2ec9
SR		 432
433 /*-------------------------------------------------------------------------+
434 | Set priority for all PLB3 devices to 0.
435 | Set PLB3 arbiter to fair mode.
436 +-------------------------------------------------------------------------*/
437 mfsdr(sdr_amp1, addr);
438 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
439 addr = mfdcr(plb3_acr);
440 mtdcr(plb3_acr, addr | 0x80000000);
441
442 /*-------------------------------------------------------------------------+
443 | Set priority for all PLB4 devices to 0.
444 +-------------------------------------------------------------------------*/
445 mfsdr(sdr_amp0, addr);
446 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
447 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
448 mtdcr(plb4_acr, addr);
449
450 /*-------------------------------------------------------------------------+
451 | Set Nebula PLB4 arbiter to fair mode.
452 +-------------------------------------------------------------------------*/
453 /* Segment0 */
454 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
455 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
456 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
457 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
458 mtdcr(plb0_acr, addr);
459
460 /* Segment1 */
461 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
462 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
463 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
464 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
465 mtdcr(plb1_acr, addr);
466
467 return 1;
468}
466fff1a 469#endif /* defined(CONFIG_PCI) */
887e2ec9
SR		 470
471/*************************************************************************
472 * pci_target_init
473 *
474 * The bootstrap configuration provides default settings for the pci
475 * inbound map (PIM). But the bootstrap config choices are limited and
476 * may not be sufficient for a given board.
477 *
478 ************************************************************************/
479#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
480void pci_target_init(struct pci_controller *hose)
481{
482 /*--------------------------------------------------------------------------+
483 * Set up Direct MMIO registers
484 *--------------------------------------------------------------------------*/
485 /*--------------------------------------------------------------------------+
486 | PowerPC440EPX PCI Master configuration.
487 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
488 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
489 | Use byte reversed out routines to handle endianess.
490 | Make this region non-prefetchable.
491 +--------------------------------------------------------------------------*/
492 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
493 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
494 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
495 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
496 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
497
498 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
499 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
500 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
501 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
502 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
503
504 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
505 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
506 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
507 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
508
509 /*--------------------------------------------------------------------------+
510 * Set up Configuration registers
511 *--------------------------------------------------------------------------*/
512
513 /* Program the board's subsystem id/vendor id */
514 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
515 CFG_PCI_SUBSYS_VENDORID);
516 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
517
518 /* Configure command register as bus master */
519 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
520
521 /* 240nS PCI clock */
522 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
523
524 /* No error reporting */
525 pci_write_config_word(0, PCI_ERREN, 0);
526
527 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
528
529}
530#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
531
532/*************************************************************************
533 * pci_master_init
534 *
535 ************************************************************************/
536#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
537void pci_master_init(struct pci_controller *hose)
538{
539 unsigned short temp_short;
540
541 /*--------------------------------------------------------------------------+
542 | Write the PowerPC440 EP PCI Configuration regs.
543 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
544 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
545 +--------------------------------------------------------------------------*/
546 pci_read_config_word(0, PCI_COMMAND, &temp_short);
547 pci_write_config_word(0, PCI_COMMAND,
548 temp_short | PCI_COMMAND_MASTER |
549 PCI_COMMAND_MEMORY);
550}
551#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
552
553/*************************************************************************
554 * is_pci_host
555 *
556 * This routine is called to determine if a pci scan should be
557 * performed. With various hardware environments (especially cPCI and
558 * PPMC) it's insufficient to depend on the state of the arbiter enable
559 * bit in the strap register, or generic host/adapter assumptions.
560 *
561 * Rather than hard-code a bad assumption in the general 440 code, the
562 * 440 pci code requires the board to decide at runtime.
563 *
564 * Return 0 for adapter mode, non-zero for host (monarch) mode.
565 *
566 *
567 ************************************************************************/
568#if defined(CONFIG_PCI)
569int is_pci_host(struct pci_controller *hose)
570{
571 /* Cactus is always configured as host. */
572 return (1);
573}
574#endif /* defined(CONFIG_PCI) */
a11e0696
IL		 575#if defined(CONFIG_POST)
576/*
577 * Returns 1 if keys pressed to start the power-on long-running tests
578 * Called from board_init_f().
579 */
580int post_hotkeys_pressed(void)
581{
582 return 0; /* No hotkeys supported */
583}
584#endif /* CONFIG_POST */
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