[people/ms/u-boot.git] / board / atmel / sama5d3xek / sama5d3xek.c

/*
 * Copyright (C) 2012 - 2013 Atmel Corporation
 * Bo Shen <voice.shen@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#include <micrel.h>
#include <net.h>
#include <netdev.h>
#include <spl.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/at91_wdt.h>

#ifdef CONFIG_USB_GADGET_ATMEL_USBA
#include <asm/arch/atmel_usba_udc.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_NAND_ATMEL
void sama5d3xek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
	       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
	       AT91_SMC_MODE_DBW_8 |
#endif
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);
}
#endif

#ifdef CONFIG_CMD_USB
static void sama5d3xek_usb_hw_init(void)
{
	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
}
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
static void sama5d3xek_mci_hw_init(void)
{
	at91_mci_hw_init();

	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col = 800,
	.vl_row = 480,
	.vl_clk = 24000000,
	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
	.vl_bpix = LCD_BPP,
	.vl_tft = 1,
	.vl_hsync_len = 128,
	.vl_left_margin = 64,
	.vl_right_margin = 64,
	.vl_vsync_len = 2,
	.vl_upper_margin = 22,
	.vl_lower_margin = 21,
	.mmio = ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
}

void lcd_disable(void)
{
}

static void sama5d3xek_lcd_hw_init(void)
{
	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;

	/* The higher 8 bit of LCD is board related */
	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */

	/* Configure lower 16 bit of LCD and enable clock */
	at91_lcd_hw_init();
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

void lcd_show_board_info(void)
{
	ulong dram_size;
	uint64_t nand_size;
	int i;
	char temp[32];

	lcd_printf("%s\n", U_BOOT_VERSION);
	lcd_printf("(C) 2013 ATMEL Corp\n");
	lcd_printf("at91@atmel.com\n");
	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
		   strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;
#endif
	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
		   dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIOD);
	at91_periph_clk_enable(ATMEL_ID_PIOE);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_NAND_ATMEL
	sama5d3xek_nand_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	sama5d3xek_usb_hw_init();
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	at91_udp_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
	sama5d3xek_mci_hw_init();
#endif
#ifdef CONFIG_ATMEL_SPI
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	if (has_emac())
		at91_macb_hw_init();
	if (has_gmac())
		at91_gmac_hw_init();
#endif
#ifdef CONFIG_LCD
	if (has_lcdc())
		sama5d3xek_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	/* rx data delay */
	ksz9021_phy_extended_write(phydev,
				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
	/* tx data delay */
	ksz9021_phy_extended_write(phydev,
				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
	/* rx/tx clock delay */
	ksz9021_phy_extended_write(phydev,
				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_MACB
	if (has_emac())
		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
	if (has_gmac())
		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	usba_udc_probe(&pdata);
#ifdef CONFIG_USB_ETH_RNDIS
	usb_eth_initialize(bis);
#endif
#endif

	return rc;
}

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bis)
{
	int rc = 0;

	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);

	return rc;
}
#endif

/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs < 4;
}

void spi_cs_activate(struct spi_slave *slave)
{
	switch (slave->cs) {
	case 0:
		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
	case 1:
		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
	case 2:
		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
	case 3:
		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
	default:
		break;
	}
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	switch (slave->cs) {
	case 0:
		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
	case 1:
		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
	case 2:
		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
	case 3:
		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
	default:
		break;
	}
}
#endif /* CONFIG_ATMEL_SPI */

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
	sama5d3xek_mci_hw_init();
#endif
}

static void ddr2_conf(struct atmel_mpddr *ddr2)
{
	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);

	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_14 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
		    ATMEL_MPDDRC_CR_ENRDM_ON |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	/*
	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
	 */
	ddr2->rtr = 0x411;

	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);

	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);

	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}

void mem_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct atmel_mpddr ddr2;

	ddr2_conf(&ddr2);

	/* enable MPDDR clock */
	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	writel(0x4, &pmc->scer);

	/* DDRAM2 Controller initialize */
	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
}

void at91_pmc_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	u32 tmp;

	tmp = AT91_PMC_PLLAR_29 |
	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
	      AT91_PMC_PLLXR_MUL(43) |
	      AT91_PMC_PLLXR_DIV(1);
	at91_plla_init(tmp);

	writel(0x3 << 8, &pmc->pllicpr);

	tmp = AT91_PMC_MCKR_MDIV_4 |
	      AT91_PMC_MCKR_CSS_PLLA;
	at91_mck_init(tmp);
}
#endif
Commit	Line	Data
3225f34e BS	1	/*
	2	* Copyright (C) 2012 - 2013 Atmel Corporation
	3	* Bo Shen <voice.shen@atmel.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3225f34e BS	6	*/
	7
	8	#include <common.h>
	9	#include <mmc.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/sama5d3_smc.h>
	12	#include <asm/arch/at91_common.h>
	13	#include <asm/arch/at91_pmc.h>
	14	#include <asm/arch/at91_rstc.h>
	15	#include <asm/arch/gpio.h>
	16	#include <asm/arch/clk.h>
	17	#include <lcd.h>
	18	#include <atmel_lcdc.h>
	19	#include <atmel_mci.h>
e08d6f3a	20	#include <micrel.h>
3225f34e BS	21	#include <net.h>
3225f34e BS	22	#include <netdev.h>
c5e8885a BS	23	#include <spl.h>
	24	#include <asm/arch/atmel_mpddrc.h>
	25	#include <asm/arch/at91_wdt.h>
3225f34e	26
3668ce3c BS	27	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	28	#include <asm/arch/atmel_usba_udc.h>
	29	#endif
	30
3225f34e BS	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	/* ------------------------------------------------------------------------- */
	34	/*
	35	* Miscelaneous platform dependent initialisations
	36	*/
	37
	38	#ifdef CONFIG_NAND_ATMEL
	39	void sama5d3xek_nand_hw_init(void)
	40	{
	41	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	42
	43	at91_periph_clk_enable(ATMEL_ID_SMC);
	44
	45	/* Configure SMC CS3 for NAND/SmartMedia */
	46	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(1) \|
	47	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(1),
	48	&smc->cs[3].setup);
	49	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(5) \|
	50	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(5),
	51	&smc->cs[3].pulse);
	52	writel(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(8),
	53	&smc->cs[3].cycle);
	54	writel(AT91_SMC_TIMINGS_TCLR(3) \| AT91_SMC_TIMINGS_TADL(10) \|
	55	AT91_SMC_TIMINGS_TAR(3) \| AT91_SMC_TIMINGS_TRR(4) \|
	56	AT91_SMC_TIMINGS_TWB(5) \| AT91_SMC_TIMINGS_RBNSEL(3)\|
	57	AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	58	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	59	AT91_SMC_MODE_EXNW_DISABLE \|
	60	#ifdef CONFIG_SYS_NAND_DBW_16
	61	AT91_SMC_MODE_DBW_16 \|
	62	#else /* CONFIG_SYS_NAND_DBW_8 */
	63	AT91_SMC_MODE_DBW_8 \|
	64	#endif
	65	AT91_SMC_MODE_TDF_CYCLE(3),
	66	&smc->cs[3].mode);
	67	}
	68	#endif
	69
	70	#ifdef CONFIG_CMD_USB
	71	static void sama5d3xek_usb_hw_init(void)
	72	{
	73	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
	74	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
	75	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
	76	}
	77	#endif
	78
	79	#ifdef CONFIG_GENERIC_ATMEL_MCI
	80	static void sama5d3xek_mci_hw_init(void)
	81	{
	82	at91_mci_hw_init();
	83
	84	at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
	85	}
	86	#endif
	87
	88	#ifdef CONFIG_LCD
	89	vidinfo_t panel_info = {
	90	.vl_col = 800,
	91	.vl_row = 480,
	92	.vl_clk = 24000000,
	93	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL \| ATMEL_LCDC_INVFRAME_NORMAL,
	94	.vl_bpix = LCD_BPP,
95	.vl_tft = 1,
96	.vl_hsync_len = 128,
97	.vl_left_margin = 64,
98	.vl_right_margin = 64,
99	.vl_vsync_len = 2,
100	.vl_upper_margin = 22,
101	.vl_lower_margin = 21,
102	.mmio = ATMEL_BASE_LCDC,
103	};
104
105	void lcd_enable(void)
106	{
107	}
108
109	void lcd_disable(void)
110	{
111	}
112
113	static void sama5d3xek_lcd_hw_init(void)
114	{
115	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
116
117	/* The higher 8 bit of LCD is board related */
118	at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
119	at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
120	at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
121	at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
122	at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
123	at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
124	at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
125	at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
126
127	/* Configure lower 16 bit of LCD and enable clock */
128	at91_lcd_hw_init();
129	}
130
131	#ifdef CONFIG_LCD_INFO
132	#include <nand.h>
133	#include <version.h>
134
135	void lcd_show_board_info(void)
136	{
d02a60a1 WJ	137	ulong dram_size;
d02a60a1 WJ	138	uint64_t nand_size;
3225f34e BS	139	int i;
	140	char temp[32];
	141
	142	lcd_printf("%s\n", U_BOOT_VERSION);
	143	lcd_printf("(C) 2013 ATMEL Corp\n");
	144	lcd_printf("at91@atmel.com\n");
	145	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
	146	strmhz(temp, get_cpu_clk_rate()));
	147
	148	dram_size = 0;
	149	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	150	dram_size += gd->bd->bi_dram[i].size;
	151
	152	nand_size = 0;
	153	#ifdef CONFIG_NAND_ATMEL
	154	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
	155	nand_size += nand_info[i].size;
	156	#endif
d02a60a1	157	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
3225f34e BS	158	dram_size >> 20, nand_size >> 20);
	159	}
	160	#endif /* CONFIG_LCD_INFO */
	161	#endif /* CONFIG_LCD */
	162
	163	int board_early_init_f(void)
	164	{
d2acb986 BS	165	at91_periph_clk_enable(ATMEL_ID_PIOA);
	166	at91_periph_clk_enable(ATMEL_ID_PIOB);
	167	at91_periph_clk_enable(ATMEL_ID_PIOC);
	168	at91_periph_clk_enable(ATMEL_ID_PIOD);
	169	at91_periph_clk_enable(ATMEL_ID_PIOE);
	170
3225f34e BS	171	at91_seriald_hw_init();
	172
	173	return 0;
	174	}
	175
	176	int board_init(void)
	177	{
	178	/* adress of boot parameters */
	179	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	180
	181	#ifdef CONFIG_NAND_ATMEL
	182	sama5d3xek_nand_hw_init();
	183	#endif
	184	#ifdef CONFIG_CMD_USB
	185	sama5d3xek_usb_hw_init();
	186	#endif
3668ce3c BS	187	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	188	at91_udp_hw_init();
	189	#endif
3225f34e BS	190	#ifdef CONFIG_GENERIC_ATMEL_MCI
	191	sama5d3xek_mci_hw_init();
	192	#endif
	193	#ifdef CONFIG_ATMEL_SPI
	194	at91_spi0_hw_init(1 << 0);
	195	#endif
	196	#ifdef CONFIG_MACB
	197	if (has_emac())
	198	at91_macb_hw_init();
e08d6f3a BS	199	if (has_gmac())
e08d6f3a BS	200	at91_gmac_hw_init();
3225f34e BS	201	#endif
	202	#ifdef CONFIG_LCD
	203	if (has_lcdc())
	204	sama5d3xek_lcd_hw_init();
	205	#endif
	206	return 0;
	207	}
	208
	209	int dram_init(void)
	210	{
	211	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	212	CONFIG_SYS_SDRAM_SIZE);
	213	return 0;
	214	}
	215
e08d6f3a BS	216	int board_phy_config(struct phy_device *phydev)
	217	{
	218	/* rx data delay */
	219	ksz9021_phy_extended_write(phydev,
	220	MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
	221	/* tx data delay */
	222	ksz9021_phy_extended_write(phydev,
	223	MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
	224	/* rx/tx clock delay */
	225	ksz9021_phy_extended_write(phydev,
	226	MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
	227
	228	return 0;
	229	}
	230
3225f34e BS	231	int board_eth_init(bd_t *bis)
	232	{
	233	int rc = 0;
	234
	235	#ifdef CONFIG_MACB
	236	if (has_emac())
	237	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
e08d6f3a BS	238	if (has_gmac())
e08d6f3a BS	239	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
3668ce3c BS	240	#endif
	241	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	242	usba_udc_probe(&pdata);
	243	#ifdef CONFIG_USB_ETH_RNDIS
	244	usb_eth_initialize(bis);
	245	#endif
3225f34e BS	246	#endif
	247
	248	return rc;
	249	}
	250
	251	#ifdef CONFIG_GENERIC_ATMEL_MCI
	252	int board_mmc_init(bd_t *bis)
	253	{
	254	int rc = 0;
	255
	256	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
	257
	258	return rc;
	259	}
	260	#endif
	261
	262	/* SPI chip select control */
	263	#ifdef CONFIG_ATMEL_SPI
	264	#include <spi.h>
	265
	266	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	267	{
	268	return bus == 0 && cs < 4;
	269	}
	270
	271	void spi_cs_activate(struct spi_slave *slave)
	272	{
	273	switch (slave->cs) {
	274	case 0:
	275	at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
	276	case 1:
	277	at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
	278	case 2:
	279	at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
	280	case 3:
	281	at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
	282	default:
	283	break;
	284	}
	285	}
	286
	287	void spi_cs_deactivate(struct spi_slave *slave)
	288	{
	289	switch (slave->cs) {
	290	case 0:
	291	at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
	292	case 1:
	293	at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
	294	case 2:
	295	at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
	296	case 3:
	297	at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
	298	default:
	299	break;
	300	}
	301	}
	302	#endif /* CONFIG_ATMEL_SPI */
c5e8885a BS	303
	304	/* SPL */
	305	#ifdef CONFIG_SPL_BUILD
	306	void spl_board_init(void)
	307	{
	308	#ifdef CONFIG_SYS_USE_MMC
	309	sama5d3xek_mci_hw_init();
	310	#endif
	311	}
	312
	313	static void ddr2_conf(struct atmel_mpddr *ddr2)
	314	{
	315	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
	316
	317	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	318	ATMEL_MPDDRC_CR_NR_ROW_14 \|
	319	ATMEL_MPDDRC_CR_CAS_DDR_CAS3 \|
	320	ATMEL_MPDDRC_CR_ENRDM_ON \|
	321	ATMEL_MPDDRC_CR_NB_8BANKS \|
	322	ATMEL_MPDDRC_CR_NDQS_DISABLED \|
	323	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
	324	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	325	/*
	326	* As the DDR2-SDRAm device requires a refresh time is 7.8125us
	327	* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
	328	*/
	329	ddr2->rtr = 0x411;
	330
	331	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|
	332	2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|
	333	2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \|
	334	8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \|
	335	2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \|
	336	2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \|
	337	2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \|
	338	2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
	339
	340	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET \|
	341	200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	342	28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	343	26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
	344
	345	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET \|
	346	2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	347	2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	348	7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	349	8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
	350	}
	351
	352	void mem_init(void)
	353	{
	354	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	355	struct atmel_mpddr ddr2;
	356
	357	ddr2_conf(&ddr2);
	358
	359	/* enable MPDDR clock */
	360	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	361	writel(0x4, &pmc->scer);
	362
	363	/* DDRAM2 Controller initialize */
	364	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
	365	}
	366
367	void at91_pmc_init(void)
368	{
369	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
370	u32 tmp;
371
372	tmp = AT91_PMC_PLLAR_29 \|
373	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
374	AT91_PMC_PLLXR_MUL(43) \|
375	AT91_PMC_PLLXR_DIV(1);
376	at91_plla_init(tmp);
377
378	writel(0x3 << 8, &pmc->pllicpr);
379
380	tmp = AT91_PMC_MCKR_MDIV_4 \|
381	AT91_PMC_MCKR_CSS_PLLA;
382	at91_mck_init(tmp);
383	}
384	#endif