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7644f16f SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f013dacf | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
7644f16f SR |
16 | * GNU General Public License for more details. |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
049216f0 | 26 | #include <asm/io.h> |
7644f16f SR |
27 | #include <command.h> |
28 | #include <malloc.h> | |
29 | ||
d87080b7 WD |
30 | DECLARE_GLOBAL_DATA_PTR; |
31 | ||
7644f16f SR |
32 | int board_early_init_f (void) |
33 | { | |
d1c3b275 | 34 | unsigned long CPC0_CR0Reg; |
7644f16f SR |
35 | |
36 | /* | |
2076d0a1 | 37 | * Setup GPIO pins |
7644f16f | 38 | */ |
d1c3b275 SR |
39 | CPC0_CR0Reg = mfdcr(CPC0_CR0); |
40 | mtdcr(CPC0_CR0, CPC0_CR0Reg | | |
049216f0 MF |
41 | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | |
42 | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); | |
7644f16f | 43 | |
bfc81252 | 44 | /* set output pins to high */ |
049216f0 | 45 | out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP); |
bfc81252 | 46 | /* setup for output (LED=off) */ |
049216f0 | 47 | out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); |
7644f16f SR |
48 | |
49 | /* | |
50 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
51 | * IRQ 16 405GP internally generated; active low; level sensitive | |
52 | * IRQ 17-24 RESERVED | |
53 | * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive | |
54 | * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive | |
55 | * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive | |
56 | * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive | |
57 | * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
58 | * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive | |
59 | * IRQ 31 (EXT IRQ 6) unused | |
60 | */ | |
952e7760 SR |
61 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
62 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
63 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ | |
64 | mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ | |
65 | ||
66 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ | |
67 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
68 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
7644f16f SR |
69 | |
70 | return 0; | |
71 | } | |
72 | ||
7644f16f SR |
73 | int misc_init_r (void) |
74 | { | |
d1c3b275 | 75 | unsigned long CPC0_CR0Reg; |
7644f16f SR |
76 | |
77 | /* adjust flash start and offset */ | |
78 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
79 | gd->bd->bi_flashoffset = 0; | |
80 | ||
81 | /* | |
82 | * Select cts (and not dsr) on uart1 | |
83 | */ | |
d1c3b275 SR |
84 | CPC0_CR0Reg = mfdcr(CPC0_CR0); |
85 | mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); | |
7644f16f SR |
86 | |
87 | return (0); | |
88 | } | |
89 | ||
90 | ||
91 | /* | |
92 | * Check Board Identity: | |
93 | */ | |
94 | int checkboard (void) | |
95 | { | |
77ddac94 | 96 | char str[64]; |
7644f16f SR |
97 | int i = getenv_r ("serial#", str, sizeof(str)); |
98 | ||
99 | puts ("Board: "); | |
100 | ||
101 | if (i == -1) { | |
102 | puts ("### No HW ID - assuming CPCI2DP"); | |
103 | } else { | |
104 | puts(str); | |
105 | } | |
106 | ||
107 | printf(" (Ver 1.0)"); | |
108 | ||
109 | putc ('\n'); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
6d0f6bcf | 114 | #if defined(CONFIG_SYS_EEPROM_WREN) |
7644f16f | 115 | /* Input: <dev_addr> I2C address of EEPROM device to enable. |
f013dacf WD |
116 | * <state> -1: deliver current state |
117 | * 0: disable write | |
7644f16f | 118 | * 1: enable write |
f013dacf WD |
119 | * Returns: -1: wrong device address |
120 | * 0: dis-/en- able done | |
7644f16f SR |
121 | * 0/1: current state if <state> was -1. |
122 | */ | |
123 | int eeprom_write_enable (unsigned dev_addr, int state) { | |
6d0f6bcf | 124 | if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { |
7644f16f | 125 | return -1; |
f013dacf | 126 | } else { |
7644f16f SR |
127 | switch (state) { |
128 | case 1: | |
129 | /* Enable write access, clear bit GPIO_SINT2. */ | |
049216f0 MF |
130 | out_be32((void *)GPIO0_OR, |
131 | in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); | |
7644f16f SR |
132 | state = 0; |
133 | break; | |
134 | case 0: | |
135 | /* Disable write access, set bit GPIO_SINT2. */ | |
049216f0 MF |
136 | out_be32((void *)GPIO0_OR, |
137 | in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); | |
7644f16f SR |
138 | state = 0; |
139 | break; | |
140 | default: | |
141 | /* Read current status back. */ | |
049216f0 MF |
142 | state = (0 == (in_be32((void *)GPIO0_OR) & |
143 | CONFIG_SYS_EEPROM_WP)); | |
7644f16f SR |
144 | break; |
145 | } | |
146 | } | |
147 | return state; | |
148 | } | |
149 | #endif | |
150 | ||
6d0f6bcf | 151 | #if defined(CONFIG_SYS_EEPROM_WREN) |
54841ab5 | 152 | int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
7644f16f SR |
153 | { |
154 | int query = argc == 1; | |
155 | int state = 0; | |
156 | ||
157 | if (query) { | |
158 | /* Query write access state. */ | |
6d0f6bcf | 159 | state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); |
7644f16f SR |
160 | if (state < 0) { |
161 | puts ("Query of write access state failed.\n"); | |
f013dacf | 162 | } else { |
7644f16f | 163 | printf ("Write access for device 0x%0x is %sabled.\n", |
6d0f6bcf | 164 | CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); |
7644f16f SR |
165 | state = 0; |
166 | } | |
f013dacf | 167 | } else { |
7644f16f SR |
168 | if ('0' == argv[1][0]) { |
169 | /* Disable write access. */ | |
6d0f6bcf | 170 | state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); |
f013dacf | 171 | } else { |
7644f16f | 172 | /* Enable write access. */ |
6d0f6bcf | 173 | state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); |
7644f16f SR |
174 | } |
175 | if (state < 0) { | |
176 | puts ("Setup of write access state failed.\n"); | |
177 | } | |
178 | } | |
179 | ||
180 | return state; | |
181 | } | |
182 | ||
183 | U_BOOT_CMD( | |
2076d0a1 | 184 | eepwren, 2, 0, do_eep_wren, |
2fb2604d | 185 | "Enable / disable / query EEPROM write access", |
a89c33db WD |
186 | "" |
187 | ); | |
6d0f6bcf | 188 | #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ |