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f3a8e2b7 MH |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <i2c.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/arch/clock.h> | |
11 | #include <asm/arch/fsl_serdes.h> | |
12 | #include <asm/arch/soc.h> | |
13 | #include <hwconfig.h> | |
14 | #include <ahci.h> | |
8ef0d5c4 | 15 | #include <mmc.h> |
f3a8e2b7 | 16 | #include <scsi.h> |
e8297341 | 17 | #include <fm_eth.h> |
f3a8e2b7 MH |
18 | #include <fsl_csu.h> |
19 | #include <fsl_esdhc.h> | |
20 | #include <fsl_ifc.h> | |
21 | #include "cpld.h" | |
22 | ||
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
25 | int checkboard(void) | |
26 | { | |
27 | static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; | |
c7ca8b07 | 28 | #ifndef CONFIG_SD_BOOT |
f3a8e2b7 MH |
29 | u8 cfg_rcw_src1, cfg_rcw_src2; |
30 | u32 cfg_rcw_src; | |
c7ca8b07 | 31 | #endif |
f3a8e2b7 MH |
32 | u32 sd1refclk_sel; |
33 | ||
34 | printf("Board: LS1043ARDB, boot from "); | |
35 | ||
c7ca8b07 GQ |
36 | #ifdef CONFIG_SD_BOOT |
37 | puts("SD\n"); | |
38 | #else | |
f3a8e2b7 MH |
39 | cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); |
40 | cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); | |
41 | cpld_rev_bit(&cfg_rcw_src1); | |
42 | cfg_rcw_src = cfg_rcw_src1; | |
43 | cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; | |
44 | ||
45 | if (cfg_rcw_src == 0x25) | |
46 | printf("vBank %d\n", CPLD_READ(vbank)); | |
47 | else if (cfg_rcw_src == 0x106) | |
48 | puts("NAND\n"); | |
49 | else | |
50 | printf("Invalid setting of SW4\n"); | |
c7ca8b07 | 51 | #endif |
f3a8e2b7 MH |
52 | |
53 | printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), | |
54 | CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); | |
55 | ||
56 | puts("SERDES Reference Clocks:\n"); | |
57 | sd1refclk_sel = CPLD_READ(sd1refclk_sel); | |
58 | printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
63 | int dram_init(void) | |
64 | { | |
65 | gd->ram_size = initdram(0); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | int board_early_init_f(void) | |
71 | { | |
70231009 GQ |
72 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
73 | u32 usb_pwrfault; | |
74 | ||
f3a8e2b7 | 75 | fsl_lsch2_early_init_f(); |
70231009 GQ |
76 | |
77 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
78 | out_be32(&scfg->rcwpmuxcr0, 0x3333); | |
79 | out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); | |
80 | usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << | |
81 | SCFG_USBPWRFAULT_USB3_SHIFT) | | |
82 | (SCFG_USBPWRFAULT_DEDICATED << | |
83 | SCFG_USBPWRFAULT_USB2_SHIFT) | | |
84 | (SCFG_USBPWRFAULT_SHARED << | |
85 | SCFG_USBPWRFAULT_USB1_SHIFT); | |
86 | out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); | |
87 | #endif | |
88 | ||
f3a8e2b7 MH |
89 | return 0; |
90 | } | |
91 | ||
92 | int board_init(void) | |
93 | { | |
94 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; | |
95 | ||
96 | /* | |
97 | * Set CCI-400 control override register to enable barrier | |
98 | * transaction | |
99 | */ | |
100 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); | |
101 | ||
102 | #ifdef CONFIG_FSL_IFC | |
103 | init_final_memctl_regs(); | |
104 | #endif | |
105 | ||
106 | #ifdef CONFIG_ENV_IS_NOWHERE | |
107 | gd->env_addr = (ulong)&default_environment[0]; | |
108 | #endif | |
109 | ||
110 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS | |
111 | enable_layerscape_ns_access(); | |
112 | #endif | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | int config_board_mux(void) | |
118 | { | |
119 | return 0; | |
120 | } | |
121 | ||
122 | #if defined(CONFIG_MISC_INIT_R) | |
123 | int misc_init_r(void) | |
124 | { | |
125 | config_board_mux(); | |
126 | ||
127 | return 0; | |
128 | } | |
129 | #endif | |
130 | ||
131 | int ft_board_setup(void *blob, bd_t *bd) | |
132 | { | |
133 | ft_cpu_setup(blob, bd); | |
134 | ||
e8297341 SX |
135 | #ifdef CONFIG_SYS_DPAA_FMAN |
136 | fdt_fixup_fman_ethernet(blob); | |
137 | #endif | |
f3a8e2b7 MH |
138 | return 0; |
139 | } | |
140 | ||
141 | u8 flash_read8(void *addr) | |
142 | { | |
143 | return __raw_readb(addr + 1); | |
144 | } | |
145 | ||
146 | void flash_write16(u16 val, void *addr) | |
147 | { | |
148 | u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); | |
149 | ||
150 | __raw_writew(shftval, addr); | |
151 | } | |
152 | ||
153 | u16 flash_read16(void *addr) | |
154 | { | |
155 | u16 val = __raw_readw(addr); | |
156 | ||
157 | return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); | |
158 | } |