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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / board / freescale / mx6qsabrelite / mx6qsabrelite.c
CommitLineData
bc5833c4
JL		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
f5cdc117 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
bc5833c4
JL		 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/io.h>
af2a35fb 25#include <asm/arch/clock.h>
bc5833c4 26#include <asm/arch/imx-regs.h>
d1c679a4 27#include <asm/arch/iomux.h>
cfb8b9d3 28#include <asm/arch/mx6q_pins.h>
bc5833c4
JL		 29#include <asm/errno.h>
30#include <asm/gpio.h>
af2a35fb 31#include <asm/imx-common/iomux-v3.h>
9c067828 32#include <asm/imx-common/mxc_i2c.h>
bb05b40b 33#include <asm/imx-common/boot_mode.h>
bc5833c4
JL		 34#include <mmc.h>
35#include <fsl_esdhc.h>
32369219 36#include <malloc.h>
2bf3359e 37#include <micrel.h>
2af81e27
JL		 38#include <miiphy.h>
39#include <netdev.h>
e58010b5
EN		 40#include <linux/fb.h>
41#include <ipu_pixfmt.h>
42#include <asm/arch/crm_regs.h>
43#include <asm/arch/mxc_hdmi.h>
44#include <i2c.h>
45
bc5833c4
JL		 46DECLARE_GLOBAL_DATA_PTR;
47
f5cdc117 48#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
74cf8099
EN		 49 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
bc5833c4 51
f5cdc117 52#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
74cf8099
EN		 53 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
54 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
bc5833c4 55
2af81e27 56#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
f5cdc117 57 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
2af81e27
JL		 58 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
59
373a1d8c
EN		 60#define SPI_PAD_CTRL (PAD_CTL_HYS | \
61 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
62 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63
28fdbddc
EN		 64#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
65 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
66 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
67
3174689b
TK		 68#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
69 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
70 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
71 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
72
bc5833c4
JL		 73int dram_init(void)
74{
74cf8099 75 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
bc5833c4 76
74cf8099 77 return 0;
bc5833c4
JL		 78}
79
6e142320 80iomux_v3_cfg_t const uart1_pads[] = {
cfb8b9d3
EN		 81 MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
82 MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
8e7d7b6b
TK		 83};
84
6e142320 85iomux_v3_cfg_t const uart2_pads[] = {
cfb8b9d3
EN		 86 MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
87 MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
bc5833c4
JL		 88};
89
9c067828
TK		 90#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
91
92/* I2C1, SGTL5000 */
93struct i2c_pads_info i2c_pad_info0 = {
94 .scl = {
cfb8b9d3
EN		 95 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
96 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
5fecb36c 97 .gp = IMX_GPIO_NR(3, 21)
9c067828
TK		 98 },
99 .sda = {
cfb8b9d3
EN		 100 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
101 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
5fecb36c 102 .gp = IMX_GPIO_NR(3, 28)
9c067828
TK		 103 }
104};
105
106/* I2C2 Camera, MIPI */
107struct i2c_pads_info i2c_pad_info1 = {
108 .scl = {
cfb8b9d3
EN		 109 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
110 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
5fecb36c 111 .gp = IMX_GPIO_NR(4, 12)
9c067828
TK		 112 },
113 .sda = {
cfb8b9d3
EN		 114 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
115 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
5fecb36c 116 .gp = IMX_GPIO_NR(4, 13)
9c067828
TK		 117 }
118};
119
120/* I2C3, J15 - RGB connector */
121struct i2c_pads_info i2c_pad_info2 = {
122 .scl = {
cfb8b9d3
EN		 123 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
124 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
5fecb36c 125 .gp = IMX_GPIO_NR(1, 5)
9c067828
TK		 126 },
127 .sda = {
cfb8b9d3
EN		 128 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
129 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
5fecb36c 130 .gp = IMX_GPIO_NR(7, 11)
9c067828 131 }
3174689b
TK		 132};
133
6e142320 134iomux_v3_cfg_t const usdhc3_pads[] = {
cfb8b9d3
EN		 135 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
bc5833c4
JL		 142};
143
6e142320 144iomux_v3_cfg_t const usdhc4_pads[] = {
cfb8b9d3
EN		 145 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
bc5833c4
JL		 152};
153
6e142320 154iomux_v3_cfg_t const enet_pads1[] = {
cfb8b9d3
EN		 155 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
156 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
157 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
158 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
159 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
161 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
162 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
2af81e27 164 /* pin 35 - 1 (PHY_AD2) on reset */
cfb8b9d3 165 MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27 166 /* pin 32 - 1 - (MODE0) all */
cfb8b9d3 167 MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27 168 /* pin 31 - 1 - (MODE1) all */
cfb8b9d3 169 MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27 170 /* pin 28 - 1 - (MODE2) all */
cfb8b9d3 171 MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27 172 /* pin 27 - 1 - (MODE3) all */
cfb8b9d3 173 MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27 174 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
cfb8b9d3 175 MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27 176 /* pin 42 PHY nRST */
cfb8b9d3 177 MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
2af81e27
JL		 178};
179
6e142320 180iomux_v3_cfg_t const enet_pads2[] = {
cfb8b9d3
EN		 181 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
182 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
183 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
184 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
185 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
186 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
2af81e27
JL		 187};
188
28fdbddc 189/* Button assignments for J14 */
6e142320 190static iomux_v3_cfg_t const button_pads[] = {
28fdbddc 191 /* Menu */
cfb8b9d3 192 MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
28fdbddc 193 /* Back */
cfb8b9d3 194 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
28fdbddc 195 /* Labelled Search (mapped to Power under Android) */
cfb8b9d3 196 MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
28fdbddc 197 /* Home */
cfb8b9d3 198 MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
28fdbddc 199 /* Volume Down */
cfb8b9d3 200 MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
28fdbddc 201 /* Volume Up */
cfb8b9d3 202 MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
28fdbddc
EN		 203};
204
2af81e27
JL		 205static void setup_iomux_enet(void)
206{
5d20881e
AKR		 207 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
208 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
209 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
210 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
211 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
212 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
2af81e27 213 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
5d20881e 214 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
2af81e27
JL		 215
216 /* Need delay 10ms according to KSZ9021 spec */
217 udelay(1000 * 10);
5d20881e 218 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
2af81e27
JL		 219
220 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
221}
222
6e142320 223iomux_v3_cfg_t const usb_pads[] = {
cfb8b9d3 224 MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
2ea73e9e
WG		 225};
226
bc5833c4
JL		 227static void setup_iomux_uart(void)
228{
8e7d7b6b 229 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
74cf8099 230 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
bc5833c4
JL		 231}
232
2ea73e9e
WG		 233#ifdef CONFIG_USB_EHCI_MX6
234int board_ehci_hcd_init(int port)
235{
236 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
237
238 /* Reset USB hub */
5fecb36c 239 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
2ea73e9e 240 mdelay(2);
5fecb36c 241 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
2ea73e9e
WG		 242
243 return 0;
244}
245#endif
246
bc5833c4
JL		 247#ifdef CONFIG_FSL_ESDHC
248struct fsl_esdhc_cfg usdhc_cfg[2] = {
74cf8099
EN		 249 {USDHC3_BASE_ADDR},
250 {USDHC4_BASE_ADDR},
bc5833c4
JL		 251};
252
253int board_mmc_getcd(struct mmc *mmc)
254{
74cf8099
EN		 255 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
256 int ret;
bc5833c4 257
74cf8099 258 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
5d20881e
AKR		 259 gpio_direction_input(IMX_GPIO_NR(7, 0));
260 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
74cf8099 261 } else {
5d20881e
AKR		 262 gpio_direction_input(IMX_GPIO_NR(2, 6));
263 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
74cf8099 264 }
bc5833c4 265
74cf8099 266 return ret;
bc5833c4
JL		 267}
268
269int board_mmc_init(bd_t *bis)
270{
74cf8099
EN		 271 s32 status = 0;
272 u32 index = 0;
bc5833c4 273
a2ac1b3a
BT		 274 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
275 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
276
aad4659a
AR		 277 usdhc_cfg[0].max_bus_width = 4;
278 usdhc_cfg[1].max_bus_width = 4;
279
74cf8099
EN		 280 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
281 switch (index) {
282 case 0:
283 imx_iomux_v3_setup_multiple_pads(
284 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
285 break;
286 case 1:
287 imx_iomux_v3_setup_multiple_pads(
288 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
f5cdc117
WD		 289 break;
290 default:
74cf8099 291 printf("Warning: you configured more USDHC controllers"
f5cdc117
WD		 292 "(%d) then supported by the board (%d)\n",
293 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
74cf8099
EN		 294 return status;
295 }
f5cdc117 296
74cf8099
EN		 297 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
298 }
bc5833c4 299
74cf8099 300 return status;
bc5833c4
JL		 301}
302#endif
303
373a1d8c 304#ifdef CONFIG_MXC_SPI
6e142320 305iomux_v3_cfg_t const ecspi1_pads[] = {
373a1d8c 306 /* SS1 */
cfb8b9d3
EN		 307 MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
308 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
309 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
310 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
373a1d8c
EN		 311};
312
313void setup_spi(void)
314{
ba54b927 315 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
373a1d8c
EN		 316 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
317 ARRAY_SIZE(ecspi1_pads));
318}
319#endif
320
2bf3359e 321int board_phy_config(struct phy_device *phydev)
2af81e27 322{
2af81e27 323 /* min rx data delay */
2bf3359e
TK		 324 ksz9021_phy_extended_write(phydev,
325 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
326 /* min tx data delay */
327 ksz9021_phy_extended_write(phydev,
328 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
329 /* max rx/tx clock delay, min rx/tx control */
330 ksz9021_phy_extended_write(phydev,
331 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
332 if (phydev->drv->config)
333 phydev->drv->config(phydev);
f5cdc117 334
2af81e27
JL		 335 return 0;
336}
337
338int board_eth_init(bd_t *bis)
339{
32369219
TK		 340 uint32_t base = IMX_FEC_BASE;
341 struct mii_dev *bus = NULL;
342 struct phy_device *phydev = NULL;
2af81e27
JL		 343 int ret;
344
345 setup_iomux_enet();
346
32369219
TK		 347#ifdef CONFIG_FEC_MXC
348 bus = fec_get_miibus(base, -1);
349 if (!bus)
350 return 0;
351 /* scan phy 4,5,6,7 */
352 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
353 if (!phydev) {
354 free(bus);
355 return 0;
356 }
357 printf("using phy at %d\n", phydev->addr);
358 ret = fec_probe(bis, -1, base, bus, phydev);
359 if (ret) {
2af81e27 360 printf("FEC MXC: %s:failed\n", __func__);
32369219
TK		 361 free(phydev);
362 free(bus);
363 }
364#endif
2af81e27
JL		 365 return 0;
366}
367
28fdbddc
EN		 368static void setup_buttons(void)
369{
370 imx_iomux_v3_setup_multiple_pads(button_pads,
371 ARRAY_SIZE(button_pads));
372}
373
3996a96c
EN		 374#ifdef CONFIG_CMD_SATA
375
376int setup_sata(void)
377{
378 struct iomuxc_base_regs *const iomuxc_regs
379 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
380 int ret = enable_sata_clock();
381 if (ret)
382 return ret;
383
384 clrsetbits_le32(&iomuxc_regs->gpr[13],
385 IOMUXC_GPR13_SATA_MASK,
386 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
387 |IOMUXC_GPR13_SATA_PHY_7_SATA2M
388 |IOMUXC_GPR13_SATA_SPEED_3G
389 |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
390 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
391 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
392 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
393 |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
394 |IOMUXC_GPR13_SATA_PHY_1_SLOW);
395
396 return 0;
397}
398#endif
399
e58010b5
EN		 400#if defined(CONFIG_VIDEO_IPUV3)
401
402static iomux_v3_cfg_t const backlight_pads[] = {
403 /* Backlight on RGB connector: J15 */
cfb8b9d3 404 MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
e58010b5
EN		 405#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
406
407 /* Backlight on LVDS connector: J6 */
cfb8b9d3 408 MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
e58010b5
EN		 409#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
410};
411
412static iomux_v3_cfg_t const rgb_pads[] = {
cfb8b9d3
EN		 413 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
414 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
415 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
416 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
417 MX6_PAD_DI0_PIN4__GPIO_4_20,
418 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
419 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
420 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
421 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
422 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
423 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
424 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
425 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
426 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
427 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
428 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
429 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
430 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
431 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
432 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
433 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
434 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
435 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
436 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
437 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
438 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
439 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
440 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
441 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
e58010b5
EN		 442};
443
444struct display_info_t {
445 int bus;
446 int addr;
447 int pixfmt;
448 int (*detect)(struct display_info_t const *dev);
449 void (*enable)(struct display_info_t const *dev);
450 struct fb_videomode mode;
451};
452
453
454static int detect_hdmi(struct display_info_t const *dev)
455{
1b097cff
FE		 456 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
457 return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
e58010b5
EN		 458}
459
460static void enable_hdmi(struct display_info_t const *dev)
461{
1b097cff 462 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
e58010b5
EN		 463 u8 reg;
464 printf("%s: setup HDMI monitor\n", __func__);
1b097cff 465 reg = readb(&hdmi->phy_conf0);
e58010b5 466 reg |= HDMI_PHY_CONF0_PDZ_MASK;
1b097cff
FE		 467 writeb(reg, &hdmi->phy_conf0);
468
e58010b5
EN		 469 udelay(3000);
470 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
1b097cff 471 writeb(reg, &hdmi->phy_conf0);
e58010b5
EN		 472 udelay(3000);
473 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
1b097cff
FE		 474 writeb(reg, &hdmi->phy_conf0);
475 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
e58010b5
EN		 476}
477
478static int detect_i2c(struct display_info_t const *dev)
479{
480 return ((0 == i2c_set_bus_num(dev->bus))
481 &&
482 (0 == i2c_probe(dev->addr)));
483}
484
485static void enable_lvds(struct display_info_t const *dev)
486{
487 struct iomuxc *iomux = (struct iomuxc *)
488 IOMUXC_BASE_ADDR;
489 u32 reg = readl(&iomux->gpr[2]);
490 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
491 writel(reg, &iomux->gpr[2]);
492 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
493}
494
495static void enable_rgb(struct display_info_t const *dev)
496{
497 imx_iomux_v3_setup_multiple_pads(
498 rgb_pads,
499 ARRAY_SIZE(rgb_pads));
500 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
501}
502
503static struct display_info_t const displays[] = {{
504 .bus = -1,
505 .addr = 0,
506 .pixfmt = IPU_PIX_FMT_RGB24,
507 .detect = detect_hdmi,
508 .enable = enable_hdmi,
509 .mode = {
510 .name = "HDMI",
511 .refresh = 60,
512 .xres = 1024,
513 .yres = 768,
514 .pixclock = 15385,
515 .left_margin = 220,
516 .right_margin = 40,
517 .upper_margin = 21,
518 .lower_margin = 7,
519 .hsync_len = 60,
520 .vsync_len = 10,
521 .sync = FB_SYNC_EXT,
522 .vmode = FB_VMODE_NONINTERLACED
523} }, {
524 .bus = 2,
525 .addr = 0x4,
526 .pixfmt = IPU_PIX_FMT_LVDS666,
527 .detect = detect_i2c,
528 .enable = enable_lvds,
529 .mode = {
530 .name = "Hannstar-XGA",
531 .refresh = 60,
532 .xres = 1024,
533 .yres = 768,
534 .pixclock = 15385,
535 .left_margin = 220,
536 .right_margin = 40,
537 .upper_margin = 21,
538 .lower_margin = 7,
539 .hsync_len = 60,
540 .vsync_len = 10,
541 .sync = FB_SYNC_EXT,
542 .vmode = FB_VMODE_NONINTERLACED
543} }, {
544 .bus = 2,
545 .addr = 0x38,
546 .pixfmt = IPU_PIX_FMT_LVDS666,
547 .detect = detect_i2c,
548 .enable = enable_lvds,
549 .mode = {
550 .name = "wsvga-lvds",
551 .refresh = 60,
552 .xres = 1024,
553 .yres = 600,
554 .pixclock = 15385,
555 .left_margin = 220,
556 .right_margin = 40,
557 .upper_margin = 21,
558 .lower_margin = 7,
559 .hsync_len = 60,
560 .vsync_len = 10,
561 .sync = FB_SYNC_EXT,
562 .vmode = FB_VMODE_NONINTERLACED
563} }, {
564 .bus = 2,
565 .addr = 0x48,
566 .pixfmt = IPU_PIX_FMT_RGB666,
567 .detect = detect_i2c,
568 .enable = enable_rgb,
569 .mode = {
570 .name = "wvga-rgb",
571 .refresh = 57,
572 .xres = 800,
573 .yres = 480,
574 .pixclock = 37037,
575 .left_margin = 40,
576 .right_margin = 60,
577 .upper_margin = 10,
578 .lower_margin = 10,
579 .hsync_len = 20,
580 .vsync_len = 10,
581 .sync = 0,
582 .vmode = FB_VMODE_NONINTERLACED
583} } };
584
585int board_video_skip(void)
586{
587 int i;
588 int ret;
589 char const *panel = getenv("panel");
590 if (!panel) {
591 for (i = 0; i < ARRAY_SIZE(displays); i++) {
592 struct display_info_t const *dev = displays+i;
593 if (dev->detect(dev)) {
594 panel = dev->mode.name;
595 printf("auto-detected panel %s\n", panel);
596 break;
597 }
598 }
599 if (!panel) {
600 panel = displays[0].mode.name;
601 printf("No panel detected: default to %s\n", panel);
602 }
603 } else {
604 for (i = 0; i < ARRAY_SIZE(displays); i++) {
605 if (!strcmp(panel, displays[i].mode.name))
606 break;
607 }
608 }
609 if (i < ARRAY_SIZE(displays)) {
610 ret = ipuv3_fb_init(&displays[i].mode, 0,
611 displays[i].pixfmt);
612 if (!ret) {
613 displays[i].enable(displays+i);
614 printf("Display: %s (%ux%u)\n",
615 displays[i].mode.name,
616 displays[i].mode.xres,
617 displays[i].mode.yres);
618 } else
619 printf("LCD %s cannot be configured: %d\n",
620 displays[i].mode.name, ret);
621 } else {
622 printf("unsupported panel %s\n", panel);
623 ret = -EINVAL;
624 }
625 return (0 != ret);
626}
627
628static void setup_display(void)
629{
630 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
631 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
632 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
1b097cff 633 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
e58010b5
EN		 634
635 int reg;
636
637 /* Turn on LDB0,IPU,IPU DI0 clocks */
638 reg = __raw_readl(&mxc_ccm->CCGR3);
639 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
640 |MXC_CCM_CCGR3_LDB_DI0_MASK;
641 writel(reg, &mxc_ccm->CCGR3);
642
643 /* Turn on HDMI PHY clock */
644 reg = __raw_readl(&mxc_ccm->CCGR2);
645 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
646 |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
647 writel(reg, &mxc_ccm->CCGR2);
648
649 /* clear HDMI PHY reset */
1b097cff 650 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
e58010b5
EN		 651
652 /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
653 writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
654 writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
655
656 /* set LDB0, LDB1 clk select to 011/011 */
657 reg = readl(&mxc_ccm->cs2cdr);
658 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
659 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
660 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
661 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
662 writel(reg, &mxc_ccm->cs2cdr);
663
664 reg = readl(&mxc_ccm->cscmr2);
665 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
666 writel(reg, &mxc_ccm->cscmr2);
667
668 reg = readl(&mxc_ccm->chsccdr);
669 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
670 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
671 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
672 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
673 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
674 |(CHSCCDR_PODF_DIVIDE_BY_3
675 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
676 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
677 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
678 writel(reg, &mxc_ccm->chsccdr);
679
680 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
681 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
682 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
683 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
684 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
685 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
686 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
687 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
688 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
689 writel(reg, &iomux->gpr[2]);
690
691 reg = readl(&iomux->gpr[3]);
692 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
693 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
694 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
695 writel(reg, &iomux->gpr[3]);
696
697 /* backlights off until needed */
698 imx_iomux_v3_setup_multiple_pads(backlight_pads,
699 ARRAY_SIZE(backlight_pads));
700 gpio_direction_input(LVDS_BACKLIGHT_GP);
701 gpio_direction_input(RGB_BACKLIGHT_GP);
702}
703#endif
704
bc5833c4
JL		 705int board_early_init_f(void)
706{
28fdbddc
EN		 707 setup_iomux_uart();
708 setup_buttons();
bc5833c4 709
e58010b5
EN		 710#if defined(CONFIG_VIDEO_IPUV3)
711 setup_display();
712#endif
28fdbddc 713 return 0;
bc5833c4
JL		 714}
715
e58010b5
EN		 716/*
717 * Do not overwrite the console
718 * Use always serial for U-Boot console
719 */
720int overwrite_console(void)
721{
722 return 1;
723}
724
bc5833c4
JL		 725int board_init(void)
726{
74cf8099
EN		 727 /* address of boot parameters */
728 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
bc5833c4 729
d928a8f3
EN		 730#ifdef CONFIG_MXC_SPI
731 setup_spi();
732#endif
9c067828
TK		 733 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
734 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
735 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
d928a8f3 736
3996a96c
EN		 737#ifdef CONFIG_CMD_SATA
738 setup_sata();
739#endif
740
74cf8099 741 return 0;
bc5833c4
JL		 742}
743
744int checkboard(void)
745{
74cf8099 746 puts("Board: MX6Q-Sabre Lite\n");
bc5833c4 747
74cf8099 748 return 0;
bc5833c4 749}
28fdbddc
EN		 750
751struct button_key {
752 char const *name;
753 unsigned gpnum;
754 char ident;
755};
756
757static struct button_key const buttons[] = {
5fecb36c
SB		 758 {"back", IMX_GPIO_NR(2, 2), 'B'},
759 {"home", IMX_GPIO_NR(2, 4), 'H'},
760 {"menu", IMX_GPIO_NR(2, 1), 'M'},
761 {"search", IMX_GPIO_NR(2, 3), 'S'},
762 {"volup", IMX_GPIO_NR(7, 13), 'V'},
763 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
28fdbddc
EN		 764};
765
766/*
767 * generate a null-terminated string containing the buttons pressed
768 * returns number of keys pressed
769 */
770static int read_keys(char *buf)
771{
772 int i, numpressed = 0;
773 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
774 if (!gpio_get_value(buttons[i].gpnum))
775 buf[numpressed++] = buttons[i].ident;
776 }
777 buf[numpressed] = '\0';
778 return numpressed;
779}
780
781static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
782{
783 char envvalue[ARRAY_SIZE(buttons)+1];
784 int numpressed = read_keys(envvalue);
785 setenv("keybd", envvalue);
786 return numpressed == 0;
787}
788
789U_BOOT_CMD(
790 kbd, 1, 1, do_kbd,
791 "Tests for keypresses, sets 'keybd' environment variable",
792 "Returns 0 (true) to shell if key is pressed."
793);
794
795#ifdef CONFIG_PREBOOT
796static char const kbd_magic_prefix[] = "key_magic";
797static char const kbd_command_prefix[] = "key_cmd";
798
799static void preboot_keys(void)
800{
801 int numpressed;
802 char keypress[ARRAY_SIZE(buttons)+1];
803 numpressed = read_keys(keypress);
804 if (numpressed) {
805 char *kbd_magic_keys = getenv("magic_keys");
806 char *suffix;
807 /*
808 * loop over all magic keys
809 */
810 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
811 char *keys;
812 char magic[sizeof(kbd_magic_prefix) + 1];
813 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
814 keys = getenv(magic);
815 if (keys) {
816 if (!strcmp(keys, keypress))
817 break;
818 }
819 }
820 if (*suffix) {
821 char cmd_name[sizeof(kbd_command_prefix) + 1];
822 char *cmd;
823 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
824 cmd = getenv(cmd_name);
825 if (cmd) {
826 setenv("preboot", cmd);
827 return;
828 }
829 }
830 }
831}
832#endif
833
bb05b40b
TK		 834#ifdef CONFIG_CMD_BMODE
835static const struct boot_mode board_boot_modes[] = {
836 /* 4 bit bus width */
837 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
838 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
839 {NULL, 0},
840};
841#endif
842
28fdbddc
EN		 843int misc_init_r(void)
844{
845#ifdef CONFIG_PREBOOT
846 preboot_keys();
847#endif
bb05b40b
TK		 848
849#ifdef CONFIG_CMD_BMODE
850 add_board_boot_modes(board_boot_modes);
851#endif
28fdbddc
EN		 852 return 0;
853}
"Das U-Boot" Source Tree