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7d393aed WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * | |
24 | * TODO: clean-up | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include "pip405.h" | |
29 | #include <asm/processor.h> | |
30 | #include <i2c.h> | |
28c34504 | 31 | #include <stdio_dev.h> |
7d393aed WD |
32 | #include "../common/isa.h" |
33 | #include "../common/common_util.h" | |
34 | ||
d87080b7 WD |
35 | DECLARE_GLOBAL_DATA_PTR; |
36 | ||
7d393aed WD |
37 | #undef SDRAM_DEBUG |
38 | ||
7d393aed WD |
39 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ |
40 | #ifndef __ldiv_t_defined | |
41 | typedef struct { | |
42 | long int quot; /* Quotient */ | |
43 | long int rem; /* Remainder */ | |
44 | } ldiv_t; | |
45 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
46 | ||
47 | # define __ldiv_t_defined 1 | |
48 | #endif | |
49 | ||
50 | ||
51 | typedef enum { | |
52 | SDRAM_NO_ERR, | |
53 | SDRAM_SPD_COMM_ERR, | |
54 | SDRAM_SPD_CHKSUM_ERR, | |
55 | SDRAM_UNSUPPORTED_ERR, | |
56 | SDRAM_UNKNOWN_ERR | |
57 | } SDRAM_ERR; | |
58 | ||
59 | typedef struct { | |
60 | const unsigned char mode; | |
61 | const unsigned char row; | |
62 | const unsigned char col; | |
63 | const unsigned char bank; | |
64 | } SDRAM_SETUP; | |
65 | ||
66 | static const SDRAM_SETUP sdram_setup_table[] = { | |
67 | {1, 11, 9, 2}, | |
68 | {1, 11, 10, 2}, | |
69 | {2, 12, 9, 4}, | |
70 | {2, 12, 10, 4}, | |
71 | {3, 13, 9, 4}, | |
72 | {3, 13, 10, 4}, | |
73 | {3, 13, 11, 4}, | |
74 | {4, 12, 8, 2}, | |
75 | {4, 12, 8, 4}, | |
76 | {5, 11, 8, 2}, | |
77 | {5, 11, 8, 4}, | |
78 | {6, 13, 8, 2}, | |
79 | {6, 13, 8, 4}, | |
80 | {7, 13, 9, 2}, | |
81 | {7, 13, 10, 2}, | |
82 | {0, 0, 0, 0} | |
83 | }; | |
84 | ||
85 | static const unsigned char cal_indextable[] = { | |
86 | 9, 23, 25 | |
87 | }; | |
88 | ||
89 | ||
90 | /* | |
91 | * translate ns.ns/10 coding of SPD timing values | |
92 | * into 10 ps unit values | |
93 | */ | |
94 | ||
95 | unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) | |
96 | { | |
97 | unsigned short ns, ns10; | |
98 | ||
99 | /* isolate upper nibble */ | |
100 | ns = (spd_byte >> 4) & 0x0F; | |
101 | /* isolate lower nibble */ | |
102 | ns10 = (spd_byte & 0x0F); | |
103 | ||
104 | return (ns * 100 + ns10 * 10); | |
105 | } | |
106 | ||
107 | /* | |
108 | * translate ns.ns/4 coding of SPD timing values | |
109 | * into 10 ps unit values | |
110 | */ | |
111 | ||
112 | unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) | |
113 | { | |
114 | unsigned short ns, ns4; | |
115 | ||
116 | /* isolate upper 6 bits */ | |
117 | ns = (spd_byte >> 2) & 0x3F; | |
118 | /* isloate lower 2 bits */ | |
119 | ns4 = (spd_byte & 0x03); | |
120 | ||
121 | return (ns * 100 + ns4 * 25); | |
122 | } | |
123 | ||
124 | /* | |
125 | * translate ns coding of SPD timing values | |
126 | * into 10 ps unit values | |
127 | */ | |
128 | ||
129 | unsigned short NSto10PS (unsigned char spd_byte) | |
130 | { | |
131 | return (spd_byte * 100); | |
132 | } | |
133 | ||
134 | void SDRAM_err (const char *s) | |
135 | { | |
136 | #ifndef SDRAM_DEBUG | |
7d393aed WD |
137 | (void) get_clocks (); |
138 | gd->baudrate = 9600; | |
139 | serial_init (); | |
140 | #endif | |
141 | serial_puts ("\n"); | |
142 | serial_puts (s); | |
143 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
144 | for (;;); | |
145 | } | |
146 | ||
147 | ||
148 | #ifdef SDRAM_DEBUG | |
149 | ||
150 | void write_hex (unsigned char i) | |
151 | { | |
152 | char cc; | |
153 | ||
154 | cc = i >> 4; | |
155 | cc &= 0xf; | |
156 | if (cc > 9) | |
157 | serial_putc (cc + 55); | |
158 | else | |
159 | serial_putc (cc + 48); | |
160 | cc = i & 0xf; | |
161 | if (cc > 9) | |
162 | serial_putc (cc + 55); | |
163 | else | |
164 | serial_putc (cc + 48); | |
165 | } | |
166 | ||
167 | void write_4hex (unsigned long val) | |
168 | { | |
169 | write_hex ((unsigned char) (val >> 24)); | |
170 | write_hex ((unsigned char) (val >> 16)); | |
171 | write_hex ((unsigned char) (val >> 8)); | |
172 | write_hex ((unsigned char) val); | |
173 | } | |
174 | ||
175 | #endif | |
176 | ||
c837dcb1 | 177 | int board_early_init_f (void) |
7d393aed | 178 | { |
7d393aed | 179 | unsigned char datain[128]; |
77ddac94 | 180 | unsigned long sdram_size = 0; |
7d393aed WD |
181 | SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; |
182 | unsigned long memclk; | |
183 | unsigned long tmemclk = 0; | |
184 | unsigned long tmp, bank, baseaddr, bank_size; | |
185 | unsigned short i; | |
186 | unsigned char rows, cols, banks, sdram_banks, density; | |
187 | unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, | |
4e11c351 | 188 | trc_clocks; |
7d393aed WD |
189 | unsigned char cal_index, cal_val, spd_version, spd_chksum; |
190 | unsigned char buf[8]; | |
4e11c351 SR |
191 | #ifdef SDRAM_DEBUG |
192 | unsigned char tctp_clocks; | |
193 | #endif | |
194 | ||
7205e407 | 195 | /* set up the config port */ |
d1c3b275 SR |
196 | mtdcr (EBC0_CFGADDR, PB7AP); |
197 | mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); | |
198 | mtdcr (EBC0_CFGADDR, PB7CR); | |
199 | mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); | |
7d393aed WD |
200 | |
201 | memclk = get_bus_freq (tmemclk); | |
202 | tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ | |
203 | ||
204 | #ifdef SDRAM_DEBUG | |
205 | (void) get_clocks (); | |
206 | gd->baudrate = 9600; | |
207 | serial_init (); | |
208 | serial_puts ("\nstart SDRAM Setup\n"); | |
209 | #endif | |
210 | ||
211 | /* Read Serial Presence Detect Information */ | |
6d0f6bcf | 212 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
7d393aed WD |
213 | for (i = 0; i < 128; i++) |
214 | datain[i] = 127; | |
215 | i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); | |
216 | #ifdef SDRAM_DEBUG | |
217 | serial_puts ("\ni2c_read returns "); | |
218 | write_hex (i); | |
219 | serial_puts ("\n"); | |
220 | #endif | |
221 | ||
222 | #ifdef SDRAM_DEBUG | |
223 | for (i = 0; i < 128; i++) { | |
224 | write_hex (datain[i]); | |
225 | serial_puts (" "); | |
226 | if (((i + 1) % 16) == 0) | |
227 | serial_puts ("\n"); | |
228 | } | |
229 | serial_puts ("\n"); | |
230 | #endif | |
231 | spd_chksum = 0; | |
232 | for (i = 0; i < 63; i++) { | |
233 | spd_chksum += datain[i]; | |
234 | } /* endfor */ | |
235 | if (datain[63] != spd_chksum) { | |
236 | #ifdef SDRAM_DEBUG | |
237 | serial_puts ("SPD chksum: 0x"); | |
238 | write_hex (datain[63]); | |
239 | serial_puts (" != calc. chksum: 0x"); | |
240 | write_hex (spd_chksum); | |
241 | serial_puts ("\n"); | |
242 | #endif | |
243 | SDRAM_err ("SPD checksum Error"); | |
244 | } | |
245 | /* SPD seems to be ok, use it */ | |
246 | ||
247 | /* get SPD version */ | |
248 | spd_version = datain[62]; | |
249 | ||
250 | /* do some sanity checks on the kind of RAM */ | |
251 | if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ | |
252 | (datain[2] != 0x04) || /* if not SDRAM */ | |
253 | (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ | |
254 | (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ | |
8ed44d91 | 255 | (datain[126] == 0x66)) /* or a 66MHz modules */ |
7d393aed WD |
256 | SDRAM_err ("unsupported SDRAM"); |
257 | #ifdef SDRAM_DEBUG | |
258 | serial_puts ("SDRAM sanity ok\n"); | |
259 | #endif | |
260 | ||
261 | /* get number of rows/cols/banks out of byte 3+4+5 */ | |
262 | rows = datain[3]; | |
263 | cols = datain[4]; | |
264 | banks = datain[5]; | |
265 | ||
266 | /* get number of SDRAM banks out of byte 17 and | |
267 | supported CAS latencies out of byte 18 */ | |
268 | sdram_banks = datain[17]; | |
269 | supported_cal = datain[18] & ~0x81; | |
270 | ||
271 | while (t->mode != 0) { | |
272 | if ((t->row == rows) && (t->col == cols) | |
273 | && (t->bank == sdram_banks)) | |
274 | break; | |
275 | t++; | |
276 | } /* endwhile */ | |
277 | ||
278 | #ifdef SDRAM_DEBUG | |
279 | serial_puts ("rows: "); | |
280 | write_hex (rows); | |
281 | serial_puts (" cols: "); | |
282 | write_hex (cols); | |
283 | serial_puts (" banks: "); | |
284 | write_hex (banks); | |
285 | serial_puts (" mode: "); | |
286 | write_hex (t->mode); | |
287 | serial_puts ("\n"); | |
288 | #endif | |
289 | if (t->mode == 0) | |
290 | SDRAM_err ("unsupported SDRAM"); | |
291 | /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ | |
292 | #ifdef SDRAM_DEBUG | |
293 | serial_puts ("tRP: "); | |
294 | write_hex (datain[27]); | |
295 | serial_puts ("\ntRCD: "); | |
296 | write_hex (datain[29]); | |
297 | serial_puts ("\ntRAS: "); | |
298 | write_hex (datain[30]); | |
299 | serial_puts ("\n"); | |
300 | #endif | |
301 | ||
302 | trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; | |
303 | trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; | |
304 | tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; | |
305 | density = datain[31]; | |
306 | ||
307 | /* trc_clocks is sum of trp_clocks + tras_clocks */ | |
308 | trc_clocks = trp_clocks + tras_clocks; | |
4e11c351 SR |
309 | |
310 | #ifdef SDRAM_DEBUG | |
7d393aed WD |
311 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ |
312 | tctp_clocks = | |
313 | ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + | |
314 | (tmemclk - 1)) / tmemclk; | |
315 | ||
7d393aed WD |
316 | serial_puts ("c_RP: "); |
317 | write_hex (trp_clocks); | |
318 | serial_puts ("\nc_RCD: "); | |
319 | write_hex (trcd_clocks); | |
320 | serial_puts ("\nc_RAS: "); | |
321 | write_hex (tras_clocks); | |
322 | serial_puts ("\nc_RC: (RP+RAS): "); | |
323 | write_hex (trc_clocks); | |
324 | serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); | |
325 | write_hex (tctp_clocks); | |
326 | serial_puts ("\nt_CTP: RAS - RCD: "); | |
327 | write_hex ((unsigned | |
328 | char) ((NSto10PS (datain[30]) - | |
329 | NSto10PS (datain[29])) >> 8)); | |
330 | write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); | |
331 | serial_puts ("\ntmemclk: "); | |
332 | write_hex ((unsigned char) (tmemclk >> 8)); | |
333 | write_hex ((unsigned char) (tmemclk)); | |
334 | serial_puts ("\n"); | |
335 | #endif | |
336 | ||
337 | ||
338 | cal_val = 255; | |
339 | for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { | |
340 | /* is this CAS latency supported ? */ | |
341 | if ((supported_cal >> i) & 0x01) { | |
342 | buf[0] = datain[cal_indextable[cal_index]]; | |
343 | if (cal_index < 2) { | |
344 | if (NS10to10PS (buf[0], spd_version) <= tmemclk) | |
345 | cal_val = i; | |
346 | } else { | |
347 | /* SPD bytes 25+26 have another format */ | |
348 | if (NS4to10PS (buf[0], spd_version) <= tmemclk) | |
349 | cal_val = i; | |
350 | } /* endif */ | |
351 | cal_index++; | |
352 | } /* endif */ | |
353 | } /* endfor */ | |
354 | #ifdef SDRAM_DEBUG | |
355 | serial_puts ("CAL: "); | |
356 | write_hex (cal_val + 1); | |
357 | serial_puts ("\n"); | |
358 | #endif | |
359 | ||
360 | if (cal_val == 255) | |
361 | SDRAM_err ("unsupported SDRAM"); | |
362 | ||
363 | /* get SDRAM timing register */ | |
95b602ba | 364 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 365 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; |
7d393aed WD |
366 | /* insert CASL value */ |
367 | /* tmp |= ((unsigned long)cal_val) << 23; */ | |
368 | tmp |= ((unsigned long) cal_val) << 23; | |
369 | /* insert PTA value */ | |
370 | tmp |= ((unsigned long) (trp_clocks - 1)) << 18; | |
371 | /* insert CTP value */ | |
372 | /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ | |
373 | tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; | |
374 | /* insert LDF (always 01) */ | |
375 | tmp |= ((unsigned long) 0x01) << 14; | |
376 | /* insert RFTA value */ | |
377 | tmp |= ((unsigned long) (trc_clocks - 4)) << 2; | |
378 | /* insert RCD value */ | |
379 | tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
380 | ||
381 | #ifdef SDRAM_DEBUG | |
382 | serial_puts ("sdtr: "); | |
383 | write_4hex (tmp); | |
384 | serial_puts ("\n"); | |
385 | #endif | |
386 | ||
387 | /* write SDRAM timing register */ | |
95b602ba | 388 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 389 | mtdcr (SDRAM0_CFGDATA, tmp); |
6d0f6bcf | 390 | baseaddr = CONFIG_SYS_SDRAM_BASE; |
7d393aed WD |
391 | bank_size = (((unsigned long) density) << 22) / 2; |
392 | /* insert AM value */ | |
393 | tmp = ((unsigned long) t->mode - 1) << 13; | |
394 | /* insert SZ value; */ | |
395 | switch (bank_size) { | |
396 | case 0x00400000: | |
397 | tmp |= ((unsigned long) 0x00) << 17; | |
398 | break; | |
399 | case 0x00800000: | |
400 | tmp |= ((unsigned long) 0x01) << 17; | |
401 | break; | |
402 | case 0x01000000: | |
403 | tmp |= ((unsigned long) 0x02) << 17; | |
404 | break; | |
405 | case 0x02000000: | |
406 | tmp |= ((unsigned long) 0x03) << 17; | |
407 | break; | |
408 | case 0x04000000: | |
409 | tmp |= ((unsigned long) 0x04) << 17; | |
410 | break; | |
411 | case 0x08000000: | |
412 | tmp |= ((unsigned long) 0x05) << 17; | |
413 | break; | |
414 | case 0x10000000: | |
415 | tmp |= ((unsigned long) 0x06) << 17; | |
416 | break; | |
417 | default: | |
418 | SDRAM_err ("unsupported SDRAM"); | |
419 | } /* endswitch */ | |
420 | /* get SDRAM bank 0 register */ | |
95b602ba | 421 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 422 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
423 | bank |= (baseaddr | tmp | 0x01); |
424 | #ifdef SDRAM_DEBUG | |
425 | serial_puts ("bank0: baseaddr: "); | |
426 | write_4hex (baseaddr); | |
427 | serial_puts (" banksize: "); | |
428 | write_4hex (bank_size); | |
429 | serial_puts (" mb0cf: "); | |
430 | write_4hex (bank); | |
431 | serial_puts ("\n"); | |
432 | #endif | |
433 | baseaddr += bank_size; | |
434 | sdram_size += bank_size; | |
435 | ||
436 | /* write SDRAM bank 0 register */ | |
95b602ba | 437 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 438 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
439 | |
440 | /* get SDRAM bank 1 register */ | |
95b602ba | 441 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 442 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
443 | sdram_size = 0; |
444 | ||
445 | #ifdef SDRAM_DEBUG | |
446 | serial_puts ("bank1: baseaddr: "); | |
447 | write_4hex (baseaddr); | |
448 | serial_puts (" banksize: "); | |
449 | write_4hex (bank_size); | |
450 | #endif | |
451 | if (banks == 2) { | |
452 | bank |= (baseaddr | tmp | 0x01); | |
453 | baseaddr += bank_size; | |
454 | sdram_size += bank_size; | |
455 | } /* endif */ | |
456 | #ifdef SDRAM_DEBUG | |
457 | serial_puts (" mb1cf: "); | |
458 | write_4hex (bank); | |
459 | serial_puts ("\n"); | |
460 | #endif | |
461 | /* write SDRAM bank 1 register */ | |
95b602ba | 462 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 463 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
464 | |
465 | /* get SDRAM bank 2 register */ | |
95b602ba | 466 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 467 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
468 | |
469 | bank |= (baseaddr | tmp | 0x01); | |
470 | ||
471 | #ifdef SDRAM_DEBUG | |
472 | serial_puts ("bank2: baseaddr: "); | |
473 | write_4hex (baseaddr); | |
474 | serial_puts (" banksize: "); | |
475 | write_4hex (bank_size); | |
476 | serial_puts (" mb2cf: "); | |
477 | write_4hex (bank); | |
478 | serial_puts ("\n"); | |
479 | #endif | |
480 | ||
481 | baseaddr += bank_size; | |
482 | sdram_size += bank_size; | |
483 | ||
484 | /* write SDRAM bank 2 register */ | |
95b602ba | 485 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 486 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
487 | |
488 | /* get SDRAM bank 3 register */ | |
95b602ba | 489 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 490 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
491 | |
492 | #ifdef SDRAM_DEBUG | |
493 | serial_puts ("bank3: baseaddr: "); | |
494 | write_4hex (baseaddr); | |
495 | serial_puts (" banksize: "); | |
496 | write_4hex (bank_size); | |
497 | #endif | |
498 | ||
499 | if (banks == 2) { | |
500 | bank |= (baseaddr | tmp | 0x01); | |
501 | baseaddr += bank_size; | |
502 | sdram_size += bank_size; | |
503 | } | |
504 | /* endif */ | |
505 | #ifdef SDRAM_DEBUG | |
506 | serial_puts (" mb3cf: "); | |
507 | write_4hex (bank); | |
508 | serial_puts ("\n"); | |
509 | #endif | |
510 | ||
511 | /* write SDRAM bank 3 register */ | |
95b602ba | 512 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 513 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
514 | |
515 | ||
516 | /* get SDRAM refresh interval register */ | |
95b602ba | 517 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 518 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; |
7d393aed WD |
519 | |
520 | if (tmemclk < NSto10PS (16)) | |
521 | tmp |= 0x05F00000; | |
522 | else | |
523 | tmp |= 0x03F80000; | |
524 | ||
525 | /* write SDRAM refresh interval register */ | |
95b602ba | 526 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 527 | mtdcr (SDRAM0_CFGDATA, tmp); |
7d393aed WD |
528 | |
529 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
95b602ba | 530 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 531 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; |
95b602ba | 532 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 533 | mtdcr (SDRAM0_CFGDATA, tmp); |
7d393aed WD |
534 | |
535 | ||
7d393aed WD |
536 | /*-------------------------------------------------------------------------+ |
537 | | Interrupt controller setup for the PIP405 board. | |
538 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
539 | | IRQ 16 405GP internally generated; active low; level sensitive | |
540 | | IRQ 17-24 RESERVED | |
541 | | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive | |
542 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
543 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
544 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
545 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
546 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
547 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
548 | | Note for PIP405 board: | |
549 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
550 | | the Interrupt Controller in the South Bridge has caused the | |
551 | | interrupt. The IC must be read to determine which device | |
552 | | caused the interrupt. | |
553 | | | |
554 | +-------------------------------------------------------------------------*/ | |
952e7760 SR |
555 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
556 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
557 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ | |
558 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
559 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
560 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
561 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
7d393aed WD |
562 | |
563 | return 0; | |
564 | } | |
565 | ||
21be309b DM |
566 | int board_early_init_r(void) |
567 | { | |
568 | int mode; | |
569 | ||
570 | /* | |
571 | * since we are relocated, we can finally enable i-cache | |
572 | * and set up the flash CS correctly | |
573 | */ | |
574 | icache_enable(); | |
575 | setup_cs_reloc(); | |
576 | /* get and display boot mode */ | |
577 | mode = get_boot_mode(); | |
578 | if (mode & BOOT_PCI) | |
579 | printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? | |
580 | "MPS" : "Flash"); | |
581 | else | |
582 | printf("%s Boot\n", (mode & BOOT_MPS) ? | |
583 | "MPS" : "Flash"); | |
7d393aed | 584 | |
21be309b DM |
585 | return 0; |
586 | } | |
7d393aed WD |
587 | /* ------------------------------------------------------------------------- */ |
588 | ||
589 | /* | |
590 | * Check Board Identity: | |
591 | */ | |
592 | ||
593 | int checkboard (void) | |
594 | { | |
77ddac94 | 595 | char s[50]; |
7d393aed WD |
596 | unsigned char bc; |
597 | int i; | |
598 | backup_t *b = (backup_t *) s; | |
599 | ||
600 | puts ("Board: "); | |
601 | ||
cdb74977 | 602 | i = getenv_f("serial#", (char *)s, 32); |
77ddac94 | 603 | if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { |
7d393aed WD |
604 | get_backup_values (b); |
605 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
606 | puts ("### No HW ID - assuming PIP405"); | |
607 | } else { | |
608 | b->serial_name[6] = 0; | |
609 | printf ("%s SN: %s", b->serial_name, | |
610 | &b->serial_name[7]); | |
611 | } | |
612 | } else { | |
613 | s[6] = 0; | |
614 | printf ("%s SN: %s", s, &s[7]); | |
615 | } | |
616 | bc = in8 (CONFIG_PORT_ADDR); | |
617 | printf (" Boot Config: 0x%x\n", bc); | |
618 | return (0); | |
619 | } | |
620 | ||
621 | ||
622 | /* ------------------------------------------------------------------------- */ | |
623 | /* ------------------------------------------------------------------------- */ | |
624 | /* | |
625 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
626 | the necessary info for SDRAM controller configuration | |
627 | */ | |
628 | /* ------------------------------------------------------------------------- */ | |
629 | /* ------------------------------------------------------------------------- */ | |
630 | static int test_dram (unsigned long ramsize); | |
631 | ||
9973e3c6 | 632 | phys_size_t initdram (int board_type) |
7d393aed | 633 | { |
7d393aed WD |
634 | unsigned long bank_reg[4], tmp, bank_size; |
635 | int i, ds; | |
636 | unsigned long TotalSize; | |
637 | ||
638 | ds = 0; | |
639 | /* since the DRAM controller is allready set up, | |
640 | * calculate the size with the bank registers | |
641 | */ | |
95b602ba | 642 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 643 | bank_reg[0] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 644 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 645 | bank_reg[1] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 646 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 647 | bank_reg[2] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 648 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 649 | bank_reg[3] = mfdcr (SDRAM0_CFGDATA); |
7d393aed WD |
650 | TotalSize = 0; |
651 | for (i = 0; i < 4; i++) { | |
652 | if ((bank_reg[i] & 0x1) == 0x1) { | |
653 | tmp = (bank_reg[i] >> 17) & 0x7; | |
654 | bank_size = 4 << tmp; | |
655 | TotalSize += bank_size; | |
656 | } else | |
657 | ds = 1; | |
658 | } | |
659 | if (ds == 1) | |
660 | printf ("single-sided DIMM "); | |
661 | else | |
662 | printf ("double-sided DIMM "); | |
663 | test_dram (TotalSize * 1024 * 1024); | |
664 | /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ | |
665 | (void) get_clocks(); | |
666 | if (gd->cpu_clk > 220000000) | |
667 | TotalSize /= 2; | |
668 | return (TotalSize * 1024 * 1024); | |
669 | } | |
670 | ||
671 | /* ------------------------------------------------------------------------- */ | |
672 | ||
673 | ||
674 | static int test_dram (unsigned long ramsize) | |
675 | { | |
676 | /* not yet implemented */ | |
677 | return (1); | |
678 | } | |
679 | ||
7d393aed WD |
680 | int misc_init_r (void) |
681 | { | |
7205e407 WD |
682 | /* adjust flash start and size as well as the offset */ |
683 | gd->bd->bi_flashstart=0-flash_info[0].size; | |
6d0f6bcf | 684 | gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; |
7205e407 WD |
685 | gd->bd->bi_flashoffset=0; |
686 | ||
687 | /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ | |
d1c3b275 | 688 | if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) |
58ea142f | 689 | mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); |
7205e407 | 690 | |
7d393aed WD |
691 | return (0); |
692 | } | |
693 | ||
694 | /*************************************************************************** | |
695 | * some helping routines | |
696 | */ | |
697 | ||
698 | int overwrite_console (void) | |
699 | { | |
472d5460 YS |
700 | /* return true if console should be overwritten */ |
701 | return in8(CONFIG_PORT_ADDR) & 0x1; | |
7d393aed WD |
702 | } |
703 | ||
704 | ||
7d393aed WD |
705 | extern int isa_init (void); |
706 | ||
707 | ||
708 | void print_pip405_rev (void) | |
709 | { | |
710 | unsigned char part, vers, cfg; | |
711 | ||
712 | part = in8 (PLD_PART_REG); | |
713 | vers = in8 (PLD_VERS_REG); | |
714 | cfg = in8 (PLD_BOARD_CFG_REG); | |
715 | printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", | |
716 | 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, | |
717 | vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
718 | } | |
719 | ||
720 | extern void check_env(void); | |
721 | ||
722 | ||
723 | int last_stage_init (void) | |
724 | { | |
725 | print_pip405_rev (); | |
726 | isa_init (); | |
28c34504 | 727 | stdio_print_current_devices (); |
7d393aed WD |
728 | check_env(); |
729 | return 0; | |
730 | } | |
731 | ||
732 | /************************************************************************ | |
733 | * Print PIP405 Info | |
734 | ************************************************************************/ | |
735 | void print_pip405_info (void) | |
736 | { | |
737 | unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, | |
738 | compwr, nicvga, scsirst; | |
739 | ||
740 | part = in8 (PLD_PART_REG); | |
741 | vers = in8 (PLD_VERS_REG); | |
742 | cfg = in8 (PLD_BOARD_CFG_REG); | |
743 | ledu = in8 (PLD_LED_USER_REG); | |
744 | sysman = in8 (PLD_SYS_MAN_REG); | |
745 | flashcom = in8 (PLD_FLASH_COM_REG); | |
746 | can = in8 (PLD_CAN_REG); | |
747 | serpwr = in8 (PLD_SER_PWR_REG); | |
748 | compwr = in8 (PLD_COM_PWR_REG); | |
749 | nicvga = in8 (PLD_NIC_VGA_REG); | |
750 | scsirst = in8 (PLD_SCSI_RST_REG); | |
751 | printf ("PLD Part %d version %d\n", | |
752 | part & 0xf, vers & 0xf); | |
753 | printf ("PLD Part %d version %d\n", | |
754 | (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
755 | printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); | |
756 | printf ("Population Options %d %d %d %d\n", | |
757 | (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, | |
758 | (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); | |
759 | printf ("User LED0 %s User LED1 %s\n", | |
760 | ((ledu & 0x1) == 0x1) ? "on" : "off", | |
761 | ((ledu & 0x2) == 0x2) ? "on" : "off"); | |
762 | printf ("Additionally Options %d %d\n", | |
763 | (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); | |
764 | printf ("User Config Switch %d %d %d %d\n", | |
765 | (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, | |
766 | (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); | |
767 | switch (sysman & 0x3) { | |
768 | case 0: | |
769 | printf ("PCI Clocks are running\n"); | |
770 | break; | |
771 | case 1: | |
772 | printf ("PCI Clocks are stopped in POS State\n"); | |
773 | break; | |
774 | case 2: | |
775 | printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); | |
776 | break; | |
777 | case 3: | |
778 | printf ("PCI Clocks are stopped\n"); | |
779 | break; | |
780 | } | |
781 | switch ((sysman >> 2) & 0x3) { | |
782 | case 0: | |
783 | printf ("Main Clocks are running\n"); | |
784 | break; | |
785 | case 1: | |
786 | printf ("Main Clocks are stopped in POS State\n"); | |
787 | break; | |
788 | case 2: | |
789 | case 3: | |
790 | printf ("PCI Clocks are stopped\n"); | |
791 | break; | |
792 | } | |
793 | printf ("INIT asserts %sINT2# (SMI)\n", | |
794 | ((sysman & 0x10) == 0x10) ? "" : "not "); | |
795 | printf ("INIT asserts %sINT1# (NMI)\n", | |
796 | ((sysman & 0x20) == 0x20) ? "" : "not "); | |
797 | printf ("INIT occured %d\n", (sysman >> 6) & 0x1); | |
798 | printf ("SER1 is routed to %s\n", | |
799 | ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); | |
800 | printf ("COM2 is routed to %s\n", | |
801 | ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); | |
802 | printf ("RS485 is configured as %s duplex\n", | |
803 | ((flashcom & 0x4) == 0x4) ? "full" : "half"); | |
804 | printf ("RS485 is connected to %s\n", | |
805 | ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); | |
806 | printf ("SER1 uses handshakes %s\n", | |
807 | ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); | |
808 | printf ("Bootflash is %swriteprotected\n", | |
809 | ((flashcom & 0x20) == 0x20) ? "not " : ""); | |
810 | printf ("Bootflash VPP is %s\n", | |
811 | ((flashcom & 0x40) == 0x40) ? "on" : "off"); | |
812 | printf ("Bootsector is %swriteprotected\n", | |
813 | ((flashcom & 0x80) == 0x80) ? "not " : ""); | |
814 | switch ((can) & 0x3) { | |
815 | case 0: | |
816 | printf ("CAN Controller is on address 0x1000..0x10FF\n"); | |
817 | break; | |
818 | case 1: | |
819 | printf ("CAN Controller is on address 0x8000..0x80FF\n"); | |
820 | break; | |
821 | case 2: | |
822 | printf ("CAN Controller is on address 0xE000..0xE0FF\n"); | |
823 | break; | |
824 | case 3: | |
825 | printf ("CAN Controller is disabled\n"); | |
826 | break; | |
827 | } | |
828 | switch ((can >> 2) & 0x3) { | |
829 | case 0: | |
830 | printf ("CAN Controller Reset is ISA Reset\n"); | |
831 | break; | |
832 | case 1: | |
833 | printf ("CAN Controller Reset is ISA Reset and POS State\n"); | |
834 | break; | |
835 | case 2: | |
836 | case 3: | |
837 | printf ("CAN Controller is in reset\n"); | |
838 | break; | |
839 | } | |
840 | if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) | |
841 | printf ("CAN Interrupt is disabled\n"); | |
842 | else | |
843 | printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); | |
844 | switch (serpwr & 0x3) { | |
845 | case 0: | |
846 | printf ("SER0 Drivers are enabled\n"); | |
847 | break; | |
848 | case 1: | |
849 | printf ("SER0 Drivers are disabled in the POS state\n"); | |
850 | break; | |
851 | case 2: | |
852 | case 3: | |
853 | printf ("SER0 Drivers are disabled\n"); | |
854 | break; | |
855 | } | |
856 | switch ((serpwr >> 2) & 0x3) { | |
857 | case 0: | |
858 | printf ("SER1 Drivers are enabled\n"); | |
859 | break; | |
860 | case 1: | |
861 | printf ("SER1 Drivers are disabled in the POS state\n"); | |
862 | break; | |
863 | case 2: | |
864 | case 3: | |
865 | printf ("SER1 Drivers are disabled\n"); | |
866 | break; | |
867 | } | |
868 | switch (compwr & 0x3) { | |
869 | case 0: | |
870 | printf ("COM1 Drivers are enabled\n"); | |
871 | break; | |
872 | case 1: | |
873 | printf ("COM1 Drivers are disabled in the POS state\n"); | |
874 | break; | |
875 | case 2: | |
876 | case 3: | |
877 | printf ("COM1 Drivers are disabled\n"); | |
878 | break; | |
879 | } | |
880 | switch ((compwr >> 2) & 0x3) { | |
881 | case 0: | |
882 | printf ("COM2 Drivers are enabled\n"); | |
883 | break; | |
884 | case 1: | |
885 | printf ("COM2 Drivers are disabled in the POS state\n"); | |
886 | break; | |
887 | case 2: | |
888 | case 3: | |
889 | printf ("COM2 Drivers are disabled\n"); | |
890 | break; | |
891 | } | |
892 | switch ((nicvga) & 0x3) { | |
893 | case 0: | |
894 | printf ("PHY is running\n"); | |
895 | break; | |
896 | case 1: | |
897 | printf ("PHY is in Power save mode in POS state\n"); | |
898 | break; | |
899 | case 2: | |
900 | case 3: | |
901 | printf ("PHY is in Power save mode\n"); | |
902 | break; | |
903 | } | |
904 | switch ((nicvga >> 2) & 0x3) { | |
905 | case 0: | |
906 | printf ("VGA is running\n"); | |
907 | break; | |
908 | case 1: | |
909 | printf ("VGA is in Power save mode in POS state\n"); | |
910 | break; | |
911 | case 2: | |
912 | case 3: | |
913 | printf ("VGA is in Power save mode\n"); | |
914 | break; | |
915 | } | |
916 | printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); | |
917 | printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); | |
918 | printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, | |
919 | (nicvga >> 7) & 0x1); | |
920 | switch ((scsirst) & 0x3) { | |
921 | case 0: | |
922 | printf ("SCSI Controller is running\n"); | |
923 | break; | |
924 | case 1: | |
925 | printf ("SCSI Controller is in Power save mode in POS state\n"); | |
926 | break; | |
927 | case 2: | |
928 | case 3: | |
929 | printf ("SCSI Controller is in Power save mode\n"); | |
930 | break; | |
931 | } | |
932 | printf ("SCSI termination is %s\n", | |
933 | ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); | |
934 | printf ("SCSI Controller is %sreseted\n", | |
935 | ((scsirst & 0x10) == 0x10) ? "" : "not "); | |
936 | printf ("IDE disks are %sreseted\n", | |
937 | ((scsirst & 0x20) == 0x20) ? "" : "not "); | |
938 | printf ("ISA Bus is %sreseted\n", | |
939 | ((scsirst & 0x40) == 0x40) ? "" : "not "); | |
940 | printf ("Super IO is %sreseted\n", | |
941 | ((scsirst & 0x80) == 0x80) ? "" : "not "); | |
942 | } | |
943 | ||
944 | void user_led0 (unsigned char on) | |
945 | { | |
472d5460 | 946 | if (on == true) |
7d393aed WD |
947 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); |
948 | else | |
949 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); | |
950 | } | |
951 | ||
952 | void user_led1 (unsigned char on) | |
953 | { | |
472d5460 | 954 | if (on == true) |
7d393aed WD |
955 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); |
956 | else | |
957 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); | |
958 | } | |
959 | ||
960 | void ide_set_reset (int idereset) | |
961 | { | |
962 | /* if reset = 1 IDE reset will be asserted */ | |
963 | unsigned char resreg; | |
964 | ||
965 | resreg = in8 (PLD_SCSI_RST_REG); | |
966 | if (idereset == 1) | |
967 | resreg |= 0x20; | |
968 | else { | |
969 | udelay(10000); | |
970 | resreg &= 0xdf; | |
971 | } | |
972 | out8 (PLD_SCSI_RST_REG, resreg); | |
973 | } |