3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include <stdio_dev.h>
32 #include "../common/isa.h"
33 #include "../common/common_util.h"
35 DECLARE_GLOBAL_DATA_PTR
;
39 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
40 #ifndef __ldiv_t_defined
42 long int quot
; /* Quotient */
43 long int rem
; /* Remainder */
45 extern ldiv_t ldiv (long int __numer
, long int __denom
);
47 # define __ldiv_t_defined 1
55 SDRAM_UNSUPPORTED_ERR
,
60 const unsigned char mode
;
61 const unsigned char row
;
62 const unsigned char col
;
63 const unsigned char bank
;
66 static const SDRAM_SETUP sdram_setup_table
[] = {
85 static const unsigned char cal_indextable
[] = {
91 * translate ns.ns/10 coding of SPD timing values
92 * into 10 ps unit values
95 unsigned short NS10to10PS (unsigned char spd_byte
, unsigned char spd_version
)
97 unsigned short ns
, ns10
;
99 /* isolate upper nibble */
100 ns
= (spd_byte
>> 4) & 0x0F;
101 /* isolate lower nibble */
102 ns10
= (spd_byte
& 0x0F);
104 return (ns
* 100 + ns10
* 10);
108 * translate ns.ns/4 coding of SPD timing values
109 * into 10 ps unit values
112 unsigned short NS4to10PS (unsigned char spd_byte
, unsigned char spd_version
)
114 unsigned short ns
, ns4
;
116 /* isolate upper 6 bits */
117 ns
= (spd_byte
>> 2) & 0x3F;
118 /* isloate lower 2 bits */
119 ns4
= (spd_byte
& 0x03);
121 return (ns
* 100 + ns4
* 25);
125 * translate ns coding of SPD timing values
126 * into 10 ps unit values
129 unsigned short NSto10PS (unsigned char spd_byte
)
131 return (spd_byte
* 100);
134 void SDRAM_err (const char *s
)
137 (void) get_clocks ();
143 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
150 void write_hex (unsigned char i
)
157 serial_putc (cc
+ 55);
159 serial_putc (cc
+ 48);
162 serial_putc (cc
+ 55);
164 serial_putc (cc
+ 48);
167 void write_4hex (unsigned long val
)
169 write_hex ((unsigned char) (val
>> 24));
170 write_hex ((unsigned char) (val
>> 16));
171 write_hex ((unsigned char) (val
>> 8));
172 write_hex ((unsigned char) val
);
177 int board_early_init_f (void)
179 unsigned char datain
[128];
180 unsigned long sdram_size
= 0;
181 SDRAM_SETUP
*t
= (SDRAM_SETUP
*) sdram_setup_table
;
182 unsigned long memclk
;
183 unsigned long tmemclk
= 0;
184 unsigned long tmp
, bank
, baseaddr
, bank_size
;
186 unsigned char rows
, cols
, banks
, sdram_banks
, density
;
187 unsigned char supported_cal
, trp_clocks
, trcd_clocks
, tras_clocks
,
189 unsigned char cal_index
, cal_val
, spd_version
, spd_chksum
;
190 unsigned char buf
[8];
192 unsigned char tctp_clocks
;
195 /* set up the config port */
196 mtdcr (EBC0_CFGADDR
, PB7AP
);
197 mtdcr (EBC0_CFGDATA
, CONFIG_PORT_AP
);
198 mtdcr (EBC0_CFGADDR
, PB7CR
);
199 mtdcr (EBC0_CFGDATA
, CONFIG_PORT_CR
);
201 memclk
= get_bus_freq (tmemclk
);
202 tmemclk
= 1000000000 / (memclk
/ 100); /* in 10 ps units */
205 (void) get_clocks ();
208 serial_puts ("\nstart SDRAM Setup\n");
211 /* Read Serial Presence Detect Information */
212 i2c_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
213 for (i
= 0; i
< 128; i
++)
215 i2c_read(SPD_EEPROM_ADDRESS
,0,1,datain
,128);
217 serial_puts ("\ni2c_read returns ");
223 for (i
= 0; i
< 128; i
++) {
224 write_hex (datain
[i
]);
226 if (((i
+ 1) % 16) == 0)
232 for (i
= 0; i
< 63; i
++) {
233 spd_chksum
+= datain
[i
];
235 if (datain
[63] != spd_chksum
) {
237 serial_puts ("SPD chksum: 0x");
238 write_hex (datain
[63]);
239 serial_puts (" != calc. chksum: 0x");
240 write_hex (spd_chksum
);
243 SDRAM_err ("SPD checksum Error");
245 /* SPD seems to be ok, use it */
247 /* get SPD version */
248 spd_version
= datain
[62];
250 /* do some sanity checks on the kind of RAM */
251 if ((datain
[0] < 0x80) || /* less than 128 valid bytes in SPD */
252 (datain
[2] != 0x04) || /* if not SDRAM */
253 (!((datain
[6] == 0x40) || (datain
[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
254 (datain
[7] != 0x00) || (datain
[8] != 0x01) || /* or not LVTTL signal levels */
255 (datain
[126] == 0x66)) /* or a 66MHz modules */
256 SDRAM_err ("unsupported SDRAM");
258 serial_puts ("SDRAM sanity ok\n");
261 /* get number of rows/cols/banks out of byte 3+4+5 */
266 /* get number of SDRAM banks out of byte 17 and
267 supported CAS latencies out of byte 18 */
268 sdram_banks
= datain
[17];
269 supported_cal
= datain
[18] & ~0x81;
271 while (t
->mode
!= 0) {
272 if ((t
->row
== rows
) && (t
->col
== cols
)
273 && (t
->bank
== sdram_banks
))
279 serial_puts ("rows: ");
281 serial_puts (" cols: ");
283 serial_puts (" banks: ");
285 serial_puts (" mode: ");
290 SDRAM_err ("unsupported SDRAM");
291 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
293 serial_puts ("tRP: ");
294 write_hex (datain
[27]);
295 serial_puts ("\ntRCD: ");
296 write_hex (datain
[29]);
297 serial_puts ("\ntRAS: ");
298 write_hex (datain
[30]);
302 trp_clocks
= (NSto10PS (datain
[27]) + (tmemclk
- 1)) / tmemclk
;
303 trcd_clocks
= (NSto10PS (datain
[29]) + (tmemclk
- 1)) / tmemclk
;
304 tras_clocks
= (NSto10PS (datain
[30]) + (tmemclk
- 1)) / tmemclk
;
305 density
= datain
[31];
307 /* trc_clocks is sum of trp_clocks + tras_clocks */
308 trc_clocks
= trp_clocks
+ tras_clocks
;
311 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
313 ((NSto10PS (datain
[30]) - NSto10PS (datain
[29])) +
314 (tmemclk
- 1)) / tmemclk
;
316 serial_puts ("c_RP: ");
317 write_hex (trp_clocks
);
318 serial_puts ("\nc_RCD: ");
319 write_hex (trcd_clocks
);
320 serial_puts ("\nc_RAS: ");
321 write_hex (tras_clocks
);
322 serial_puts ("\nc_RC: (RP+RAS): ");
323 write_hex (trc_clocks
);
324 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
325 write_hex (tctp_clocks
);
326 serial_puts ("\nt_CTP: RAS - RCD: ");
328 char) ((NSto10PS (datain
[30]) -
329 NSto10PS (datain
[29])) >> 8));
330 write_hex ((unsigned char) (NSto10PS (datain
[30]) - NSto10PS (datain
[29])));
331 serial_puts ("\ntmemclk: ");
332 write_hex ((unsigned char) (tmemclk
>> 8));
333 write_hex ((unsigned char) (tmemclk
));
339 for (i
= 6, cal_index
= 0; (i
> 0) && (cal_index
< 3); i
--) {
340 /* is this CAS latency supported ? */
341 if ((supported_cal
>> i
) & 0x01) {
342 buf
[0] = datain
[cal_indextable
[cal_index
]];
344 if (NS10to10PS (buf
[0], spd_version
) <= tmemclk
)
347 /* SPD bytes 25+26 have another format */
348 if (NS4to10PS (buf
[0], spd_version
) <= tmemclk
)
355 serial_puts ("CAL: ");
356 write_hex (cal_val
+ 1);
361 SDRAM_err ("unsupported SDRAM");
363 /* get SDRAM timing register */
364 mtdcr (SDRAM0_CFGADDR
, SDRAM0_TR
);
365 tmp
= mfdcr (SDRAM0_CFGDATA
) & ~0x018FC01F;
366 /* insert CASL value */
367 /* tmp |= ((unsigned long)cal_val) << 23; */
368 tmp
|= ((unsigned long) cal_val
) << 23;
369 /* insert PTA value */
370 tmp
|= ((unsigned long) (trp_clocks
- 1)) << 18;
371 /* insert CTP value */
372 /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
373 tmp
|= ((unsigned long) (trc_clocks
- trp_clocks
- trcd_clocks
)) << 16;
374 /* insert LDF (always 01) */
375 tmp
|= ((unsigned long) 0x01) << 14;
376 /* insert RFTA value */
377 tmp
|= ((unsigned long) (trc_clocks
- 4)) << 2;
378 /* insert RCD value */
379 tmp
|= ((unsigned long) (trcd_clocks
- 1)) << 0;
382 serial_puts ("sdtr: ");
387 /* write SDRAM timing register */
388 mtdcr (SDRAM0_CFGADDR
, SDRAM0_TR
);
389 mtdcr (SDRAM0_CFGDATA
, tmp
);
390 baseaddr
= CONFIG_SYS_SDRAM_BASE
;
391 bank_size
= (((unsigned long) density
) << 22) / 2;
392 /* insert AM value */
393 tmp
= ((unsigned long) t
->mode
- 1) << 13;
394 /* insert SZ value; */
397 tmp
|= ((unsigned long) 0x00) << 17;
400 tmp
|= ((unsigned long) 0x01) << 17;
403 tmp
|= ((unsigned long) 0x02) << 17;
406 tmp
|= ((unsigned long) 0x03) << 17;
409 tmp
|= ((unsigned long) 0x04) << 17;
412 tmp
|= ((unsigned long) 0x05) << 17;
415 tmp
|= ((unsigned long) 0x06) << 17;
418 SDRAM_err ("unsupported SDRAM");
420 /* get SDRAM bank 0 register */
421 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B0CR
);
422 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
423 bank
|= (baseaddr
| tmp
| 0x01);
425 serial_puts ("bank0: baseaddr: ");
426 write_4hex (baseaddr
);
427 serial_puts (" banksize: ");
428 write_4hex (bank_size
);
429 serial_puts (" mb0cf: ");
433 baseaddr
+= bank_size
;
434 sdram_size
+= bank_size
;
436 /* write SDRAM bank 0 register */
437 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B0CR
);
438 mtdcr (SDRAM0_CFGDATA
, bank
);
440 /* get SDRAM bank 1 register */
441 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B1CR
);
442 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
446 serial_puts ("bank1: baseaddr: ");
447 write_4hex (baseaddr
);
448 serial_puts (" banksize: ");
449 write_4hex (bank_size
);
452 bank
|= (baseaddr
| tmp
| 0x01);
453 baseaddr
+= bank_size
;
454 sdram_size
+= bank_size
;
457 serial_puts (" mb1cf: ");
461 /* write SDRAM bank 1 register */
462 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B1CR
);
463 mtdcr (SDRAM0_CFGDATA
, bank
);
465 /* get SDRAM bank 2 register */
466 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B2CR
);
467 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
469 bank
|= (baseaddr
| tmp
| 0x01);
472 serial_puts ("bank2: baseaddr: ");
473 write_4hex (baseaddr
);
474 serial_puts (" banksize: ");
475 write_4hex (bank_size
);
476 serial_puts (" mb2cf: ");
481 baseaddr
+= bank_size
;
482 sdram_size
+= bank_size
;
484 /* write SDRAM bank 2 register */
485 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B2CR
);
486 mtdcr (SDRAM0_CFGDATA
, bank
);
488 /* get SDRAM bank 3 register */
489 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B3CR
);
490 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
493 serial_puts ("bank3: baseaddr: ");
494 write_4hex (baseaddr
);
495 serial_puts (" banksize: ");
496 write_4hex (bank_size
);
500 bank
|= (baseaddr
| tmp
| 0x01);
501 baseaddr
+= bank_size
;
502 sdram_size
+= bank_size
;
506 serial_puts (" mb3cf: ");
511 /* write SDRAM bank 3 register */
512 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B3CR
);
513 mtdcr (SDRAM0_CFGDATA
, bank
);
516 /* get SDRAM refresh interval register */
517 mtdcr (SDRAM0_CFGADDR
, SDRAM0_RTR
);
518 tmp
= mfdcr (SDRAM0_CFGDATA
) & ~0x3FF80000;
520 if (tmemclk
< NSto10PS (16))
525 /* write SDRAM refresh interval register */
526 mtdcr (SDRAM0_CFGADDR
, SDRAM0_RTR
);
527 mtdcr (SDRAM0_CFGDATA
, tmp
);
529 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
530 mtdcr (SDRAM0_CFGADDR
, SDRAM0_CFG
);
531 tmp
= (mfdcr (SDRAM0_CFGDATA
) & ~0xFFE00000) | 0x80E00000;
532 mtdcr (SDRAM0_CFGADDR
, SDRAM0_CFG
);
533 mtdcr (SDRAM0_CFGDATA
, tmp
);
536 /*-------------------------------------------------------------------------+
537 | Interrupt controller setup for the PIP405 board.
538 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
539 | IRQ 16 405GP internally generated; active low; level sensitive
541 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
542 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
543 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
544 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
545 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
546 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
547 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
548 | Note for PIP405 board:
549 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
550 | the Interrupt Controller in the South Bridge has caused the
551 | interrupt. The IC must be read to determine which device
552 | caused the interrupt.
554 +-------------------------------------------------------------------------*/
555 mtdcr (UIC0SR
, 0xFFFFFFFF); /* clear all ints */
556 mtdcr (UIC0ER
, 0x00000000); /* disable all ints */
557 mtdcr (UIC0CR
, 0x00000000); /* set all to be non-critical (for now) */
558 mtdcr (UIC0PR
, 0xFFFFFF80); /* set int polarities */
559 mtdcr (UIC0TR
, 0x10000000); /* set int trigger levels */
560 mtdcr (UIC0VCR
, 0x00000001); /* set vect base=0,INT0 highest priority */
561 mtdcr (UIC0SR
, 0xFFFFFFFF); /* clear all ints */
566 int board_early_init_r(void)
571 * since we are relocated, we can finally enable i-cache
572 * and set up the flash CS correctly
576 /* get and display boot mode */
577 mode
= get_boot_mode();
579 printf("PCI Boot %s Map\n", (mode
& BOOT_MPS
) ?
582 printf("%s Boot\n", (mode
& BOOT_MPS
) ?
587 /* ------------------------------------------------------------------------- */
590 * Check Board Identity:
593 int checkboard (void)
598 backup_t
*b
= (backup_t
*) s
;
602 i
= getenv_f("serial#", (char *)s
, 32);
603 if ((i
== 0) || strncmp ((char *)s
, "PIP405", 6)) {
604 get_backup_values (b
);
605 if (strncmp (b
->signature
, "MPL\0", 4) != 0) {
606 puts ("### No HW ID - assuming PIP405");
608 b
->serial_name
[6] = 0;
609 printf ("%s SN: %s", b
->serial_name
,
614 printf ("%s SN: %s", s
, &s
[7]);
616 bc
= in8 (CONFIG_PORT_ADDR
);
617 printf (" Boot Config: 0x%x\n", bc
);
622 /* ------------------------------------------------------------------------- */
623 /* ------------------------------------------------------------------------- */
625 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
626 the necessary info for SDRAM controller configuration
628 /* ------------------------------------------------------------------------- */
629 /* ------------------------------------------------------------------------- */
630 static int test_dram (unsigned long ramsize
);
632 phys_size_t
initdram (int board_type
)
634 unsigned long bank_reg
[4], tmp
, bank_size
;
636 unsigned long TotalSize
;
639 /* since the DRAM controller is allready set up,
640 * calculate the size with the bank registers
642 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B0CR
);
643 bank_reg
[0] = mfdcr (SDRAM0_CFGDATA
);
644 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B1CR
);
645 bank_reg
[1] = mfdcr (SDRAM0_CFGDATA
);
646 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B2CR
);
647 bank_reg
[2] = mfdcr (SDRAM0_CFGDATA
);
648 mtdcr (SDRAM0_CFGADDR
, SDRAM0_B3CR
);
649 bank_reg
[3] = mfdcr (SDRAM0_CFGDATA
);
651 for (i
= 0; i
< 4; i
++) {
652 if ((bank_reg
[i
] & 0x1) == 0x1) {
653 tmp
= (bank_reg
[i
] >> 17) & 0x7;
654 bank_size
= 4 << tmp
;
655 TotalSize
+= bank_size
;
660 printf ("single-sided DIMM ");
662 printf ("double-sided DIMM ");
663 test_dram (TotalSize
* 1024 * 1024);
664 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
666 if (gd
->cpu_clk
> 220000000)
668 return (TotalSize
* 1024 * 1024);
671 /* ------------------------------------------------------------------------- */
674 static int test_dram (unsigned long ramsize
)
676 /* not yet implemented */
680 int misc_init_r (void)
682 /* adjust flash start and size as well as the offset */
683 gd
->bd
->bi_flashstart
=0-flash_info
[0].size
;
684 gd
->bd
->bi_flashsize
=flash_info
[0].size
-CONFIG_SYS_MONITOR_LEN
;
685 gd
->bd
->bi_flashoffset
=0;
687 /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
688 if (mfdcr(CPC0_PSR
) & PSR_ROM_LOC
)
689 mtspr(SPRN_CCR0
, (mfspr(SPRN_CCR0
) & ~0x80));
694 /***************************************************************************
695 * some helping routines
698 int overwrite_console (void)
700 /* return true if console should be overwritten */
701 return in8(CONFIG_PORT_ADDR
) & 0x1;
705 extern int isa_init (void);
708 void print_pip405_rev (void)
710 unsigned char part
, vers
, cfg
;
712 part
= in8 (PLD_PART_REG
);
713 vers
= in8 (PLD_VERS_REG
);
714 cfg
= in8 (PLD_BOARD_CFG_REG
);
715 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
716 16 - ((cfg
>> 4) & 0xf), (cfg
& 0xf) + 'A', part
& 0xf,
717 vers
& 0xf, (part
>> 4) & 0xf, (vers
>> 4) & 0xf);
720 extern void check_env(void);
723 int last_stage_init (void)
727 stdio_print_current_devices ();
732 /************************************************************************
734 ************************************************************************/
735 void print_pip405_info (void)
737 unsigned char part
, vers
, cfg
, ledu
, sysman
, flashcom
, can
, serpwr
,
738 compwr
, nicvga
, scsirst
;
740 part
= in8 (PLD_PART_REG
);
741 vers
= in8 (PLD_VERS_REG
);
742 cfg
= in8 (PLD_BOARD_CFG_REG
);
743 ledu
= in8 (PLD_LED_USER_REG
);
744 sysman
= in8 (PLD_SYS_MAN_REG
);
745 flashcom
= in8 (PLD_FLASH_COM_REG
);
746 can
= in8 (PLD_CAN_REG
);
747 serpwr
= in8 (PLD_SER_PWR_REG
);
748 compwr
= in8 (PLD_COM_PWR_REG
);
749 nicvga
= in8 (PLD_NIC_VGA_REG
);
750 scsirst
= in8 (PLD_SCSI_RST_REG
);
751 printf ("PLD Part %d version %d\n",
752 part
& 0xf, vers
& 0xf);
753 printf ("PLD Part %d version %d\n",
754 (part
>> 4) & 0xf, (vers
>> 4) & 0xf);
755 printf ("Board Revision %c\n", (cfg
& 0xf) + 'A');
756 printf ("Population Options %d %d %d %d\n",
757 (cfg
>> 4) & 0x1, (cfg
>> 5) & 0x1,
758 (cfg
>> 6) & 0x1, (cfg
>> 7) & 0x1);
759 printf ("User LED0 %s User LED1 %s\n",
760 ((ledu
& 0x1) == 0x1) ? "on" : "off",
761 ((ledu
& 0x2) == 0x2) ? "on" : "off");
762 printf ("Additionally Options %d %d\n",
763 (ledu
>> 2) & 0x1, (ledu
>> 3) & 0x1);
764 printf ("User Config Switch %d %d %d %d\n",
765 (ledu
>> 4) & 0x1, (ledu
>> 5) & 0x1,
766 (ledu
>> 6) & 0x1, (ledu
>> 7) & 0x1);
767 switch (sysman
& 0x3) {
769 printf ("PCI Clocks are running\n");
772 printf ("PCI Clocks are stopped in POS State\n");
775 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
778 printf ("PCI Clocks are stopped\n");
781 switch ((sysman
>> 2) & 0x3) {
783 printf ("Main Clocks are running\n");
786 printf ("Main Clocks are stopped in POS State\n");
790 printf ("PCI Clocks are stopped\n");
793 printf ("INIT asserts %sINT2# (SMI)\n",
794 ((sysman
& 0x10) == 0x10) ? "" : "not ");
795 printf ("INIT asserts %sINT1# (NMI)\n",
796 ((sysman
& 0x20) == 0x20) ? "" : "not ");
797 printf ("INIT occured %d\n", (sysman
>> 6) & 0x1);
798 printf ("SER1 is routed to %s\n",
799 ((flashcom
& 0x1) == 0x1) ? "RS485" : "RS232");
800 printf ("COM2 is routed to %s\n",
801 ((flashcom
& 0x2) == 0x2) ? "RS485" : "RS232");
802 printf ("RS485 is configured as %s duplex\n",
803 ((flashcom
& 0x4) == 0x4) ? "full" : "half");
804 printf ("RS485 is connected to %s\n",
805 ((flashcom
& 0x8) == 0x8) ? "COM1" : "COM2");
806 printf ("SER1 uses handshakes %s\n",
807 ((flashcom
& 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
808 printf ("Bootflash is %swriteprotected\n",
809 ((flashcom
& 0x20) == 0x20) ? "not " : "");
810 printf ("Bootflash VPP is %s\n",
811 ((flashcom
& 0x40) == 0x40) ? "on" : "off");
812 printf ("Bootsector is %swriteprotected\n",
813 ((flashcom
& 0x80) == 0x80) ? "not " : "");
814 switch ((can
) & 0x3) {
816 printf ("CAN Controller is on address 0x1000..0x10FF\n");
819 printf ("CAN Controller is on address 0x8000..0x80FF\n");
822 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
825 printf ("CAN Controller is disabled\n");
828 switch ((can
>> 2) & 0x3) {
830 printf ("CAN Controller Reset is ISA Reset\n");
833 printf ("CAN Controller Reset is ISA Reset and POS State\n");
837 printf ("CAN Controller is in reset\n");
840 if (((can
>> 4) < 3) || ((can
>> 4) == 8) || ((can
>> 4) == 13))
841 printf ("CAN Interrupt is disabled\n");
843 printf ("CAN Interrupt is ISA INT%d\n", (can
>> 4) & 0xf);
844 switch (serpwr
& 0x3) {
846 printf ("SER0 Drivers are enabled\n");
849 printf ("SER0 Drivers are disabled in the POS state\n");
853 printf ("SER0 Drivers are disabled\n");
856 switch ((serpwr
>> 2) & 0x3) {
858 printf ("SER1 Drivers are enabled\n");
861 printf ("SER1 Drivers are disabled in the POS state\n");
865 printf ("SER1 Drivers are disabled\n");
868 switch (compwr
& 0x3) {
870 printf ("COM1 Drivers are enabled\n");
873 printf ("COM1 Drivers are disabled in the POS state\n");
877 printf ("COM1 Drivers are disabled\n");
880 switch ((compwr
>> 2) & 0x3) {
882 printf ("COM2 Drivers are enabled\n");
885 printf ("COM2 Drivers are disabled in the POS state\n");
889 printf ("COM2 Drivers are disabled\n");
892 switch ((nicvga
) & 0x3) {
894 printf ("PHY is running\n");
897 printf ("PHY is in Power save mode in POS state\n");
901 printf ("PHY is in Power save mode\n");
904 switch ((nicvga
>> 2) & 0x3) {
906 printf ("VGA is running\n");
909 printf ("VGA is in Power save mode in POS state\n");
913 printf ("VGA is in Power save mode\n");
916 printf ("PHY is %sreseted\n", ((nicvga
& 0x10) == 0x10) ? "" : "not ");
917 printf ("VGA is %sreseted\n", ((nicvga
& 0x20) == 0x20) ? "" : "not ");
918 printf ("Reserved Configuration is %d %d\n", (nicvga
>> 6) & 0x1,
919 (nicvga
>> 7) & 0x1);
920 switch ((scsirst
) & 0x3) {
922 printf ("SCSI Controller is running\n");
925 printf ("SCSI Controller is in Power save mode in POS state\n");
929 printf ("SCSI Controller is in Power save mode\n");
932 printf ("SCSI termination is %s\n",
933 ((scsirst
& 0x4) == 0x4) ? "disabled" : "enabled");
934 printf ("SCSI Controller is %sreseted\n",
935 ((scsirst
& 0x10) == 0x10) ? "" : "not ");
936 printf ("IDE disks are %sreseted\n",
937 ((scsirst
& 0x20) == 0x20) ? "" : "not ");
938 printf ("ISA Bus is %sreseted\n",
939 ((scsirst
& 0x40) == 0x40) ? "" : "not ");
940 printf ("Super IO is %sreseted\n",
941 ((scsirst
& 0x80) == 0x80) ? "" : "not ");
944 void user_led0 (unsigned char on
)
947 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) | 0x1));
949 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) & 0xfe));
952 void user_led1 (unsigned char on
)
955 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) | 0x2));
957 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) & 0xfd));
960 void ide_set_reset (int idereset
)
962 /* if reset = 1 IDE reset will be asserted */
963 unsigned char resreg
;
965 resreg
= in8 (PLD_SCSI_RST_REG
);
972 out8 (PLD_SCSI_RST_REG
, resreg
);