[people/ms/u-boot.git] / board / ti / am335x / board.c

/*
 * board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;

/* MII mode defines */
#define MII_MODE_ENABLE		0x0
#define RGMII_MODE_ENABLE	0x3A

/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN		7

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(struct am335x_baseboard_id *header)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		puts("Could not probe the EEPROM; something fundamentally "
			"wrong on the I2C bus.\n");
		return -ENODEV;
	}

	/* read the eeprom using i2c */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
		     sizeof(struct am335x_baseboard_id))) {
		puts("Could not read the EEPROM; something fundamentally"
			" wrong on the I2C bus.\n");
		return -EIO;
	}

	if (header->magic != 0xEE3355AA) {
		/*
		 * read the eeprom using i2c again,
		 * but use only a 1 byte address
		 */
		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
			     sizeof(struct am335x_baseboard_id))) {
			puts("Could not read the EEPROM; something "
				"fundamentally wrong on the I2C bus.\n");
			return -EIO;
		}

		if (header->magic != 0xEE3355AA) {
			printf("Incorrect magic number (0x%x) in EEPROM\n",
					header->magic);
			return -EINVAL;
		}
	}

	return 0;
}

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
static const struct ddr_data ddr2_data = {
	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
			  (MT47H128M16RT25E_RD_DQS<<20) |
			  (MT47H128M16RT25E_RD_DQS<<10) |
			  (MT47H128M16RT25E_RD_DQS<<0)),
	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
			  (MT47H128M16RT25E_WR_DQS<<20) |
			  (MT47H128M16RT25E_WR_DQS<<10) |
			  (MT47H128M16RT25E_WR_DQS<<0)),
	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr2_cmd_ctrl_data = {
	.cmd0csratio = MT47H128M16RT25E_RATIO,
	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd1csratio = MT47H128M16RT25E_RATIO,
	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd2csratio = MT47H128M16RT25E_RATIO,
	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};

static const struct emif_regs ddr2_emif_reg_data = {
	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};

static const struct ddr_data ddr3_data = {
	.datardsratio0 = MT41J128MJT125_RD_DQS,
	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct ddr_data ddr3_beagleblack_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct ddr_data ddr3_evm_data = {
	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = MT41J128MJT125_RATIO,
	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd1csratio = MT41J128MJT125_RATIO,
	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd2csratio = MT41J128MJT125_RATIO,
	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	.cmd0csratio = MT41J512M8RH125_RATIO,
	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd1csratio = MT41J512M8RH125_RATIO,
	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd2csratio = MT41J512M8RH125_RATIO,
	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	.zq_config = MT41J128MJT125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

static struct emif_regs ddr3_evm_emif_reg_data = {
	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	.zq_config = MT41J512M8RH125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	return (serial_tstc() && serial_getc() == 'c');
}
#endif

#define OSC	(V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
		266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_evm_sk = {
		303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_bone_black = {
		400, OSC-1, 1, -1, -1, -1, -1};

const struct dpll_params *get_dpll_ddr_params(void)
{
	struct am335x_baseboard_id header;

	enable_i2c0_pin_mux();
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	if (board_is_evm_sk(&header))
		return &dpll_ddr_evm_sk;
	else if (board_is_bone_lt(&header))
		return &dpll_ddr_bone_black;
	else if (board_is_evm_15_or_later(&header))
		return &dpll_ddr_evm_sk;
	else
		return &dpll_ddr;
}

#endif

/*
 * early system init of muxing and clocks.
 */
void s_init(void)
{
	__maybe_unused struct am335x_baseboard_id header;

	/*
	 * The ROM will only have set up sufficient pinmux to allow for the
	 * first 4KiB NOR to be read, we must finish doing what we know of
	 * the NOR mux in this space in order to continue.
	 */
#ifdef CONFIG_NOR_BOOT
	asm("stmfd      sp!, {r2 - r4}");
	asm("movw       r4, #0x8A4");
	asm("movw       r3, #0x44E1");
	asm("orr        r4, r4, r3, lsl #16");
	asm("mov        r2, #9");
	asm("mov        r3, #8");
	asm("gpmc_mux:  str     r2, [r4], #4");
	asm("subs       r3, r3, #1");
	asm("bne        gpmc_mux");
	asm("ldmfd      sp!, {r2 - r4}");
#endif

#ifdef CONFIG_SPL_BUILD
	/*
	 * Save the boot parameters passed from romcode.
	 * We cannot delay the saving further than this,
	 * to prevent overwrites.
	 */
	save_omap_boot_params();
#endif

	/* WDT1 is already running when the bootloader gets control
	 * Disable it to avoid "random" resets
	 */
	writel(0xAAAA, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;
	writel(0x5555, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
	/* Setup the PLLs and the clocks for the peripherals */
	setup_clocks_for_console();

#ifdef CONFIG_SERIAL1
	enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
	enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
	enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
	enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
	enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
	enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */

	uart_soft_reset();

#if defined(CONFIG_NOR_BOOT)
	/* We want our console now. */
	gd->baudrate = CONFIG_BAUDRATE;
	serial_init();
	gd->have_console = 1;
#else
	gd = &gdata;

	preloader_console_init();
#endif

	prcm_init();

	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	/* Enable RTC32K clock */
	rtc32k_enable();

	enable_board_pin_mux(&header);
	if (board_is_evm_sk(&header)) {
		/*
		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
		 * This is safe enough to do on older revs.
		 */
		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	}

	if (board_is_evm_sk(&header))
		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
	else if (board_is_bone_lt(&header))
		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
			   &ddr3_beagleblack_data,
			   &ddr3_beagleblack_cmd_ctrl_data,
			   &ddr3_beagleblack_emif_reg_data, 0);
	else if (board_is_evm_15_or_later(&header))
		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
	else
		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
#endif
}

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
#ifdef CONFIG_NOR
	const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
		STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
		STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
#endif

	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;

	gpmc_init();

#ifdef CONFIG_NOR
	/* Reconfigure CS0 for NOR instead of NAND. */
	enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
			      CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
#endif

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	char safe_string[HDR_NAME_LEN + 1];
	struct am335x_baseboard_id header;

	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	/* Now set variables based on the header. */
	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	safe_string[sizeof(header.name)] = 0;
	setenv("board_name", safe_string);

	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	safe_string[sizeof(header.version)] = 0;
	setenv("board_rev", safe_string);
#endif

	return 0;
}
#endif

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_id		= 0,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_id		= 1,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	int rv, n = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	__maybe_unused struct am335x_baseboard_id header;

	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

#ifdef CONFIG_DRIVER_TI_CPSW
	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
	    board_is_idk(&header)) {
		writel(MII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_MII;
	} else {
		writel(RGMII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_RGMII;
	}

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
#endif

	/*
	 *
	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
	 * operating points.  So we must set the TX clock delay feature
	 * in the AR8051 PHY.  Since we only support a single ethernet
	 * device in U-Boot, we only do this for the first instance.
	 */
#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
#define AR8051_PHY_DEBUG_DATA_REG	0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
#define AR8051_RGMII_TX_CLK_DLY		0x100

	if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
		const char *devname;
		devname = miiphy_get_current_dev();

		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
				AR8051_DEBUG_RGMII_CLK_DLY_REG);
		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
				AR8051_RGMII_TX_CLK_DLY);
	}
#endif
#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
	if (is_valid_ether_addr(mac_addr))
		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);

	rv = usb_eth_initialize(bis);
	if (rv < 0)
		printf("Error %d registering USB_ETHER\n", rv);
	else
		n += rv;
#endif
	return n;
}
#endif
Commit	Line	Data
e363426e PK	1	/*
	2	* board.c
	3	*
	4	* Board functions for TI AM335X based boards
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
e363426e PK	9	*/
	10
	11	#include <common.h>
	12	#include <errno.h>
	13	#include <spl.h>
	14	#include <asm/arch/cpu.h>
	15	#include <asm/arch/hardware.h>
	16	#include <asm/arch/omap.h>
	17	#include <asm/arch/ddr_defs.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/gpio.h>
	20	#include <asm/arch/mmc_host_def.h>
	21	#include <asm/arch/sys_proto.h>
cd8845d7	22	#include <asm/arch/mem.h>
e363426e PK	23	#include <asm/io.h>
	24	#include <asm/emif.h>
	25	#include <asm/gpio.h>
	26	#include <i2c.h>
	27	#include <miiphy.h>
	28	#include <cpsw.h>
	29	#include "board.h"
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	static struct wd_timer wdtimer = (struct wd_timer )WDT_BASE;
e363426e PK	34
	35	/* MII mode defines */
	36	#define MII_MODE_ENABLE 0x0
cfd4ff6f	37	#define RGMII_MODE_ENABLE 0x3A
e363426e PK	38
	39	/* GPIO that controls power to DDR on EVM-SK */
	40	#define GPIO_DDR_VTT_EN 7
	41
	42	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	43
e363426e PK	44	/*
	45	* Read header information from EEPROM into global structure.
	46	*/
ace4275e	47	static int read_eeprom(struct am335x_baseboard_id *header)
e363426e PK	48	{
	49	/* Check if baseboard eeprom is available */
	50	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	51	puts("Could not probe the EEPROM; something fundamentally "
	52	"wrong on the I2C bus.\n");
	53	return -ENODEV;
	54	}
	55
	56	/* read the eeprom using i2c */
ace4275e TR	57	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
ace4275e TR	58	sizeof(struct am335x_baseboard_id))) {
e363426e PK	59	puts("Could not read the EEPROM; something fundamentally"
	60	" wrong on the I2C bus.\n");
	61	return -EIO;
	62	}
	63
ace4275e	64	if (header->magic != 0xEE3355AA) {
e363426e PK	65	/*
	66	* read the eeprom using i2c again,
	67	* but use only a 1 byte address
	68	*/
ace4275e TR	69	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
ace4275e TR	70	sizeof(struct am335x_baseboard_id))) {
e363426e PK	71	puts("Could not read the EEPROM; something "
	72	"fundamentally wrong on the I2C bus.\n");
	73	return -EIO;
	74	}
	75
ace4275e	76	if (header->magic != 0xEE3355AA) {
e363426e	77	printf("Incorrect magic number (0x%x) in EEPROM\n",
ace4275e	78	header->magic);
e363426e PK	79	return -EINVAL;
	80	}
	81	}
	82
	83	return 0;
	84	}
	85
c5c7a7c3	86	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_NOR_BOOT)
c00f69db	87	static const struct ddr_data ddr2_data = {
c7d35bef PK	88	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) \|
	89	(MT47H128M16RT25E_RD_DQS<<20) \|
	90	(MT47H128M16RT25E_RD_DQS<<10) \|
	91	(MT47H128M16RT25E_RD_DQS<<0)),
	92	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) \|
	93	(MT47H128M16RT25E_WR_DQS<<20) \|
	94	(MT47H128M16RT25E_WR_DQS<<10) \|
	95	(MT47H128M16RT25E_WR_DQS<<0)),
	96	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) \|
	97	(MT47H128M16RT25E_PHY_WRLVL<<20) \|
	98	(MT47H128M16RT25E_PHY_WRLVL<<10) \|
	99	(MT47H128M16RT25E_PHY_WRLVL<<0)),
	100	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) \|
	101	(MT47H128M16RT25E_PHY_GATELVL<<20) \|
	102	(MT47H128M16RT25E_PHY_GATELVL<<10) \|
	103	(MT47H128M16RT25E_PHY_GATELVL<<0)),
	104	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) \|
	105	(MT47H128M16RT25E_PHY_FIFO_WE<<20) \|
	106	(MT47H128M16RT25E_PHY_FIFO_WE<<10) \|
	107	(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	108	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) \|
	109	(MT47H128M16RT25E_PHY_WR_DATA<<20) \|
	110	(MT47H128M16RT25E_PHY_WR_DATA<<10) \|
	111	(MT47H128M16RT25E_PHY_WR_DATA<<0)),
	112	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
c00f69db PK	113	.datadldiff0 = PHY_DLL_LOCK_DIFF,
c00f69db PK	114	};
e363426e	115
c00f69db	116	static const struct cmd_control ddr2_cmd_ctrl_data = {
c7d35bef PK	117	.cmd0csratio = MT47H128M16RT25E_RATIO,
	118	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	119	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	120
c7d35bef PK	121	.cmd1csratio = MT47H128M16RT25E_RATIO,
	122	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	123	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	124
c7d35bef PK	125	.cmd2csratio = MT47H128M16RT25E_RATIO,
	126	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	127	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db PK	128	};
	129
	130	static const struct emif_regs ddr2_emif_reg_data = {
c7d35bef PK	131	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	132	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	133	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	134	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	135	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	136	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
c00f69db PK	137	};
	138
	139	static const struct ddr_data ddr3_data = {
c7d35bef PK	140	.datardsratio0 = MT41J128MJT125_RD_DQS,
	141	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	142	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	143	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
c00f69db PK	144	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	145	};
	146
c7ba18ad TR	147	static const struct ddr_data ddr3_beagleblack_data = {
	148	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	149	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	150	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	151	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	152	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	153	};
	154
13526f71 JL	155	static const struct ddr_data ddr3_evm_data = {
	156	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	157	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	158	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	159	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
	160	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	161	};
	162
c00f69db	163	static const struct cmd_control ddr3_cmd_ctrl_data = {
c7d35bef PK	164	.cmd0csratio = MT41J128MJT125_RATIO,
	165	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	166	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	167
c7d35bef PK	168	.cmd1csratio = MT41J128MJT125_RATIO,
	169	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	170	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	171
c7d35bef PK	172	.cmd2csratio = MT41J128MJT125_RATIO,
	173	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	174	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db PK	175	};
c00f69db PK	176
c7ba18ad TR	177	static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
	178	.cmd0csratio = MT41K256M16HA125E_RATIO,
	179	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	180	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	181
	182	.cmd1csratio = MT41K256M16HA125E_RATIO,
	183	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	184	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	185
	186	.cmd2csratio = MT41K256M16HA125E_RATIO,
	187	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	188	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	189	};
	190
13526f71 JL	191	static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	192	.cmd0csratio = MT41J512M8RH125_RATIO,
	193	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	194	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	195
	196	.cmd1csratio = MT41J512M8RH125_RATIO,
	197	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	198	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	199
	200	.cmd2csratio = MT41J512M8RH125_RATIO,
	201	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	202	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	203	};
	204
c00f69db	205	static struct emif_regs ddr3_emif_reg_data = {
c7d35bef PK	206	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	207	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	208	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	209	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	210	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	211	.zq_config = MT41J128MJT125_ZQ_CFG,
59dcf970 VH	212	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY \|
59dcf970 VH	213	PHY_EN_DYN_PWRDN,
c00f69db	214	};
13526f71	215
c7ba18ad TR	216	static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	217	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	218	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	219	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	220	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	221	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	222	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	223	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	224	};
	225
13526f71 JL	226	static struct emif_regs ddr3_evm_emif_reg_data = {
	227	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	228	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	229	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	230	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	231	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	232	.zq_config = MT41J512M8RH125_ZQ_CFG,
59dcf970 VH	233	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY \|
59dcf970 VH	234	PHY_EN_DYN_PWRDN,
13526f71	235	};
12d7a474 PK	236
	237	#ifdef CONFIG_SPL_OS_BOOT
	238	int spl_start_uboot(void)
	239	{
	240	/* break into full u-boot on 'c' */
	241	return (serial_tstc() && serial_getc() == 'c');
	242	}
	243	#endif
	244
94d77fb6 LV	245	#define OSC (V_OSCK/1000000)
	246	const struct dpll_params dpll_ddr = {
	247	266, OSC-1, 1, -1, -1, -1, -1};
	248	const struct dpll_params dpll_ddr_evm_sk = {
	249	303, OSC-1, 1, -1, -1, -1, -1};
	250	const struct dpll_params dpll_ddr_bone_black = {
	251	400, OSC-1, 1, -1, -1, -1, -1};
	252
	253	const struct dpll_params *get_dpll_ddr_params(void)
	254	{
	255	struct am335x_baseboard_id header;
	256
	257	enable_i2c0_pin_mux();
	258	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	259	if (read_eeprom(&header) < 0)
	260	puts("Could not get board ID.\n");
	261
	262	if (board_is_evm_sk(&header))
	263	return &dpll_ddr_evm_sk;
	264	else if (board_is_bone_lt(&header))
	265	return &dpll_ddr_bone_black;
	266	else if (board_is_evm_15_or_later(&header))
	267	return &dpll_ddr_evm_sk;
	268	else
	269	return &dpll_ddr;
	270	}
	271
c00f69db	272	#endif
e363426e PK	273
	274	/*
	275	* early system init of muxing and clocks.
	276	*/
	277	void s_init(void)
	278	{
c5c7a7c3	279	__maybe_unused struct am335x_baseboard_id header;
ace4275e	280
c5c7a7c3 SK	281	/*
	282	* The ROM will only have set up sufficient pinmux to allow for the
	283	* first 4KiB NOR to be read, we must finish doing what we know of
	284	* the NOR mux in this space in order to continue.
	285	*/
	286	#ifdef CONFIG_NOR_BOOT
	287	asm("stmfd sp!, {r2 - r4}");
	288	asm("movw r4, #0x8A4");
	289	asm("movw r3, #0x44E1");
	290	asm("orr r4, r4, r3, lsl #16");
	291	asm("mov r2, #9");
	292	asm("mov r3, #8");
	293	asm("gpmc_mux: str r2, [r4], #4");
	294	asm("subs r3, r3, #1");
	295	asm("bne gpmc_mux");
	296	asm("ldmfd sp!, {r2 - r4}");
	297	#endif
	298
	299	#ifdef CONFIG_SPL_BUILD
4596dcc1 TR	300	/*
	301	* Save the boot parameters passed from romcode.
	302	* We cannot delay the saving further than this,
	303	* to prevent overwrites.
	304	*/
4596dcc1 TR	305	save_omap_boot_params();
	306	#endif
	307
e363426e PK	308	/* WDT1 is already running when the bootloader gets control
	309	* Disable it to avoid "random" resets
	310	*/
	311	writel(0xAAAA, &wdtimer->wdtwspr);
	312	while (readl(&wdtimer->wdtwwps) != 0x0)
	313	;
	314	writel(0x5555, &wdtimer->wdtwspr);
	315	while (readl(&wdtimer->wdtwwps) != 0x0)
	316	;
	317
c5c7a7c3	318	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_NOR_BOOT)
e363426e	319	/* Setup the PLLs and the clocks for the peripherals */
95cb69fa	320	setup_clocks_for_console();
e363426e	321
6422b70b	322	#ifdef CONFIG_SERIAL1
e363426e	323	enable_uart0_pin_mux();
6422b70b AB	324	#endif /* CONFIG_SERIAL1 */
	325	#ifdef CONFIG_SERIAL2
	326	enable_uart1_pin_mux();
	327	#endif /* CONFIG_SERIAL2 */
	328	#ifdef CONFIG_SERIAL3
	329	enable_uart2_pin_mux();
	330	#endif /* CONFIG_SERIAL3 */
	331	#ifdef CONFIG_SERIAL4
	332	enable_uart3_pin_mux();
	333	#endif /* CONFIG_SERIAL4 */
	334	#ifdef CONFIG_SERIAL5
	335	enable_uart4_pin_mux();
	336	#endif /* CONFIG_SERIAL5 */
	337	#ifdef CONFIG_SERIAL6
	338	enable_uart5_pin_mux();
	339	#endif /* CONFIG_SERIAL6 */
e363426e	340
7ea7f689	341	uart_soft_reset();
e363426e	342
c5c7a7c3 SK	343	#if defined(CONFIG_NOR_BOOT)
	344	/* We want our console now. */
	345	gd->baudrate = CONFIG_BAUDRATE;
	346	serial_init();
	347	gd->have_console = 1;
	348	#else
e363426e PK	349	gd = &gdata;
	350
	351	preloader_console_init();
c5c7a7c3	352	#endif
e363426e	353
95cb69fa LV	354	prcm_init();
95cb69fa LV	355
ace4275e	356	if (read_eeprom(&header) < 0)
e363426e PK	357	puts("Could not get board ID.\n");
e363426e PK	358
95cb69fa LV	359	/* Enable RTC32K clock */
	360	rtc32k_enable();
	361
e363426e	362	enable_board_pin_mux(&header);
ace4275e	363	if (board_is_evm_sk(&header)) {
e363426e PK	364	/*
	365	* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
	366	* This is safe enough to do on older revs.
	367	*/
	368	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	369	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	370	}
	371
ace4275e	372	if (board_is_evm_sk(&header))
c7d35bef	373	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
3ba65f97	374	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
ace4275e	375	else if (board_is_bone_lt(&header))
b996a3e9	376	config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
c7ba18ad TR	377	&ddr3_beagleblack_data,
	378	&ddr3_beagleblack_cmd_ctrl_data,
	379	&ddr3_beagleblack_emif_reg_data, 0);
ace4275e	380	else if (board_is_evm_15_or_later(&header))
13526f71	381	config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
3ba65f97	382	&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
c00f69db	383	else
c7d35bef	384	config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
3ba65f97	385	&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
e363426e PK	386	#endif
	387	}
	388
	389	/*
	390	* Basic board specific setup. Pinmux has been handled already.
	391	*/
	392	int board_init(void)
	393	{
cd8845d7 SK	394	#ifdef CONFIG_NOR
	395	const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
	396	STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
	397	STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
	398	#endif
	399
e363426e PK	400	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
e363426e PK	401
98b5c269 IY	402	gpmc_init();
98b5c269 IY	403
cd8845d7 SK	404	#ifdef CONFIG_NOR
	405	/* Reconfigure CS0 for NOR instead of NAND. */
	406	enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
	407	CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
	408	#endif
	409
e363426e PK	410	return 0;
	411	}
	412
044fc14b TR	413	#ifdef CONFIG_BOARD_LATE_INIT
	414	int board_late_init(void)
	415	{
	416	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	417	char safe_string[HDR_NAME_LEN + 1];
ace4275e TR	418	struct am335x_baseboard_id header;
	419
	420	if (read_eeprom(&header) < 0)
	421	puts("Could not get board ID.\n");
044fc14b TR	422
	423	/* Now set variables based on the header. */
	424	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	425	safe_string[sizeof(header.name)] = 0;
	426	setenv("board_name", safe_string);
	427
	428	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	429	safe_string[sizeof(header.version)] = 0;
	430	setenv("board_rev", safe_string);
	431	#endif
	432
	433	return 0;
	434	}
	435	#endif
	436
c0e66793 IY	437	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
c0e66793 IY	438	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e PK	439	static void cpsw_control(int enabled)
	440	{
	441	/* VTP can be added here */
	442
	443	return;
	444	}
	445
	446	static struct cpsw_slave_data cpsw_slaves[] = {
	447	{
	448	.slave_reg_ofs = 0x208,
	449	.sliver_reg_ofs = 0xd80,
	450	.phy_id = 0,
	451	},
	452	{
	453	.slave_reg_ofs = 0x308,
	454	.sliver_reg_ofs = 0xdc0,
	455	.phy_id = 1,
	456	},
	457	};
	458
	459	static struct cpsw_platform_data cpsw_data = {
81df2bab MP	460	.mdio_base = CPSW_MDIO_BASE,
81df2bab MP	461	.cpsw_base = CPSW_BASE,
e363426e PK	462	.mdio_div = 0xff,
	463	.channels = 8,
	464	.cpdma_reg_ofs = 0x800,
	465	.slaves = 1,
	466	.slave_data = cpsw_slaves,
	467	.ale_reg_ofs = 0xd00,
	468	.ale_entries = 1024,
	469	.host_port_reg_ofs = 0x108,
	470	.hw_stats_reg_ofs = 0x900,
2bf36ac6	471	.bd_ram_ofs = 0x2000,
e363426e PK	472	.mac_control = (1 << 5),
	473	.control = cpsw_control,
	474	.host_port_num = 0,
	475	.version = CPSW_CTRL_VERSION_2,
	476	};
d2aa1154	477	#endif
e363426e	478
d2aa1154 IY	479	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
d2aa1154 IY	480	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
e363426e PK	481	int board_eth_init(bd_t *bis)
e363426e PK	482	{
d2aa1154	483	int rv, n = 0;
e363426e PK	484	uint8_t mac_addr[6];
e363426e PK	485	uint32_t mac_hi, mac_lo;
ace4275e	486	__maybe_unused struct am335x_baseboard_id header;
e363426e	487
c0e66793 IY	488	/* try reading mac address from efuse */
	489	mac_lo = readl(&cdev->macid0l);
	490	mac_hi = readl(&cdev->macid0h);
	491	mac_addr[0] = mac_hi & 0xFF;
	492	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	493	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	494	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	495	mac_addr[4] = mac_lo & 0xFF;
	496	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
	497
	498	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	499	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	500	if (!getenv("ethaddr")) {
	501	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
e363426e PK	502
	503	if (is_valid_ether_addr(mac_addr))
	504	eth_setenv_enetaddr("ethaddr", mac_addr);
e363426e PK	505	}
e363426e PK	506
a662e0c3	507	#ifdef CONFIG_DRIVER_TI_CPSW
ace4275e TR	508	if (read_eeprom(&header) < 0)
	509	puts("Could not get board ID.\n");
	510
	511	if (board_is_bone(&header) \|\| board_is_bone_lt(&header) \|\|
	512	board_is_idk(&header)) {
e363426e PK	513	writel(MII_MODE_ENABLE, &cdev->miisel);
	514	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	515	PHY_INTERFACE_MODE_MII;
	516	} else {
	517	writel(RGMII_MODE_ENABLE, &cdev->miisel);
	518	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	519	PHY_INTERFACE_MODE_RGMII;
	520	}
	521
d2aa1154 IY	522	rv = cpsw_register(&cpsw_data);
	523	if (rv < 0)
	524	printf("Error %d registering CPSW switch\n", rv);
	525	else
	526	n += rv;
a662e0c3	527	#endif
1634e969 TR	528
	529	/*
	530	*
	531	* CPSW RGMII Internal Delay Mode is not supported in all PVT
	532	* operating points. So we must set the TX clock delay feature
	533	* in the AR8051 PHY. Since we only support a single ethernet
	534	* device in U-Boot, we only do this for the first instance.
	535	*/
	536	#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
	537	#define AR8051_PHY_DEBUG_DATA_REG 0x1e
	538	#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
	539	#define AR8051_RGMII_TX_CLK_DLY 0x100
	540
ace4275e	541	if (board_is_evm_sk(&header) \|\| board_is_gp_evm(&header)) {
1634e969 TR	542	const char *devname;
	543	devname = miiphy_get_current_dev();
	544
	545	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
	546	AR8051_DEBUG_RGMII_CLK_DLY_REG);
	547	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
	548	AR8051_RGMII_TX_CLK_DLY);
	549	}
d2aa1154	550	#endif
c0e66793 IY	551	#if defined(CONFIG_USB_ETHER) && \
	552	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_USBETH_SUPPORT))
	553	if (is_valid_ether_addr(mac_addr))
	554	eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
	555
d2aa1154 IY	556	rv = usb_eth_initialize(bis);
	557	if (rv < 0)
	558	printf("Error %d registering USB_ETHER\n", rv);
	559	else
	560	n += rv;
	561	#endif
	562	return n;
e363426e PK	563	}
e363426e PK	564	#endif