[people/ms/u-boot.git] / board / ti / ks2_evm / board_k2g.c

/*
 * K2G EVM : Board initialization
 *
 * (C) Copyright 2015
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include <fdtdec.h>
#include <i2c.h>
#include "mux-k2g.h"
#include "../common/board_detect.h"

#define K2G_GP_AUDIO_CODEC_ADDRESS	0x1B

const unsigned int sysclk_array[MAX_SYSCLK] = {
	19200000,
	24000000,
	25000000,
	26000000,
};

unsigned int get_external_clk(u32 clk)
{
	unsigned int clk_freq;
	u8 sysclk_index = get_sysclk_index();

	switch (clk) {
	case sys_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case pa_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case tetris_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case ddr3a_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case uart_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	default:
		clk_freq = 0;
		break;
	}

	return clk_freq;
}

static int arm_speeds[DEVSPEED_NUMSPDS] = {
	SPD400,
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
	SPD200,
};

static int dev_speeds[DEVSPEED_NUMSPDS] = {
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
};

static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	[SYSCLK_19MHz] = {
		[SPD400]	= {MAIN_PLL, 125, 3, 2},
		[SPD600]	= {MAIN_PLL, 125, 2, 2},
		[SPD800]	= {MAIN_PLL, 250, 3, 2},
		[SPD900]	= {MAIN_PLL, 187, 2, 2},
		[SPD1000]	= {MAIN_PLL, 104, 1, 2},
	},
	[SYSCLK_24MHz] = {
		[SPD400]	= {MAIN_PLL, 100, 3, 2},
		[SPD600]	= {MAIN_PLL, 300, 6, 2},
		[SPD800]	= {MAIN_PLL, 200, 3, 2},
		[SPD900]	= {MAIN_PLL, 75, 1, 2},
		[SPD1000]	= {MAIN_PLL, 250, 3, 2},
	},
	[SYSCLK_25MHz] = {
		[SPD400]	= {MAIN_PLL, 32, 1, 2},
		[SPD600]	= {MAIN_PLL, 48, 1, 2},
		[SPD800]	= {MAIN_PLL, 64, 1, 2},
		[SPD900]	= {MAIN_PLL, 72, 1, 2},
		[SPD1000]	= {MAIN_PLL, 80, 1, 2},
	},
	[SYSCLK_26MHz] = {
		[SPD400]	= {MAIN_PLL, 400, 13, 2},
		[SPD600]	= {MAIN_PLL, 230, 5, 2},
		[SPD800]	= {MAIN_PLL, 123, 2, 2},
		[SPD900]	= {MAIN_PLL, 69, 1, 2},
		[SPD1000]	= {MAIN_PLL, 384, 5, 2},
	},
};

static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	[SYSCLK_19MHz] = {
		[SPD200]	= {TETRIS_PLL, 625, 6, 10},
		[SPD400]	= {TETRIS_PLL, 125, 1, 6},
		[SPD600]	= {TETRIS_PLL, 125, 1, 4},
		[SPD800]	= {TETRIS_PLL, 333, 2, 4},
		[SPD900]	= {TETRIS_PLL, 187, 2, 2},
		[SPD1000]	= {TETRIS_PLL, 104, 1, 2},
	},
	[SYSCLK_24MHz] = {
		[SPD200]	= {TETRIS_PLL, 250, 3, 10},
		[SPD400]	= {TETRIS_PLL, 100, 1, 6},
		[SPD600]	= {TETRIS_PLL, 100, 1, 4},
		[SPD800]	= {TETRIS_PLL, 400, 3, 4},
		[SPD900]	= {TETRIS_PLL, 75, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 250, 3, 2},
	},
	[SYSCLK_25MHz] = {
		[SPD200]	= {TETRIS_PLL, 80, 1, 10},
		[SPD400]	= {TETRIS_PLL, 96, 1, 6},
		[SPD600]	= {TETRIS_PLL, 96, 1, 4},
		[SPD800]	= {TETRIS_PLL, 128, 1, 4},
		[SPD900]	= {TETRIS_PLL, 72, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 80, 1, 2},
	},
	[SYSCLK_26MHz] = {
		[SPD200]	= {TETRIS_PLL, 307, 4, 10},
		[SPD400]	= {TETRIS_PLL, 369, 4, 6},
		[SPD600]	= {TETRIS_PLL, 369, 4, 4},
		[SPD800]	= {TETRIS_PLL, 123, 1, 4},
		[SPD900]	= {TETRIS_PLL, 69, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 384, 5, 2},
	},
};

static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
};

static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
};

static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
};

struct pll_init_data *get_pll_init_data(int pll)
{
	int speed;
	struct pll_init_data *data = NULL;
	u8 sysclk_index = get_sysclk_index();

	switch (pll) {
	case MAIN_PLL:
		speed = get_max_dev_speed(dev_speeds);
		data = &main_pll_config[sysclk_index][speed];
		break;
	case TETRIS_PLL:
		speed = get_max_arm_speed(arm_speeds);
		data = &tetris_pll_config[sysclk_index][speed];
		break;
	case NSS_PLL:
		data = &nss_pll_config[sysclk_index];
		break;
	case UART_PLL:
		data = &uart_pll_config[sysclk_index];
		break;
	case DDR3_PLL:
		data = &ddr3_pll_config[sysclk_index];
		break;
	default:
		data = NULL;
	}

	return data;
}

s16 divn_val[16] = {
	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
	if (psc_enable_module(KS2_LPSC_MMC)) {
		printf("%s module enabled failed\n", __func__);
		return -1;
	}

	if (board_is_k2g_gp())
		omap_mmc_init(0, 0, 0, -1, -1);

	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#if defined(CONFIG_FIT_EMBED)
int board_fit_config_name_match(const char *name)
{
	bool eeprom_read = board_ti_was_eeprom_read();

	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
		return 0;
	else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
		return 0;
	else
		return -1;
}
#endif

#if defined(CONFIG_DTB_RESELECT)
static int k2g_alt_board_detect(void)
{
	int rc;

	rc = i2c_set_bus_num(1);
	if (rc)
		return rc;

	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
	if (rc)
		return rc;

	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");

	return 0;
}

static void k2g_reset_mux_config(void)
{
	/* Unlock the reset mux register */
	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);

	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);

	/* lock the reset mux register to prevent any spurious writes. */
	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
}

int embedded_dtb_select(void)
{
	int rc;
	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc) {
		rc = k2g_alt_board_detect();
		if (rc) {
			printf("Unable to do board detection\n");
			return -1;
		}
	}

	fdtdec_setup();

	k2g_mux_config();

	k2g_reset_mux_config();

	if (board_is_k2g_gp()) {
		/* deassert FLASH_HOLD */
		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
			     BIT(9));
		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
			     BIT(9));
	}

	return 0;
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
	int rc;

	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc)
		printf("ti_i2c_eeprom_init failed %d\n", rc);

	board_ti_set_ethaddr(1);
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (board_is_k2g_gp())
		setenv("board_name", "66AK2GGP\0");
	else if (board_is_k2g_ice())
		setenv("board_name", "66AK2GIC\0");
#endif
	return 0;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif

#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
	{
		.int_name	= "K2G_EMAC",
		.rx_flow	= 0,
		.phy_addr	= 0,
		.slave_port	= 1,
		.sgmii_link_type = SGMII_LINK_MAC_PHY,
		.phy_if          = PHY_INTERFACE_MODE_RGMII,
	},
};

int get_num_eth_ports(void)
{
	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
Commit	Line	Data
bda920c6 VA	1	/*
	2	* K2G EVM : Board initialization
	3	*
	4	* (C) Copyright 2015
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <asm/arch/clock.h>
91266ccb	11	#include <asm/ti-common/keystone_net.h>
3b68939f RQ	12	#include <asm/arch/psc_defs.h>
3b68939f RQ	13	#include <asm/arch/mmc_host_def.h>
5f48da9a CJF	14	#include <fdtdec.h>
5f48da9a CJF	15	#include <i2c.h>
dd78b8cf	16	#include "mux-k2g.h"
752a8311	17	#include "../common/board_detect.h"
bda920c6	18
5f48da9a CJF	19	#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
5f48da9a CJF	20
c5f177de LV	21	const unsigned int sysclk_array[MAX_SYSCLK] = {
	22	19200000,
	23	24000000,
	24	25000000,
	25	26000000,
	26	};
	27
ee3c6532 LV	28	unsigned int get_external_clk(u32 clk)
	29	{
	30	unsigned int clk_freq;
	31	u8 sysclk_index = get_sysclk_index();
	32
	33	switch (clk) {
	34	case sys_clk:
	35	clk_freq = sysclk_array[sysclk_index];
	36	break;
	37	case pa_clk:
	38	clk_freq = sysclk_array[sysclk_index];
	39	break;
	40	case tetris_clk:
	41	clk_freq = sysclk_array[sysclk_index];
	42	break;
	43	case ddr3a_clk:
	44	clk_freq = sysclk_array[sysclk_index];
	45	break;
	46	case uart_clk:
	47	clk_freq = sysclk_array[sysclk_index];
	48	break;
	49	default:
	50	clk_freq = 0;
	51	break;
	52	}
	53
	54	return clk_freq;
	55	}
e6d71e1c	56
ef76ebb1 LV	57	static int arm_speeds[DEVSPEED_NUMSPDS] = {
	58	SPD400,
	59	SPD600,
	60	SPD800,
	61	SPD900,
	62	SPD1000,
	63	SPD900,
	64	SPD800,
	65	SPD600,
	66	SPD400,
	67	SPD200,
	68	};
	69
	70	static int dev_speeds[DEVSPEED_NUMSPDS] = {
	71	SPD600,
	72	SPD800,
	73	SPD900,
	74	SPD1000,
	75	SPD900,
	76	SPD800,
	77	SPD600,
	78	SPD400,
	79	};
	80
c5f177de LV	81	static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	82	[SYSCLK_19MHz] = {
	83	[SPD400] = {MAIN_PLL, 125, 3, 2},
	84	[SPD600] = {MAIN_PLL, 125, 2, 2},
	85	[SPD800] = {MAIN_PLL, 250, 3, 2},
9cb5eaf2 LV	86	[SPD900] = {MAIN_PLL, 187, 2, 2},
9cb5eaf2 LV	87	[SPD1000] = {MAIN_PLL, 104, 1, 2},
c5f177de LV	88	},
	89	[SYSCLK_24MHz] = {
	90	[SPD400] = {MAIN_PLL, 100, 3, 2},
	91	[SPD600] = {MAIN_PLL, 300, 6, 2},
	92	[SPD800] = {MAIN_PLL, 200, 3, 2},
9cb5eaf2 LV	93	[SPD900] = {MAIN_PLL, 75, 1, 2},
9cb5eaf2 LV	94	[SPD1000] = {MAIN_PLL, 250, 3, 2},
c5f177de LV	95	},
	96	[SYSCLK_25MHz] = {
	97	[SPD400] = {MAIN_PLL, 32, 1, 2},
	98	[SPD600] = {MAIN_PLL, 48, 1, 2},
	99	[SPD800] = {MAIN_PLL, 64, 1, 2},
9cb5eaf2 LV	100	[SPD900] = {MAIN_PLL, 72, 1, 2},
9cb5eaf2 LV	101	[SPD1000] = {MAIN_PLL, 80, 1, 2},
c5f177de LV	102	},
	103	[SYSCLK_26MHz] = {
	104	[SPD400] = {MAIN_PLL, 400, 13, 2},
	105	[SPD600] = {MAIN_PLL, 230, 5, 2},
	106	[SPD800] = {MAIN_PLL, 123, 2, 2},
9cb5eaf2 LV	107	[SPD900] = {MAIN_PLL, 69, 1, 2},
9cb5eaf2 LV	108	[SPD1000] = {MAIN_PLL, 384, 5, 2},
c5f177de LV	109	},
	110	};
	111
	112	static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	113	[SYSCLK_19MHz] = {
	114	[SPD200] = {TETRIS_PLL, 625, 6, 10},
	115	[SPD400] = {TETRIS_PLL, 125, 1, 6},
	116	[SPD600] = {TETRIS_PLL, 125, 1, 4},
	117	[SPD800] = {TETRIS_PLL, 333, 2, 4},
	118	[SPD900] = {TETRIS_PLL, 187, 2, 2},
	119	[SPD1000] = {TETRIS_PLL, 104, 1, 2},
	120	},
	121	[SYSCLK_24MHz] = {
	122	[SPD200] = {TETRIS_PLL, 250, 3, 10},
	123	[SPD400] = {TETRIS_PLL, 100, 1, 6},
	124	[SPD600] = {TETRIS_PLL, 100, 1, 4},
	125	[SPD800] = {TETRIS_PLL, 400, 3, 4},
	126	[SPD900] = {TETRIS_PLL, 75, 1, 2},
	127	[SPD1000] = {TETRIS_PLL, 250, 3, 2},
	128	},
	129	[SYSCLK_25MHz] = {
	130	[SPD200] = {TETRIS_PLL, 80, 1, 10},
	131	[SPD400] = {TETRIS_PLL, 96, 1, 6},
	132	[SPD600] = {TETRIS_PLL, 96, 1, 4},
	133	[SPD800] = {TETRIS_PLL, 128, 1, 4},
	134	[SPD900] = {TETRIS_PLL, 72, 1, 2},
	135	[SPD1000] = {TETRIS_PLL, 80, 1, 2},
	136	},
	137	[SYSCLK_26MHz] = {
	138	[SPD200] = {TETRIS_PLL, 307, 4, 10},
	139	[SPD400] = {TETRIS_PLL, 369, 4, 6},
	140	[SPD600] = {TETRIS_PLL, 369, 4, 4},
	141	[SPD800] = {TETRIS_PLL, 123, 1, 4},
	142	[SPD900] = {TETRIS_PLL, 69, 1, 2},
	143	[SPD1000] = {TETRIS_PLL, 384, 5, 2},
	144	},
ef76ebb1 LV	145	};
ef76ebb1 LV	146
c5f177de LV	147	static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
	148	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
	149	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
	150	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
	151	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
ef76ebb1 LV	152	};
ef76ebb1 LV	153
c5f177de LV	154	static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
	155	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
	156	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
	157	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
	158	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
	159	};
	160
	161	static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
	162	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
	163	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
	164	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
	165	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
	166	};
bda920c6 VA	167
	168	struct pll_init_data *get_pll_init_data(int pll)
	169	{
ef76ebb1	170	int speed;
bda920c6	171	struct pll_init_data *data = NULL;
c5f177de	172	u8 sysclk_index = get_sysclk_index();
bda920c6 VA	173
	174	switch (pll) {
	175	case MAIN_PLL:
ef76ebb1	176	speed = get_max_dev_speed(dev_speeds);
c5f177de	177	data = &main_pll_config[sysclk_index][speed];
bda920c6 VA	178	break;
bda920c6 VA	179	case TETRIS_PLL:
ef76ebb1	180	speed = get_max_arm_speed(arm_speeds);
c5f177de	181	data = &tetris_pll_config[sysclk_index][speed];
bda920c6 VA	182	break;
bda920c6 VA	183	case NSS_PLL:
c5f177de	184	data = &nss_pll_config[sysclk_index];
bda920c6 VA	185	break;
bda920c6 VA	186	case UART_PLL:
c5f177de	187	data = &uart_pll_config[sysclk_index];
bda920c6 VA	188	break;
bda920c6 VA	189	case DDR3_PLL:
c5f177de	190	data = &ddr3_pll_config[sysclk_index];
bda920c6 VA	191	break;
	192	default:
	193	data = NULL;
	194	}
	195
	196	return data;
	197	}
	198
	199	s16 divn_val[16] = {
	200	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	201	};
	202
4aa2ba3a	203	#if defined(CONFIG_MMC)
3b68939f RQ	204	int board_mmc_init(bd_t *bis)
	205	{
	206	if (psc_enable_module(KS2_LPSC_MMC)) {
	207	printf("%s module enabled failed\n", __func__);
	208	return -1;
	209	}
	210
4f490402 CJF	211	if (board_is_k2g_gp())
	212	omap_mmc_init(0, 0, 0, -1, -1);
	213
3b68939f RQ	214	omap_mmc_init(1, 0, 0, -1, -1);
	215	return 0;
	216	}
	217	#endif
	218
7234f215 CJF	219	#if defined(CONFIG_FIT_EMBED)
	220	int board_fit_config_name_match(const char *name)
	221	{
	222	bool eeprom_read = board_ti_was_eeprom_read();
	223
	224	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
	225	return 0;
	226	else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
	227	return 0;
	228	else
	229	return -1;
	230	}
	231	#endif
	232
5f48da9a CJF	233	#if defined(CONFIG_DTB_RESELECT)
	234	static int k2g_alt_board_detect(void)
	235	{
	236	int rc;
	237
	238	rc = i2c_set_bus_num(1);
	239	if (rc)
	240	return rc;
	241
	242	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
	243	if (rc)
	244	return rc;
	245
	246	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
	247
	248	return 0;
	249	}
	250
e2924e59 LV	251	static void k2g_reset_mux_config(void)
	252	{
	253	/* Unlock the reset mux register */
	254	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
	255
	256	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
	257	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
	258	RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
	259
	260	/* lock the reset mux register to prevent any spurious writes. */
	261	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
	262	}
	263
e820f523	264	int embedded_dtb_select(void)
bda920c6	265	{
e820f523 CJF	266	int rc;
	267	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
	268	CONFIG_EEPROM_CHIP_ADDRESS);
	269	if (rc) {
	270	rc = k2g_alt_board_detect();
	271	if (rc) {
	272	printf("Unable to do board detection\n");
	273	return -1;
	274	}
	275	}
bda920c6	276
e820f523	277	fdtdec_setup();
dd78b8cf	278
b9b342ea CJF	279	k2g_mux_config();
b9b342ea CJF	280
e2924e59 LV	281	k2g_reset_mux_config();
e2924e59 LV	282
4f490402 CJF	283	if (board_is_k2g_gp()) {
	284	/* deassert FLASH_HOLD */
	285	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
	286	BIT(9));
	287	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
	288	BIT(9));
	289	}
83b9bf11	290
bda920c6 VA	291	return 0;
	292	}
	293	#endif
	294
752a8311 RQ	295	#ifdef CONFIG_BOARD_LATE_INIT
	296	int board_late_init(void)
	297	{
	298	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
	299	int rc;
	300
	301	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
	302	CONFIG_EEPROM_CHIP_ADDRESS);
	303	if (rc)
	304	printf("ti_i2c_eeprom_init failed %d\n", rc);
	305
	306	board_ti_set_ethaddr(1);
	307	#endif
	308
92761fcc CJF	309	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	310	if (board_is_k2g_gp())
	311	setenv("board_name", "66AK2GGP\0");
	312	else if (board_is_k2g_ice())
	313	setenv("board_name", "66AK2GIC\0");
	314	#endif
752a8311 RQ	315	return 0;
	316	}
	317	#endif
	318
e820f523 CJF	319	#ifdef CONFIG_BOARD_EARLY_INIT_F
	320	int board_early_init_f(void)
	321	{
	322	init_plls();
	323
	324	k2g_mux_config();
	325
	326	return 0;
	327	}
	328	#endif
	329
bda920c6 VA	330	#ifdef CONFIG_SPL_BUILD
	331	void spl_init_keystone_plls(void)
	332	{
	333	init_plls();
	334	}
	335	#endif
91266ccb VA	336
	337	#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
	338	struct eth_priv_t eth_priv_cfg[] = {
	339	{
	340	.int_name = "K2G_EMAC",
	341	.rx_flow = 0,
	342	.phy_addr = 0,
	343	.slave_port = 1,
	344	.sgmii_link_type = SGMII_LINK_MAC_PHY,
	345	.phy_if = PHY_INTERFACE_MODE_RGMII,
	346	},
	347	};
	348
	349	int get_num_eth_ports(void)
	350	{
	351	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
	352	}
	353	#endif