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CommitLineData
8bde7f77
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
8bde7f77
WD
6 */
7
8/*
9 * Boot support
10 */
11#include <common.h>
12#include <command.h>
d88af4da 13#include <linux/compiler.h>
8bde7f77 14
d87080b7 15DECLARE_GLOBAL_DATA_PTR;
8bde7f77 16
d88af4da
MF
17__maybe_unused
18static void print_num(const char *name, ulong value)
19{
20 printf("%-12s= 0x%08lX\n", name, value);
21}
8bde7f77 22
5f3dfadc 23__maybe_unused
d88af4da
MF
24static void print_eth(int idx)
25{
26 char name[10], *val;
27 if (idx)
28 sprintf(name, "eth%iaddr", idx);
29 else
30 strcpy(name, "ethaddr");
31 val = getenv(name);
32 if (!val)
33 val = "(not set)";
34 printf("%-12s= %s\n", name, val);
35}
de2dff6f 36
05c3e68f 37#ifndef CONFIG_DM_ETH
9fc6a06a
MS
38__maybe_unused
39static void print_eths(void)
40{
41 struct eth_device *dev;
42 int i = 0;
43
44 do {
45 dev = eth_get_dev_by_index(i);
46 if (dev) {
47 printf("eth%dname = %s\n", i, dev->name);
48 print_eth(i);
49 i++;
50 }
51 } while (dev);
52
53 printf("current eth = %s\n", eth_get_name());
54 printf("ip_addr = %s\n", getenv("ipaddr"));
55}
05c3e68f 56#endif
9fc6a06a 57
d88af4da 58__maybe_unused
47708457 59static void print_lnum(const char *name, unsigned long long value)
d88af4da
MF
60{
61 printf("%-12s= 0x%.8llX\n", name, value);
62}
63
64__maybe_unused
65static void print_mhz(const char *name, unsigned long hz)
66{
67 char buf[32];
68
69 printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
70}
8bde7f77 71
c99ea790 72#if defined(CONFIG_PPC)
e7939464
YS
73void __weak board_detail(void)
74{
75 /* Please define boot_detail() for your platform */
76}
8bde7f77 77
5902e8f7 78int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 79{
8bde7f77 80 bd_t *bd = gd->bd;
8bde7f77
WD
81
82#ifdef DEBUG
5902e8f7
ML
83 print_num("bd address", (ulong)bd);
84#endif
85 print_num("memstart", bd->bi_memstart);
86 print_lnum("memsize", bd->bi_memsize);
87 print_num("flashstart", bd->bi_flashstart);
88 print_num("flashsize", bd->bi_flashsize);
89 print_num("flashoffset", bd->bi_flashoffset);
90 print_num("sramstart", bd->bi_sramstart);
91 print_num("sramsize", bd->bi_sramsize);
92#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
58dac327 93 defined(CONFIG_MPC8260) || defined(CONFIG_E500)
5902e8f7
ML
94 print_num("immr_base", bd->bi_immr_base);
95#endif
96 print_num("bootflags", bd->bi_bootflags);
3fb85889 97#if defined(CONFIG_405EP) || \
5902e8f7
ML
98 defined(CONFIG_405GP) || \
99 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
100 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
101 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
102 defined(CONFIG_XILINX_405)
0c277ef9
TT
103 print_mhz("procfreq", bd->bi_procfreq);
104 print_mhz("plb_busfreq", bd->bi_plb_busfreq);
5902e8f7
ML
105#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
106 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
107 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
108 defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
0c277ef9 109 print_mhz("pci_busfreq", bd->bi_pci_busfreq);
8bde7f77 110#endif
3fb85889 111#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
9c4c5ae3 112#if defined(CONFIG_CPM2)
0c277ef9
TT
113 print_mhz("vco", bd->bi_vco);
114 print_mhz("sccfreq", bd->bi_sccfreq);
115 print_mhz("brgfreq", bd->bi_brgfreq);
8bde7f77 116#endif
0c277ef9 117 print_mhz("intfreq", bd->bi_intfreq);
9c4c5ae3 118#if defined(CONFIG_CPM2)
0c277ef9 119 print_mhz("cpmfreq", bd->bi_cpmfreq);
8bde7f77 120#endif
0c277ef9 121 print_mhz("busfreq", bd->bi_busfreq);
3fb85889 122#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
03f5c550 123
34e210f5
TT
124#ifdef CONFIG_ENABLE_36BIT_PHYS
125#ifdef CONFIG_PHYS_64BIT
126 puts("addressing = 36-bit\n");
127#else
128 puts("addressing = 32-bit\n");
129#endif
130#endif
131
de2dff6f 132 print_eth(0);
e2ffd59b 133#if defined(CONFIG_HAS_ETH1)
de2dff6f 134 print_eth(1);
03f5c550 135#endif
e2ffd59b 136#if defined(CONFIG_HAS_ETH2)
de2dff6f 137 print_eth(2);
42d1f039 138#endif
e2ffd59b 139#if defined(CONFIG_HAS_ETH3)
de2dff6f 140 print_eth(3);
03f5c550 141#endif
c68a05fe 142#if defined(CONFIG_HAS_ETH4)
de2dff6f 143 print_eth(4);
c68a05fe 144#endif
c68a05fe 145#if defined(CONFIG_HAS_ETH5)
de2dff6f 146 print_eth(5);
c68a05fe 147#endif
148
50a47d05 149 printf("IP addr = %s\n", getenv("ipaddr"));
8e261575 150 printf("baudrate = %6u bps\n", gd->baudrate);
5902e8f7 151 print_num("relocaddr", gd->relocaddr);
e7939464 152 board_detail();
8bde7f77
WD
153 return 0;
154}
155
c99ea790 156#elif defined(CONFIG_NIOS2)
5c952cf0 157
5902e8f7 158int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
5c952cf0 159{
744b57b8 160 int i;
5c952cf0
WD
161 bd_t *bd = gd->bd;
162
744b57b8
TC
163 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
164 print_num("DRAM bank", i);
165 print_num("-> start", bd->bi_dram[i].start);
166 print_num("-> size", bd->bi_dram[i].size);
167 }
168
5902e8f7
ML
169 print_num("flash start", (ulong)bd->bi_flashstart);
170 print_num("flash size", (ulong)bd->bi_flashsize);
171 print_num("flash offset", (ulong)bd->bi_flashoffset);
5c952cf0 172
6d0f6bcf 173#if defined(CONFIG_SYS_SRAM_BASE)
5c952cf0
WD
174 print_num ("sram start", (ulong)bd->bi_sramstart);
175 print_num ("sram size", (ulong)bd->bi_sramsize);
176#endif
177
90253178 178#if defined(CONFIG_CMD_NET)
de2dff6f 179 print_eth(0);
50a47d05 180 printf("ip_addr = %s\n", getenv("ipaddr"));
5c952cf0
WD
181#endif
182
8e261575 183 printf("baudrate = %u bps\n", gd->baudrate);
5c952cf0
WD
184
185 return 0;
186}
c99ea790
RM
187
188#elif defined(CONFIG_MICROBLAZE)
cfc67116 189
5902e8f7 190int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cfc67116 191{
cfc67116 192 bd_t *bd = gd->bd;
e945f6dc
MS
193 int i;
194
195 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
196 print_num("DRAM bank", i);
197 print_num("-> start", bd->bi_dram[i].start);
198 print_num("-> size", bd->bi_dram[i].size);
199 }
200
5902e8f7
ML
201 print_num("flash start ", (ulong)bd->bi_flashstart);
202 print_num("flash size ", (ulong)bd->bi_flashsize);
203 print_num("flash offset ", (ulong)bd->bi_flashoffset);
6d0f6bcf 204#if defined(CONFIG_SYS_SRAM_BASE)
5902e8f7
ML
205 print_num("sram start ", (ulong)bd->bi_sramstart);
206 print_num("sram size ", (ulong)bd->bi_sramsize);
cfc67116 207#endif
062f078c 208#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
9fc6a06a 209 print_eths();
cfc67116 210#endif
8e261575 211 printf("baudrate = %u bps\n", gd->baudrate);
e945f6dc
MS
212 print_num("relocaddr", gd->relocaddr);
213 print_num("reloc off", gd->reloc_off);
de86765b
MS
214 print_num("fdt_blob", (ulong)gd->fdt_blob);
215 print_num("new_fdt", (ulong)gd->new_fdt);
216 print_num("fdt_size", (ulong)gd->fdt_size);
e945f6dc 217
cfc67116
MS
218 return 0;
219}
4a551709 220
c99ea790
RM
221#elif defined(CONFIG_SPARC)
222
54841ab5 223int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
00ab32c8
DH
224{
225 bd_t *bd = gd->bd;
00ab32c8
DH
226
227#ifdef DEBUG
228 print_num("bd address ", (ulong) bd);
229#endif
230 print_num("memstart ", bd->bi_memstart);
b57ca3e1 231 print_lnum("memsize ", bd->bi_memsize);
00ab32c8 232 print_num("flashstart ", bd->bi_flashstart);
6d0f6bcf 233 print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
0e8d1586 234 print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
d97f01a6 235 printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
6d0f6bcf 236 CONFIG_SYS_MONITOR_LEN);
d97f01a6 237 printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
6d0f6bcf 238 CONFIG_SYS_MALLOC_LEN);
d97f01a6 239 printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
6d0f6bcf 240 CONFIG_SYS_STACK_SIZE);
d97f01a6 241 printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
6d0f6bcf 242 CONFIG_SYS_PROM_SIZE);
d97f01a6 243 printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
25ddd1fb 244 GENERATED_GBL_DATA_SIZE);
00ab32c8
DH
245
246#if defined(CONFIG_CMD_NET)
de2dff6f 247 print_eth(0);
50a47d05 248 printf("ip_addr = %s\n", getenv("ipaddr"));
00ab32c8 249#endif
8e261575 250 printf("baudrate = %6u bps\n", gd->baudrate);
00ab32c8
DH
251 return 0;
252}
253
c99ea790
RM
254#elif defined(CONFIG_M68K)
255
5902e8f7 256int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8e585f02 257{
8e585f02 258 bd_t *bd = gd->bd;
8ae158cd 259
5902e8f7
ML
260 print_num("memstart", (ulong)bd->bi_memstart);
261 print_lnum("memsize", (u64)bd->bi_memsize);
262 print_num("flashstart", (ulong)bd->bi_flashstart);
263 print_num("flashsize", (ulong)bd->bi_flashsize);
264 print_num("flashoffset", (ulong)bd->bi_flashoffset);
6d0f6bcf 265#if defined(CONFIG_SYS_INIT_RAM_ADDR)
5902e8f7
ML
266 print_num("sramstart", (ulong)bd->bi_sramstart);
267 print_num("sramsize", (ulong)bd->bi_sramsize);
8e585f02 268#endif
6d0f6bcf 269#if defined(CONFIG_SYS_MBAR)
5902e8f7 270 print_num("mbar", bd->bi_mbar_base);
8e585f02 271#endif
0c277ef9
TT
272 print_mhz("cpufreq", bd->bi_intfreq);
273 print_mhz("busfreq", bd->bi_busfreq);
8ae158cd 274#ifdef CONFIG_PCI
0c277ef9 275 print_mhz("pcifreq", bd->bi_pcifreq);
8ae158cd
TL
276#endif
277#ifdef CONFIG_EXTRA_CLOCK
0c277ef9
TT
278 print_mhz("flbfreq", bd->bi_flbfreq);
279 print_mhz("inpfreq", bd->bi_inpfreq);
280 print_mhz("vcofreq", bd->bi_vcofreq);
8ae158cd 281#endif
26667b7f 282#if defined(CONFIG_CMD_NET)
de2dff6f 283 print_eth(0);
8e585f02 284#if defined(CONFIG_HAS_ETH1)
de2dff6f 285 print_eth(1);
8e585f02 286#endif
8e585f02 287#if defined(CONFIG_HAS_ETH2)
de2dff6f 288 print_eth(2);
8e585f02 289#endif
8e585f02 290#if defined(CONFIG_HAS_ETH3)
de2dff6f 291 print_eth(3);
8e585f02
TL
292#endif
293
50a47d05 294 printf("ip_addr = %s\n", getenv("ipaddr"));
26667b7f 295#endif
8e261575 296 printf("baudrate = %u bps\n", gd->baudrate);
8e585f02
TL
297
298 return 0;
299}
300
8dc48d71 301#elif defined(CONFIG_BLACKFIN)
c99ea790 302
54841ab5 303int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8dc48d71 304{
8dc48d71
MF
305 bd_t *bd = gd->bd;
306
307 printf("U-Boot = %s\n", bd->bi_r_version);
308 printf("CPU = %s\n", bd->bi_cpu);
309 printf("Board = %s\n", bd->bi_board_name);
0c277ef9
TT
310 print_mhz("VCO", bd->bi_vco);
311 print_mhz("CCLK", bd->bi_cclk);
312 print_mhz("SCLK", bd->bi_sclk);
8dc48d71 313
5902e8f7
ML
314 print_num("boot_params", (ulong)bd->bi_boot_params);
315 print_num("memstart", (ulong)bd->bi_memstart);
316 print_lnum("memsize", (u64)bd->bi_memsize);
317 print_num("flashstart", (ulong)bd->bi_flashstart);
318 print_num("flashsize", (ulong)bd->bi_flashsize);
319 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8dc48d71 320
de2dff6f 321 print_eth(0);
50a47d05 322 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 323 printf("baudrate = %u bps\n", gd->baudrate);
8dc48d71
MF
324
325 return 0;
326}
327
c99ea790 328#elif defined(CONFIG_MIPS)
8bde7f77 329
5902e8f7 330int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 331{
8bde7f77
WD
332 bd_t *bd = gd->bd;
333
5902e8f7
ML
334 print_num("boot_params", (ulong)bd->bi_boot_params);
335 print_num("memstart", (ulong)bd->bi_memstart);
336 print_lnum("memsize", (u64)bd->bi_memsize);
337 print_num("flashstart", (ulong)bd->bi_flashstart);
338 print_num("flashsize", (ulong)bd->bi_flashsize);
339 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8bde7f77 340
de2dff6f 341 print_eth(0);
50a47d05 342 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 343 printf("baudrate = %u bps\n", gd->baudrate);
8bde7f77
WD
344
345 return 0;
346}
8bde7f77 347
c99ea790
RM
348#elif defined(CONFIG_AVR32)
349
5902e8f7 350int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c99ea790
RM
351{
352 bd_t *bd = gd->bd;
353
5902e8f7 354 print_num("boot_params", (ulong)bd->bi_boot_params);
a752a8b4
AB
355 print_num("memstart", (ulong)bd->bi_dram[0].start);
356 print_lnum("memsize", (u64)bd->bi_dram[0].size);
5902e8f7
ML
357 print_num("flashstart", (ulong)bd->bi_flashstart);
358 print_num("flashsize", (ulong)bd->bi_flashsize);
359 print_num("flashoffset", (ulong)bd->bi_flashoffset);
c99ea790
RM
360
361 print_eth(0);
50a47d05 362 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 363 printf("baudrate = %u bps\n", gd->baudrate);
c99ea790
RM
364
365 return 0;
366}
367
368#elif defined(CONFIG_ARM)
8bde7f77 369
0e350f81
JH
370static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
371 char * const argv[])
8bde7f77 372{
8bde7f77
WD
373 int i;
374 bd_t *bd = gd->bd;
375
5902e8f7
ML
376 print_num("arch_number", bd->bi_arch_number);
377 print_num("boot_params", (ulong)bd->bi_boot_params);
8bde7f77 378
5902e8f7 379 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
8bde7f77
WD
380 print_num("DRAM bank", i);
381 print_num("-> start", bd->bi_dram[i].start);
382 print_num("-> size", bd->bi_dram[i].size);
383 }
384
e8149522
YS
385#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
386 if (gd->secure_ram & MEM_RESERVE_SECURE_SECURED) {
387 print_num("Secure ram",
388 gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
389 }
390#endif
ff973800 391#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
9fc6a06a 392 print_eths();
a41dbbd9 393#endif
8e261575 394 printf("baudrate = %u bps\n", gd->baudrate);
e47f2db5 395#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
34fd5d25 396 print_num("TLB addr", gd->arch.tlb_addr);
f1d2b313 397#endif
5902e8f7
ML
398 print_num("relocaddr", gd->relocaddr);
399 print_num("reloc off", gd->reloc_off);
400 print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
401 print_num("sp start ", gd->start_addr_sp);
c8fcd0f2 402#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
5902e8f7 403 print_num("FB base ", gd->fb_base);
c8fcd0f2 404#endif
8f5d4687
HM
405 /*
406 * TODO: Currently only support for davinci SOC's is added.
407 * Remove this check once all the board implement this.
408 */
409#ifdef CONFIG_CLOCKS
410 printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
411 printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
412 printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
7bb7d672
HS
413#endif
414#ifdef CONFIG_BOARD_TYPES
415 printf("Board Type = %ld\n", gd->board_type);
8f5d4687 416#endif
8bde7f77
WD
417 return 0;
418}
419
ebd0d062
NI
420#elif defined(CONFIG_SH)
421
5902e8f7 422int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ebd0d062
NI
423{
424 bd_t *bd = gd->bd;
5902e8f7
ML
425 print_num("mem start ", (ulong)bd->bi_memstart);
426 print_lnum("mem size ", (u64)bd->bi_memsize);
427 print_num("flash start ", (ulong)bd->bi_flashstart);
428 print_num("flash size ", (ulong)bd->bi_flashsize);
429 print_num("flash offset ", (ulong)bd->bi_flashoffset);
ebd0d062
NI
430
431#if defined(CONFIG_CMD_NET)
432 print_eth(0);
50a47d05 433 printf("ip_addr = %s\n", getenv("ipaddr"));
ebd0d062 434#endif
8e261575 435 printf("baudrate = %u bps\n", gd->baudrate);
ebd0d062
NI
436 return 0;
437}
438
a806ee6f
GR
439#elif defined(CONFIG_X86)
440
5902e8f7 441int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a806ee6f
GR
442{
443 int i;
444 bd_t *bd = gd->bd;
a806ee6f 445
5902e8f7
ML
446 print_num("boot_params", (ulong)bd->bi_boot_params);
447 print_num("bi_memstart", bd->bi_memstart);
448 print_num("bi_memsize", bd->bi_memsize);
449 print_num("bi_flashstart", bd->bi_flashstart);
450 print_num("bi_flashsize", bd->bi_flashsize);
451 print_num("bi_flashoffset", bd->bi_flashoffset);
452 print_num("bi_sramstart", bd->bi_sramstart);
453 print_num("bi_sramsize", bd->bi_sramsize);
454 print_num("bi_bootflags", bd->bi_bootflags);
0c277ef9
TT
455 print_mhz("cpufreq", bd->bi_intfreq);
456 print_mhz("busfreq", bd->bi_busfreq);
5902e8f7
ML
457
458 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
a806ee6f
GR
459 print_num("DRAM bank", i);
460 print_num("-> start", bd->bi_dram[i].start);
461 print_num("-> size", bd->bi_dram[i].size);
462 }
463
464#if defined(CONFIG_CMD_NET)
465 print_eth(0);
50a47d05 466 printf("ip_addr = %s\n", getenv("ipaddr"));
0c277ef9 467 print_mhz("ethspeed", bd->bi_ethspeed);
a806ee6f 468#endif
8e261575 469 printf("baudrate = %u bps\n", gd->baudrate);
a806ee6f
GR
470
471 return 0;
472}
473
6fcc3be4
SG
474#elif defined(CONFIG_SANDBOX)
475
476int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
477{
478 int i;
479 bd_t *bd = gd->bd;
480
481 print_num("boot_params", (ulong)bd->bi_boot_params);
482
483 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
484 print_num("DRAM bank", i);
485 print_num("-> start", bd->bi_dram[i].start);
486 print_num("-> size", bd->bi_dram[i].size);
487 }
488
489#if defined(CONFIG_CMD_NET)
490 print_eth(0);
50a47d05 491 printf("ip_addr = %s\n", getenv("ipaddr"));
6fcc3be4 492#endif
c8fcd0f2 493#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
6fcc3be4 494 print_num("FB base ", gd->fb_base);
c8fcd0f2 495#endif
6fcc3be4
SG
496 return 0;
497}
498
64d61461
ML
499#elif defined(CONFIG_NDS32)
500
501int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
502{
503 int i;
504 bd_t *bd = gd->bd;
505
506 print_num("arch_number", bd->bi_arch_number);
507 print_num("boot_params", (ulong)bd->bi_boot_params);
508
509 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
510 print_num("DRAM bank", i);
511 print_num("-> start", bd->bi_dram[i].start);
512 print_num("-> size", bd->bi_dram[i].size);
513 }
514
515#if defined(CONFIG_CMD_NET)
516 print_eth(0);
50a47d05 517 printf("ip_addr = %s\n", getenv("ipaddr"));
64d61461 518#endif
8e261575 519 printf("baudrate = %u bps\n", gd->baudrate);
64d61461
ML
520
521 return 0;
522}
523
2be9fdbf
SK
524#elif defined(CONFIG_OPENRISC)
525
526int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
527{
528 bd_t *bd = gd->bd;
529
530 print_num("mem start", (ulong)bd->bi_memstart);
531 print_lnum("mem size", (u64)bd->bi_memsize);
532 print_num("flash start", (ulong)bd->bi_flashstart);
533 print_num("flash size", (ulong)bd->bi_flashsize);
534 print_num("flash offset", (ulong)bd->bi_flashoffset);
535
536#if defined(CONFIG_CMD_NET)
537 print_eth(0);
50a47d05 538 printf("ip_addr = %s\n", getenv("ipaddr"));
2be9fdbf
SK
539#endif
540
8e261575 541 printf("baudrate = %u bps\n", gd->baudrate);
2be9fdbf
SK
542
543 return 0;
544}
545
946f6f24 546#elif defined(CONFIG_ARC)
bc5d5428
AB
547
548int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
549{
550 bd_t *bd = gd->bd;
551
552 print_num("mem start", bd->bi_memstart);
553 print_lnum("mem size", bd->bi_memsize);
554
555#if defined(CONFIG_CMD_NET)
556 print_eth(0);
557 printf("ip_addr = %s\n", getenv("ipaddr"));
558#endif
8e261575 559 printf("baudrate = %d bps\n", gd->baudrate);
bc5d5428
AB
560
561 return 0;
562}
563
c99ea790
RM
564#else
565 #error "a case for this architecture does not exist!"
566#endif
8bde7f77 567
8bde7f77
WD
568/* -------------------------------------------------------------------- */
569
0d498393
WD
570U_BOOT_CMD(
571 bdinfo, 1, 1, do_bdinfo,
2fb2604d 572 "print Board Info structure",
a89c33db 573 ""
8bde7f77 574);