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Merge branch 'master' of git://git.denx.de/u-boot-ubi
[people/ms/u-boot.git] / common / cmd_bdinfo.c
CommitLineData
8bde7f77
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
8bde7f77
WD
6 */
7
8/*
9 * Boot support
10 */
11#include <common.h>
12#include <command.h>
d88af4da 13#include <linux/compiler.h>
8bde7f77 14
d87080b7 15DECLARE_GLOBAL_DATA_PTR;
8bde7f77 16
d88af4da
MF
17__maybe_unused
18static void print_num(const char *name, ulong value)
19{
20 printf("%-12s= 0x%08lX\n", name, value);
21}
8bde7f77 22
5f3dfadc 23__maybe_unused
d88af4da
MF
24static void print_eth(int idx)
25{
26 char name[10], *val;
27 if (idx)
28 sprintf(name, "eth%iaddr", idx);
29 else
30 strcpy(name, "ethaddr");
31 val = getenv(name);
32 if (!val)
33 val = "(not set)";
34 printf("%-12s= %s\n", name, val);
35}
de2dff6f 36
9fc6a06a
MS
37__maybe_unused
38static void print_eths(void)
39{
40 struct eth_device *dev;
41 int i = 0;
42
43 do {
44 dev = eth_get_dev_by_index(i);
45 if (dev) {
46 printf("eth%dname = %s\n", i, dev->name);
47 print_eth(i);
48 i++;
49 }
50 } while (dev);
51
52 printf("current eth = %s\n", eth_get_name());
53 printf("ip_addr = %s\n", getenv("ipaddr"));
54}
55
d88af4da 56__maybe_unused
47708457 57static void print_lnum(const char *name, unsigned long long value)
d88af4da
MF
58{
59 printf("%-12s= 0x%.8llX\n", name, value);
60}
61
62__maybe_unused
63static void print_mhz(const char *name, unsigned long hz)
64{
65 char buf[32];
66
67 printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
68}
8bde7f77 69
c99ea790 70#if defined(CONFIG_PPC)
e7939464
YS
71void __weak board_detail(void)
72{
73 /* Please define boot_detail() for your platform */
74}
8bde7f77 75
5902e8f7 76int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 77{
8bde7f77 78 bd_t *bd = gd->bd;
8bde7f77
WD
79
80#ifdef DEBUG
5902e8f7
ML
81 print_num("bd address", (ulong)bd);
82#endif
83 print_num("memstart", bd->bi_memstart);
84 print_lnum("memsize", bd->bi_memsize);
85 print_num("flashstart", bd->bi_flashstart);
86 print_num("flashsize", bd->bi_flashsize);
87 print_num("flashoffset", bd->bi_flashoffset);
88 print_num("sramstart", bd->bi_sramstart);
89 print_num("sramsize", bd->bi_sramsize);
90#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
58dac327 91 defined(CONFIG_MPC8260) || defined(CONFIG_E500)
5902e8f7
ML
92 print_num("immr_base", bd->bi_immr_base);
93#endif
94 print_num("bootflags", bd->bi_bootflags);
3fb85889 95#if defined(CONFIG_405EP) || \
5902e8f7
ML
96 defined(CONFIG_405GP) || \
97 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
98 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
99 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
100 defined(CONFIG_XILINX_405)
0c277ef9
TT
101 print_mhz("procfreq", bd->bi_procfreq);
102 print_mhz("plb_busfreq", bd->bi_plb_busfreq);
5902e8f7
ML
103#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
104 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
105 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
0c277ef9 107 print_mhz("pci_busfreq", bd->bi_pci_busfreq);
8bde7f77 108#endif
3fb85889 109#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
9c4c5ae3 110#if defined(CONFIG_CPM2)
0c277ef9
TT
111 print_mhz("vco", bd->bi_vco);
112 print_mhz("sccfreq", bd->bi_sccfreq);
113 print_mhz("brgfreq", bd->bi_brgfreq);
8bde7f77 114#endif
0c277ef9 115 print_mhz("intfreq", bd->bi_intfreq);
9c4c5ae3 116#if defined(CONFIG_CPM2)
0c277ef9 117 print_mhz("cpmfreq", bd->bi_cpmfreq);
8bde7f77 118#endif
0c277ef9 119 print_mhz("busfreq", bd->bi_busfreq);
3fb85889 120#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
03f5c550 121
34e210f5
TT
122#ifdef CONFIG_ENABLE_36BIT_PHYS
123#ifdef CONFIG_PHYS_64BIT
124 puts("addressing = 36-bit\n");
125#else
126 puts("addressing = 32-bit\n");
127#endif
128#endif
129
de2dff6f 130 print_eth(0);
e2ffd59b 131#if defined(CONFIG_HAS_ETH1)
de2dff6f 132 print_eth(1);
03f5c550 133#endif
e2ffd59b 134#if defined(CONFIG_HAS_ETH2)
de2dff6f 135 print_eth(2);
42d1f039 136#endif
e2ffd59b 137#if defined(CONFIG_HAS_ETH3)
de2dff6f 138 print_eth(3);
03f5c550 139#endif
c68a05fe 140#if defined(CONFIG_HAS_ETH4)
de2dff6f 141 print_eth(4);
c68a05fe 142#endif
c68a05fe 143#if defined(CONFIG_HAS_ETH5)
de2dff6f 144 print_eth(5);
c68a05fe 145#endif
146
50a47d05 147 printf("IP addr = %s\n", getenv("ipaddr"));
8e261575 148 printf("baudrate = %6u bps\n", gd->baudrate);
5902e8f7 149 print_num("relocaddr", gd->relocaddr);
e7939464 150 board_detail();
8bde7f77
WD
151 return 0;
152}
153
c99ea790 154#elif defined(CONFIG_NIOS2)
5c952cf0 155
5902e8f7 156int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
5c952cf0 157{
5c952cf0
WD
158 bd_t *bd = gd->bd;
159
5902e8f7
ML
160 print_num("mem start", (ulong)bd->bi_memstart);
161 print_lnum("mem size", (u64)bd->bi_memsize);
162 print_num("flash start", (ulong)bd->bi_flashstart);
163 print_num("flash size", (ulong)bd->bi_flashsize);
164 print_num("flash offset", (ulong)bd->bi_flashoffset);
5c952cf0 165
6d0f6bcf 166#if defined(CONFIG_SYS_SRAM_BASE)
5c952cf0
WD
167 print_num ("sram start", (ulong)bd->bi_sramstart);
168 print_num ("sram size", (ulong)bd->bi_sramsize);
169#endif
170
90253178 171#if defined(CONFIG_CMD_NET)
de2dff6f 172 print_eth(0);
50a47d05 173 printf("ip_addr = %s\n", getenv("ipaddr"));
5c952cf0
WD
174#endif
175
8e261575 176 printf("baudrate = %u bps\n", gd->baudrate);
5c952cf0
WD
177
178 return 0;
179}
c99ea790
RM
180
181#elif defined(CONFIG_MICROBLAZE)
cfc67116 182
5902e8f7 183int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cfc67116 184{
cfc67116 185 bd_t *bd = gd->bd;
5902e8f7
ML
186 print_num("mem start ", (ulong)bd->bi_memstart);
187 print_lnum("mem size ", (u64)bd->bi_memsize);
188 print_num("flash start ", (ulong)bd->bi_flashstart);
189 print_num("flash size ", (ulong)bd->bi_flashsize);
190 print_num("flash offset ", (ulong)bd->bi_flashoffset);
6d0f6bcf 191#if defined(CONFIG_SYS_SRAM_BASE)
5902e8f7
ML
192 print_num("sram start ", (ulong)bd->bi_sramstart);
193 print_num("sram size ", (ulong)bd->bi_sramsize);
cfc67116 194#endif
90253178 195#if defined(CONFIG_CMD_NET)
9fc6a06a 196 print_eths();
cfc67116 197#endif
8e261575 198 printf("baudrate = %u bps\n", gd->baudrate);
cfc67116
MS
199 return 0;
200}
4a551709 201
c99ea790
RM
202#elif defined(CONFIG_SPARC)
203
54841ab5 204int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
00ab32c8
DH
205{
206 bd_t *bd = gd->bd;
00ab32c8
DH
207
208#ifdef DEBUG
209 print_num("bd address ", (ulong) bd);
210#endif
211 print_num("memstart ", bd->bi_memstart);
b57ca3e1 212 print_lnum("memsize ", bd->bi_memsize);
00ab32c8 213 print_num("flashstart ", bd->bi_flashstart);
6d0f6bcf 214 print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
0e8d1586 215 print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
d97f01a6 216 printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
6d0f6bcf 217 CONFIG_SYS_MONITOR_LEN);
d97f01a6 218 printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
6d0f6bcf 219 CONFIG_SYS_MALLOC_LEN);
d97f01a6 220 printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
6d0f6bcf 221 CONFIG_SYS_STACK_SIZE);
d97f01a6 222 printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
6d0f6bcf 223 CONFIG_SYS_PROM_SIZE);
d97f01a6 224 printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
25ddd1fb 225 GENERATED_GBL_DATA_SIZE);
00ab32c8
DH
226
227#if defined(CONFIG_CMD_NET)
de2dff6f 228 print_eth(0);
50a47d05 229 printf("ip_addr = %s\n", getenv("ipaddr"));
00ab32c8 230#endif
8e261575 231 printf("baudrate = %6u bps\n", gd->baudrate);
00ab32c8
DH
232 return 0;
233}
234
c99ea790
RM
235#elif defined(CONFIG_M68K)
236
5902e8f7 237int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8e585f02 238{
8e585f02 239 bd_t *bd = gd->bd;
8ae158cd 240
5902e8f7
ML
241 print_num("memstart", (ulong)bd->bi_memstart);
242 print_lnum("memsize", (u64)bd->bi_memsize);
243 print_num("flashstart", (ulong)bd->bi_flashstart);
244 print_num("flashsize", (ulong)bd->bi_flashsize);
245 print_num("flashoffset", (ulong)bd->bi_flashoffset);
6d0f6bcf 246#if defined(CONFIG_SYS_INIT_RAM_ADDR)
5902e8f7
ML
247 print_num("sramstart", (ulong)bd->bi_sramstart);
248 print_num("sramsize", (ulong)bd->bi_sramsize);
8e585f02 249#endif
6d0f6bcf 250#if defined(CONFIG_SYS_MBAR)
5902e8f7 251 print_num("mbar", bd->bi_mbar_base);
8e585f02 252#endif
0c277ef9
TT
253 print_mhz("cpufreq", bd->bi_intfreq);
254 print_mhz("busfreq", bd->bi_busfreq);
8ae158cd 255#ifdef CONFIG_PCI
0c277ef9 256 print_mhz("pcifreq", bd->bi_pcifreq);
8ae158cd
TL
257#endif
258#ifdef CONFIG_EXTRA_CLOCK
0c277ef9
TT
259 print_mhz("flbfreq", bd->bi_flbfreq);
260 print_mhz("inpfreq", bd->bi_inpfreq);
261 print_mhz("vcofreq", bd->bi_vcofreq);
8ae158cd 262#endif
26667b7f 263#if defined(CONFIG_CMD_NET)
de2dff6f 264 print_eth(0);
8e585f02 265#if defined(CONFIG_HAS_ETH1)
de2dff6f 266 print_eth(1);
8e585f02 267#endif
8e585f02 268#if defined(CONFIG_HAS_ETH2)
de2dff6f 269 print_eth(2);
8e585f02 270#endif
8e585f02 271#if defined(CONFIG_HAS_ETH3)
de2dff6f 272 print_eth(3);
8e585f02
TL
273#endif
274
50a47d05 275 printf("ip_addr = %s\n", getenv("ipaddr"));
26667b7f 276#endif
8e261575 277 printf("baudrate = %u bps\n", gd->baudrate);
8e585f02
TL
278
279 return 0;
280}
281
8dc48d71 282#elif defined(CONFIG_BLACKFIN)
c99ea790 283
54841ab5 284int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8dc48d71 285{
8dc48d71
MF
286 bd_t *bd = gd->bd;
287
288 printf("U-Boot = %s\n", bd->bi_r_version);
289 printf("CPU = %s\n", bd->bi_cpu);
290 printf("Board = %s\n", bd->bi_board_name);
0c277ef9
TT
291 print_mhz("VCO", bd->bi_vco);
292 print_mhz("CCLK", bd->bi_cclk);
293 print_mhz("SCLK", bd->bi_sclk);
8dc48d71 294
5902e8f7
ML
295 print_num("boot_params", (ulong)bd->bi_boot_params);
296 print_num("memstart", (ulong)bd->bi_memstart);
297 print_lnum("memsize", (u64)bd->bi_memsize);
298 print_num("flashstart", (ulong)bd->bi_flashstart);
299 print_num("flashsize", (ulong)bd->bi_flashsize);
300 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8dc48d71 301
de2dff6f 302 print_eth(0);
50a47d05 303 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 304 printf("baudrate = %u bps\n", gd->baudrate);
8dc48d71
MF
305
306 return 0;
307}
308
c99ea790 309#elif defined(CONFIG_MIPS)
8bde7f77 310
5902e8f7 311int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 312{
8bde7f77
WD
313 bd_t *bd = gd->bd;
314
5902e8f7
ML
315 print_num("boot_params", (ulong)bd->bi_boot_params);
316 print_num("memstart", (ulong)bd->bi_memstart);
317 print_lnum("memsize", (u64)bd->bi_memsize);
318 print_num("flashstart", (ulong)bd->bi_flashstart);
319 print_num("flashsize", (ulong)bd->bi_flashsize);
320 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8bde7f77 321
de2dff6f 322 print_eth(0);
50a47d05 323 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 324 printf("baudrate = %u bps\n", gd->baudrate);
8bde7f77
WD
325
326 return 0;
327}
8bde7f77 328
c99ea790
RM
329#elif defined(CONFIG_AVR32)
330
5902e8f7 331int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c99ea790
RM
332{
333 bd_t *bd = gd->bd;
334
5902e8f7
ML
335 print_num("boot_params", (ulong)bd->bi_boot_params);
336 print_num("memstart", (ulong)bd->bi_memstart);
337 print_lnum("memsize", (u64)bd->bi_memsize);
338 print_num("flashstart", (ulong)bd->bi_flashstart);
339 print_num("flashsize", (ulong)bd->bi_flashsize);
340 print_num("flashoffset", (ulong)bd->bi_flashoffset);
c99ea790
RM
341
342 print_eth(0);
50a47d05 343 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 344 printf("baudrate = %u bps\n", gd->baudrate);
c99ea790
RM
345
346 return 0;
347}
348
349#elif defined(CONFIG_ARM)
8bde7f77 350
0e350f81
JH
351static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
352 char * const argv[])
8bde7f77 353{
8bde7f77
WD
354 int i;
355 bd_t *bd = gd->bd;
356
5902e8f7
ML
357 print_num("arch_number", bd->bi_arch_number);
358 print_num("boot_params", (ulong)bd->bi_boot_params);
8bde7f77 359
5902e8f7 360 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
8bde7f77
WD
361 print_num("DRAM bank", i);
362 print_num("-> start", bd->bi_dram[i].start);
363 print_num("-> size", bd->bi_dram[i].size);
364 }
365
a41dbbd9 366#if defined(CONFIG_CMD_NET)
9fc6a06a 367 print_eths();
a41dbbd9 368#endif
8e261575 369 printf("baudrate = %u bps\n", gd->baudrate);
e47f2db5 370#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
34fd5d25 371 print_num("TLB addr", gd->arch.tlb_addr);
f1d2b313 372#endif
5902e8f7
ML
373 print_num("relocaddr", gd->relocaddr);
374 print_num("reloc off", gd->reloc_off);
375 print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
376 print_num("sp start ", gd->start_addr_sp);
c8fcd0f2 377#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
5902e8f7 378 print_num("FB base ", gd->fb_base);
c8fcd0f2 379#endif
8f5d4687
HM
380 /*
381 * TODO: Currently only support for davinci SOC's is added.
382 * Remove this check once all the board implement this.
383 */
384#ifdef CONFIG_CLOCKS
385 printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
386 printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
387 printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
388#endif
8bde7f77
WD
389 return 0;
390}
391
ebd0d062
NI
392#elif defined(CONFIG_SH)
393
5902e8f7 394int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ebd0d062
NI
395{
396 bd_t *bd = gd->bd;
5902e8f7
ML
397 print_num("mem start ", (ulong)bd->bi_memstart);
398 print_lnum("mem size ", (u64)bd->bi_memsize);
399 print_num("flash start ", (ulong)bd->bi_flashstart);
400 print_num("flash size ", (ulong)bd->bi_flashsize);
401 print_num("flash offset ", (ulong)bd->bi_flashoffset);
ebd0d062
NI
402
403#if defined(CONFIG_CMD_NET)
404 print_eth(0);
50a47d05 405 printf("ip_addr = %s\n", getenv("ipaddr"));
ebd0d062 406#endif
8e261575 407 printf("baudrate = %u bps\n", gd->baudrate);
ebd0d062
NI
408 return 0;
409}
410
a806ee6f
GR
411#elif defined(CONFIG_X86)
412
5902e8f7 413int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a806ee6f
GR
414{
415 int i;
416 bd_t *bd = gd->bd;
a806ee6f 417
5902e8f7
ML
418 print_num("boot_params", (ulong)bd->bi_boot_params);
419 print_num("bi_memstart", bd->bi_memstart);
420 print_num("bi_memsize", bd->bi_memsize);
421 print_num("bi_flashstart", bd->bi_flashstart);
422 print_num("bi_flashsize", bd->bi_flashsize);
423 print_num("bi_flashoffset", bd->bi_flashoffset);
424 print_num("bi_sramstart", bd->bi_sramstart);
425 print_num("bi_sramsize", bd->bi_sramsize);
426 print_num("bi_bootflags", bd->bi_bootflags);
0c277ef9
TT
427 print_mhz("cpufreq", bd->bi_intfreq);
428 print_mhz("busfreq", bd->bi_busfreq);
5902e8f7
ML
429
430 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
a806ee6f
GR
431 print_num("DRAM bank", i);
432 print_num("-> start", bd->bi_dram[i].start);
433 print_num("-> size", bd->bi_dram[i].size);
434 }
435
436#if defined(CONFIG_CMD_NET)
437 print_eth(0);
50a47d05 438 printf("ip_addr = %s\n", getenv("ipaddr"));
0c277ef9 439 print_mhz("ethspeed", bd->bi_ethspeed);
a806ee6f 440#endif
8e261575 441 printf("baudrate = %u bps\n", gd->baudrate);
a806ee6f
GR
442
443 return 0;
444}
445
6fcc3be4
SG
446#elif defined(CONFIG_SANDBOX)
447
448int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
449{
450 int i;
451 bd_t *bd = gd->bd;
452
453 print_num("boot_params", (ulong)bd->bi_boot_params);
454
455 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
456 print_num("DRAM bank", i);
457 print_num("-> start", bd->bi_dram[i].start);
458 print_num("-> size", bd->bi_dram[i].size);
459 }
460
461#if defined(CONFIG_CMD_NET)
462 print_eth(0);
50a47d05 463 printf("ip_addr = %s\n", getenv("ipaddr"));
6fcc3be4 464#endif
c8fcd0f2 465#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
6fcc3be4 466 print_num("FB base ", gd->fb_base);
c8fcd0f2 467#endif
6fcc3be4
SG
468 return 0;
469}
470
64d61461
ML
471#elif defined(CONFIG_NDS32)
472
473int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
474{
475 int i;
476 bd_t *bd = gd->bd;
477
478 print_num("arch_number", bd->bi_arch_number);
479 print_num("boot_params", (ulong)bd->bi_boot_params);
480
481 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
482 print_num("DRAM bank", i);
483 print_num("-> start", bd->bi_dram[i].start);
484 print_num("-> size", bd->bi_dram[i].size);
485 }
486
487#if defined(CONFIG_CMD_NET)
488 print_eth(0);
50a47d05 489 printf("ip_addr = %s\n", getenv("ipaddr"));
64d61461 490#endif
8e261575 491 printf("baudrate = %u bps\n", gd->baudrate);
64d61461
ML
492
493 return 0;
494}
495
2be9fdbf
SK
496#elif defined(CONFIG_OPENRISC)
497
498int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
499{
500 bd_t *bd = gd->bd;
501
502 print_num("mem start", (ulong)bd->bi_memstart);
503 print_lnum("mem size", (u64)bd->bi_memsize);
504 print_num("flash start", (ulong)bd->bi_flashstart);
505 print_num("flash size", (ulong)bd->bi_flashsize);
506 print_num("flash offset", (ulong)bd->bi_flashoffset);
507
508#if defined(CONFIG_CMD_NET)
509 print_eth(0);
50a47d05 510 printf("ip_addr = %s\n", getenv("ipaddr"));
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511#endif
512
8e261575 513 printf("baudrate = %u bps\n", gd->baudrate);
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514
515 return 0;
516}
517
946f6f24 518#elif defined(CONFIG_ARC)
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519
520int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
521{
522 bd_t *bd = gd->bd;
523
524 print_num("mem start", bd->bi_memstart);
525 print_lnum("mem size", bd->bi_memsize);
526
527#if defined(CONFIG_CMD_NET)
528 print_eth(0);
529 printf("ip_addr = %s\n", getenv("ipaddr"));
530#endif
8e261575 531 printf("baudrate = %d bps\n", gd->baudrate);
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532
533 return 0;
534}
535
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536#else
537 #error "a case for this architecture does not exist!"
538#endif
8bde7f77 539
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540/* -------------------------------------------------------------------- */
541
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542U_BOOT_CMD(
543 bdinfo, 1, 1, do_bdinfo,
2fb2604d 544 "print Board Info structure",
a89c33db 545 ""
8bde7f77 546);