[people/ms/u-boot.git] / cpu / ppc4xx / cpu_init.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <ppc4xx_enet.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <ppc4xx.h>

#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
DECLARE_GLOBAL_DATA_PTR;
#endif

#ifndef CFG_PLL_RECONFIG
#define CFG_PLL_RECONFIG	0
#endif

void reconfigure_pll(u32 new_cpu_freq)
{
#if defined(CONFIG_440EPX)
	int	reset_needed = 0;
	u32	reg, temp;
	u32	prbdv0, target_prbdv0,				/* CLK_PRIMBD */
		fwdva, target_fwdva, fwdvb, target_fwdvb,	/* CLK_PLLD */
		fbdv, target_fbdv, lfbdv, target_lfbdv,
		perdv0,	target_perdv0,				/* CLK_PERD */
		spcid0,	target_spcid0;				/* CLK_SPCID */

	/* Reconfigure clocks if necessary.
	 * See PPC440EPx User's Manual, sections 8.2 and 14 */
	if (new_cpu_freq == 667) {
		target_prbdv0 = 2;
		target_fwdva = 2;
		target_fwdvb = 4;
		target_fbdv = 20;
		target_lfbdv = 1;
		target_perdv0 = 4;
		target_spcid0 = 4;

		mfcpr(clk_primbd, reg);
		temp = (reg & PRBDV_MASK) >> 24;
		prbdv0 = temp ? temp : 8;
		if (prbdv0 != target_prbdv0) {
			reg &= ~PRBDV_MASK;
			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
			mtcpr(clk_primbd, reg);
			reset_needed = 1;
		}

		mfcpr(clk_plld, reg);

		temp = (reg & PLLD_FWDVA_MASK) >> 16;
		fwdva = temp ? temp : 16;

		temp = (reg & PLLD_FWDVB_MASK) >> 8;
		fwdvb = temp ? temp : 8;

		temp = (reg & PLLD_FBDV_MASK) >> 24;
		fbdv = temp ? temp : 32;

		temp = (reg & PLLD_LFBDV_MASK);
		lfbdv = temp ? temp : 64;

		if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
				 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
			reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
				(target_lfbdv == 64 ? 0 : target_lfbdv);
			mtcpr(clk_plld, reg);
			reset_needed = 1;
		}

		mfcpr(clk_perd, reg);
		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
		if (perdv0 != target_perdv0) {
			reg &= ~CPR0_PERD_PERDV0_MASK;
			reg |= (target_perdv0 << 24);
			mtcpr(clk_perd, reg);
			reset_needed = 1;
		}

		mfcpr(clk_spcid, reg);
		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
		spcid0 = temp ? temp : 4;
		if (spcid0 != target_spcid0) {
			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
			mtcpr(clk_spcid, reg);
			reset_needed = 1;
		}

		/* Set reload inhibit so configuration will persist across
		 * processor resets */
		mfcpr(clk_icfg, reg);
		reg &= ~CPR0_ICFG_RLI_MASK;
		reg |= 1 << 31;
		mtcpr(clk_icfg, reg);
	}

	/* Reset processor if configuration changed */
	if (reset_needed) {
		__asm__ __volatile__ ("sync; isync");
		mtspr(dbcr0, 0x20000000);
	}
#endif
}

/*
 * Breath some life into the CPU...
 *
 * Reconfigure PLL if necessary,
 * set up the memory map,
 * initialize a bunch of registers
 */
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
	u32 val;
#endif

	reconfigure_pll(CFG_PLL_RECONFIG);

#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
	/*
	 * GPIO0 setup (select GPIO or alternate function)
	 */
#if defined(CFG_GPIO0_OR)
	out32(GPIO0_OR, CFG_GPIO0_OR);		/* set initial state of output pins	*/
#endif
#if defined(CFG_GPIO0_ODR)
	out32(GPIO0_ODR, CFG_GPIO0_ODR);	/* open-drain select			*/
#endif
	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select			*/
	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select				*/
	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
#if defined(CFG_GPIO0_ISR2H)
	out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
	out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
#endif
#if defined (CFG_GPIO0_TCR)
	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
#endif
#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */

#if defined (CONFIG_405EP)
	/*
	 * Set EMAC noise filter bits
	 */
	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);

	/*
	 * Enable the internal PCI arbiter
	 */
	mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
#endif /* CONFIG_405EP */

#if defined(CFG_4xx_GPIO_TABLE)
	gpio_set_chip_configuration();
#endif /* CFG_4xx_GPIO_TABLE */

	/*
	 * External Bus Controller (EBC) Setup
	 */
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405))
	/*
	 * Move the next instructions into icache, since these modify the flash
	 * we are running from!
	 */
	asm volatile("	bl	0f"		::: "lr");
	asm volatile("0:	mflr	3"		::: "r3");
	asm volatile("	addi	4, 0, 14"	::: "r4");
	asm volatile("	mtctr	4"		::: "ctr");
	asm volatile("1:	icbt	0, 3");
	asm volatile("	addi	3, 3, 32"	::: "r3");
	asm volatile("	bdnz	1b"		::: "ctr", "cr0");
	asm volatile("	addis	3, 0, 0x0"	::: "r3");
	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
	asm volatile("	mtctr	3"		::: "ctr");
	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
#endif

	mtebc(pb0ap, CFG_EBC_PB0AP);
	mtebc(pb0cr, CFG_EBC_PB0CR);
#endif

#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
	mtebc(pb1ap, CFG_EBC_PB1AP);
	mtebc(pb1cr, CFG_EBC_PB1CR);
#endif

#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
	mtebc(pb2ap, CFG_EBC_PB2AP);
	mtebc(pb2cr, CFG_EBC_PB2CR);
#endif

#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
	mtebc(pb3ap, CFG_EBC_PB3AP);
	mtebc(pb3cr, CFG_EBC_PB3CR);
#endif

#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
	mtebc(pb4ap, CFG_EBC_PB4AP);
	mtebc(pb4cr, CFG_EBC_PB4CR);
#endif

#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
	mtebc(pb5ap, CFG_EBC_PB5AP);
	mtebc(pb5cr, CFG_EBC_PB5CR);
#endif

#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
	mtebc(pb6ap, CFG_EBC_PB6AP);
	mtebc(pb6cr, CFG_EBC_PB6CR);
#endif

#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
	mtebc(pb7ap, CFG_EBC_PB7AP);
	mtebc(pb7cr, CFG_EBC_PB7CR);
#endif

#if defined (CFG_EBC_CFG)
	mtebc(EBC0_CFG, CFG_EBC_CFG);
#endif

#if defined(CONFIG_WATCHDOG)
	val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
	val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
#else
	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
#endif
#if defined(CFG_4xx_RESET_TYPE)
	val &= ~0x30000000;			/* clear WRC bits */
	val |= CFG_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
#endif
	mtspr(tcr, val);

	val = mfspr(tsr);
	val |= 0x80000000;      /* enable watchdog timer */
	mtspr(tsr, val);

	reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */

#if defined(CONFIG_440GX)
	/* Take the GX out of compatibility mode
	 * Travis Sawyer, 9 Mar 2004
	 * NOTE: 440gx user manual inconsistency here
	 *       Compatibility mode and Ethernet Clock select are not
	 *       correct in the manual
	 */
	mfsdr(sdr_mfr, val);
	val &= ~0x10000000;
	mtsdr(sdr_mfr,val);
#endif /* CONFIG_440GX */

#if defined(CONFIG_460EX)
	/*
	 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	 */
	mfsdr(SDR0_AHB_CFG, val);
	val |= 0x80;
	val &= ~0x40;
	mtsdr(SDR0_AHB_CFG, val);
	mfsdr(SDR0_USB2HOST_CFG, val);
	val &= ~0xf00;
	val |= 0x400;
	mtsdr(SDR0_USB2HOST_CFG, val);
#endif /* CONFIG_460EX */

#if defined(CONFIG_405EX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
    defined(CONFIG_460SX)
	/*
	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	 */
	mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
	      plb0_acr_rdp_4deep);
	mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
	      plb1_acr_rdp_4deep);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
	bd_t *bd = gd->bd;
	unsigned long reg;
#if defined(CONFIG_405GP)
	uint pvr = get_pvr();
#endif

	/*
	 * Write Ethernetaddress into on-chip register
	 */
	reg = 0x00000000;
	reg |= bd->bi_enetaddr[0];           /* set high address */
	reg = reg << 8;
	reg |= bd->bi_enetaddr[1];
	out32 (EMAC_IAH, reg);

	reg = 0x00000000;
	reg |= bd->bi_enetaddr[2];           /* set low address  */
	reg = reg << 8;
	reg |= bd->bi_enetaddr[3];
	reg = reg << 8;
	reg |= bd->bi_enetaddr[4];
	reg = reg << 8;
	reg |= bd->bi_enetaddr[5];
	out32 (EMAC_IAL, reg);

#if defined(CONFIG_405GP)
	/*
	 * Set edge conditioning circuitry on PPC405GPr
	 * for compatibility to existing PPC405GP designs.
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		mtdcr(ecr, 0x60606000);
	}
#endif  /* defined(CONFIG_405GP) */
#endif  /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */

	return (0);
}
Commit	Line	Data
4a9cbbe8	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <watchdog.h>
d6c61aab	26	#include <ppc4xx_enet.h>
4a9cbbe8	27	#include <asm/processor.h>
0d974d52	28	#include <asm/gpio.h>
4a9cbbe8 WD	29	#include <ppc4xx.h>
4a9cbbe8 WD	30
d87080b7 WD	31	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
	32	DECLARE_GLOBAL_DATA_PTR;
	33	#endif
	34
f66e2c8b MN	35	#ifndef CFG_PLL_RECONFIG
	36	#define CFG_PLL_RECONFIG 0
	37	#endif
	38
	39	void reconfigure_pll(u32 new_cpu_freq)
	40	{
	41	#if defined(CONFIG_440EPX)
	42	int reset_needed = 0;
	43	u32 reg, temp;
	44	u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
	45	fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
	46	fbdv, target_fbdv, lfbdv, target_lfbdv,
	47	perdv0, target_perdv0, /* CLK_PERD */
	48	spcid0, target_spcid0; /* CLK_SPCID */
	49
	50	/* Reconfigure clocks if necessary.
	51	* See PPC440EPx User's Manual, sections 8.2 and 14 */
	52	if (new_cpu_freq == 667) {
	53	target_prbdv0 = 2;
	54	target_fwdva = 2;
	55	target_fwdvb = 4;
	56	target_fbdv = 20;
	57	target_lfbdv = 1;
	58	target_perdv0 = 4;
	59	target_spcid0 = 4;
	60
	61	mfcpr(clk_primbd, reg);
	62	temp = (reg & PRBDV_MASK) >> 24;
	63	prbdv0 = temp ? temp : 8;
	64	if (prbdv0 != target_prbdv0) {
	65	reg &= ~PRBDV_MASK;
	66	reg \|= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
	67	mtcpr(clk_primbd, reg);
	68	reset_needed = 1;
	69	}
	70
	71	mfcpr(clk_plld, reg);
	72
	73	temp = (reg & PLLD_FWDVA_MASK) >> 16;
	74	fwdva = temp ? temp : 16;
	75
	76	temp = (reg & PLLD_FWDVB_MASK) >> 8;
	77	fwdvb = temp ? temp : 8;
	78
	79	temp = (reg & PLLD_FBDV_MASK) >> 24;
	80	fbdv = temp ? temp : 32;
	81
	82	temp = (reg & PLLD_LFBDV_MASK);
	83	lfbdv = temp ? temp : 64;
	84
	85	if (fwdva != target_fwdva \|\| fbdv != target_fbdv \|\| lfbdv != target_lfbdv) {
	86	reg &= ~(PLLD_FWDVA_MASK \| PLLD_FWDVB_MASK \|
	87	PLLD_FBDV_MASK \| PLLD_LFBDV_MASK);
	88	reg \|= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) \|
	89	((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) \|
	90	((target_fbdv == 32 ? 0 : target_fbdv) << 24) \|
	91	(target_lfbdv == 64 ? 0 : target_lfbdv);
	92	mtcpr(clk_plld, reg);
	93	reset_needed = 1;
	94	}
	95
	96	mfcpr(clk_perd, reg);
	97	perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
	98	if (perdv0 != target_perdv0) {
99	reg &= ~CPR0_PERD_PERDV0_MASK;
100	reg \|= (target_perdv0 << 24);
101	mtcpr(clk_perd, reg);
102	reset_needed = 1;
103	}
104
105	mfcpr(clk_spcid, reg);
106	temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
107	spcid0 = temp ? temp : 4;
108	if (spcid0 != target_spcid0) {
109	reg &= ~CPR0_SPCID_SPCIDV0_MASK;
110	reg \|= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
111	mtcpr(clk_spcid, reg);
112	reset_needed = 1;
113	}
114
115	/* Set reload inhibit so configuration will persist across
116	* processor resets */
117	mfcpr(clk_icfg, reg);
118	reg &= ~CPR0_ICFG_RLI_MASK;
119	reg \|= 1 << 31;
120	mtcpr(clk_icfg, reg);
121	}
122
123	/* Reset processor if configuration changed */
124	if (reset_needed) {
125	__asm__ __volatile__ ("sync; isync");
126	mtspr(dbcr0, 0x20000000);
127	}
128	#endif
129	}
130
4a9cbbe8 WD	131	/*
	132	* Breath some life into the CPU...
	133	*
f66e2c8b MN	134	* Reconfigure PLL if necessary,
f66e2c8b MN	135	* set up the memory map,
4a9cbbe8 WD	136	* initialize a bunch of registers
	137	*/
	138	void
	139	cpu_init_f (void)
	140	{
f5564837	141	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_440GX) \|\| defined(CONFIG_460EX)
745d8a0d	142	u32 val;
f11033e7	143	#endif
5de85140	144
f66e2c8b	145	reconfigure_pll(CFG_PLL_RECONFIG);
f11033e7	146
aee747f1	147	#if (defined(CONFIG_405EP) \|\| defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
b867d705 SR	148	/*
	149	* GPIO0 setup (select GPIO or alternate function)
	150	*/
e0a46554 SR	151	#if defined(CFG_GPIO0_OR)
	152	out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
	153	#endif
	154	#if defined(CFG_GPIO0_ODR)
	155	out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
	156	#endif
	157	out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
b867d705	158	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
e0a46554	159	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
b867d705	160	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
e0a46554	161	out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
b867d705	162	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
dbbd1257 SR	163	#if defined(CFG_GPIO0_ISR2H)
	164	out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
	165	out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
	166	#endif
	167	#if defined (CFG_GPIO0_TCR)
e0a46554	168	out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
dbbd1257	169	#endif
f766cdf8	170	#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
b867d705	171
bec92646	172	#if defined (CONFIG_405EP)
b867d705 SR	173	/*
	174	* Set EMAC noise filter bits
	175	*/
	176	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE \| CPC0_EPRCSR_E1NFE);
c0556906 SR	177
	178	/*
	179	* Enable the internal PCI arbiter
	180	*/
	181	mtdcr(cpc0_pci, mfdcr(cpc0_pci) \| CPC0_PCI_HOST_CFG_EN \| CPC0_PCI_ARBIT_EN);
b867d705 SR	182	#endif /* CONFIG_405EP */
b867d705 SR	183
aee747f1	184	#if defined(CFG_4xx_GPIO_TABLE)
0d974d52	185	gpio_set_chip_configuration();
aee747f1	186	#endif /* CFG_4xx_GPIO_TABLE */
a4c8d138	187
4a9cbbe8 WD	188	/*
	189	* External Bus Controller (EBC) Setup
	190	*/
	191	#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
a4c8d138	192	#if (defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
e01bd218	193	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| \
dbbd1257	194	defined(CONFIG_405EX) \|\| defined(CONFIG_405))
4a9cbbe8 WD	195	/*
	196	* Move the next instructions into icache, since these modify the flash
	197	* we are running from!
	198	*/
	199	asm volatile(" bl 0f" ::: "lr");
	200	asm volatile("0: mflr 3" ::: "r3");
1636d1c8	201	asm volatile(" addi 4, 0, 14" ::: "r4");
4a9cbbe8 WD	202	asm volatile(" mtctr 4" ::: "ctr");
	203	asm volatile("1: icbt 0, 3");
	204	asm volatile(" addi 3, 3, 32" ::: "r3");
	205	asm volatile(" bdnz 1b" ::: "ctr", "cr0");
	206	asm volatile(" addis 3, 0, 0x0" ::: "r3");
	207	asm volatile(" ori 3, 3, 0xA000" ::: "r3");
	208	asm volatile(" mtctr 3" ::: "ctr");
	209	asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
a4c8d138	210	#endif
4a9cbbe8 WD	211
	212	mtebc(pb0ap, CFG_EBC_PB0AP);
	213	mtebc(pb0cr, CFG_EBC_PB0CR);
	214	#endif
	215
37208785	216	#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
4a9cbbe8 WD	217	mtebc(pb1ap, CFG_EBC_PB1AP);
	218	mtebc(pb1cr, CFG_EBC_PB1CR);
	219	#endif
	220
37208785	221	#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
4a9cbbe8 WD	222	mtebc(pb2ap, CFG_EBC_PB2AP);
	223	mtebc(pb2cr, CFG_EBC_PB2CR);
	224	#endif
	225
37208785	226	#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
4a9cbbe8 WD	227	mtebc(pb3ap, CFG_EBC_PB3AP);
	228	mtebc(pb3cr, CFG_EBC_PB3CR);
	229	#endif
	230
37208785	231	#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
4a9cbbe8 WD	232	mtebc(pb4ap, CFG_EBC_PB4AP);
	233	mtebc(pb4cr, CFG_EBC_PB4CR);
	234	#endif
	235
37208785	236	#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
4a9cbbe8 WD	237	mtebc(pb5ap, CFG_EBC_PB5AP);
	238	mtebc(pb5cr, CFG_EBC_PB5CR);
	239	#endif
	240
37208785	241	#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
4a9cbbe8 WD	242	mtebc(pb6ap, CFG_EBC_PB6AP);
	243	mtebc(pb6cr, CFG_EBC_PB6CR);
	244	#endif
	245
37208785	246	#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
4a9cbbe8 WD	247	mtebc(pb7ap, CFG_EBC_PB7AP);
	248	mtebc(pb7cr, CFG_EBC_PB7CR);
	249	#endif
	250
cb482072	251	#if defined (CFG_EBC_CFG)
4745acaa	252	mtebc(EBC0_CFG, CFG_EBC_CFG);
ca43ba18	253	#endif
4a9cbbe8	254
f11033e7	255	#if defined(CONFIG_WATCHDOG)
4a9cbbe8	256	val = mfspr(tcr);
846b0dd2	257	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
c157d8e2	258	val \|= 0xb8000000; /* generate system reset after 1.34 seconds */
a11e0696 IL	259	#elif defined(CONFIG_440EPX)
a11e0696 IL	260	val \|= 0xb0000000; /* generate system reset after 1.34 seconds */
c157d8e2	261	#else
4a9cbbe8	262	val \|= 0xf0000000; /* generate system reset after 2.684 seconds */
1c2ce226 SR	263	#endif
	264	#if defined(CFG_4xx_RESET_TYPE)
	265	val &= ~0x30000000; /* clear WRC bits */
	266	val \|= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
c157d8e2	267	#endif
4a9cbbe8 WD	268	mtspr(tcr, val);
	269
	270	val = mfspr(tsr);
	271	val \|= 0x80000000; /* enable watchdog timer */
	272	mtspr(tsr, val);
	273
	274	reset_4xx_watchdog();
	275	#endif /* CONFIG_WATCHDOG */
745d8a0d	276
5de85140 SR	277	#if defined(CONFIG_440GX)
	278	/* Take the GX out of compatibility mode
	279	* Travis Sawyer, 9 Mar 2004
	280	* NOTE: 440gx user manual inconsistency here
	281	* Compatibility mode and Ethernet Clock select are not
	282	* correct in the manual
	283	*/
	284	mfsdr(sdr_mfr, val);
	285	val &= ~0x10000000;
	286	mtsdr(sdr_mfr,val);
	287	#endif /* CONFIG_440GX */
	288
745d8a0d SR	289	#if defined(CONFIG_460EX)
	290	/*
	291	* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	292	* clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	293	* regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	294	*/
	295	mfsdr(SDR0_AHB_CFG, val);
	296	val \|= 0x80;
	297	val &= ~0x40;
	298	mtsdr(SDR0_AHB_CFG, val);
	299	mfsdr(SDR0_USB2HOST_CFG, val);
	300	val &= ~0xf00;
	301	val \|= 0x400;
	302	mtsdr(SDR0_USB2HOST_CFG, val);
	303	#endif /* CONFIG_460EX */
079589bc	304
f5564837 SR	305	#if defined(CONFIG_405EX) \|\| \
f5564837 SR	306	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
079589bc	307	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
f5564837	308	defined(CONFIG_460SX)
079589bc PH	309	/*
	310	* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	311	*/
f5564837 SR	312	mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) \|
	313	plb0_acr_rdp_4deep);
	314	mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) \|
	315	plb1_acr_rdp_4deep);
079589bc	316	#endif /* CONFIG_440SP/SPE \|\| CONFIG_460EX/GT \|\| CONFIG_405EX */
4a9cbbe8 WD	317	}
	318
	319	/*
	320	* initialize higher level parts of CPU like time base and timers
	321	*/
	322	int cpu_init_r (void)
	323	{
b867d705	324	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
4a9cbbe8 WD	325	bd_t *bd = gd->bd;
4a9cbbe8 WD	326	unsigned long reg;
b867d705	327	#if defined(CONFIG_405GP)
38daa27d	328	uint pvr = get_pvr();
b867d705	329	#endif
4a9cbbe8 WD	330
	331	/*
	332	* Write Ethernetaddress into on-chip register
	333	*/
	334	reg = 0x00000000;
	335	reg \|= bd->bi_enetaddr[0]; /* set high address */
	336	reg = reg << 8;
	337	reg \|= bd->bi_enetaddr[1];
	338	out32 (EMAC_IAH, reg);
	339
	340	reg = 0x00000000;
	341	reg \|= bd->bi_enetaddr[2]; /* set low address */
	342	reg = reg << 8;
	343	reg \|= bd->bi_enetaddr[3];
	344	reg = reg << 8;
	345	reg \|= bd->bi_enetaddr[4];
	346	reg = reg << 8;
	347	reg \|= bd->bi_enetaddr[5];
	348	out32 (EMAC_IAL, reg);
38daa27d	349
b867d705	350	#if defined(CONFIG_405GP)
38daa27d SR	351	/*
	352	* Set edge conditioning circuitry on PPC405GPr
	353	* for compatibility to existing PPC405GP designs.
	354	*/
baa3d528	355	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
38daa27d SR	356	mtdcr(ecr, 0x60606000);
38daa27d SR	357	}
b867d705 SR	358	#endif /* defined(CONFIG_405GP) */
b867d705 SR	359	#endif /* defined(CONFIG_405GP) \|\| defined(CONFIG_405EP) */
2801b2d2	360
4a9cbbe8 WD	361	return (0);
4a9cbbe8 WD	362	}