[people/ms/u-boot.git] / cpu / ppc4xx / gpio.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>

#if defined(CFG_4xx_GPIO_TABLE)
gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
#endif

#if defined(GPIO0_OSRL)
/* Only some 4xx variants support alternate funtions on the GPIO's */
void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
{
	u32 mask;
	u32 mask2;
	u32 val;
	u32 offs = 0;
	u32 offs2 = 0;
	int pin2 = pin << 1;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (pin >= GPIO_MAX/2) {
		offs2 = 0x4;
		pin2 = (pin - GPIO_MAX/2) << 1;
	}

	mask = 0x80000000 >> pin;
	mask2 = 0xc0000000 >> (pin2 << 1);

	/* first set TCR to 0 */
	out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);

	if (in_out == GPIO_OUT) {
		val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
		switch (gpio_alt) {
		case GPIO_ALT1:
			val |= GPIO_ALT1_SEL >> pin2;
			break;
		case GPIO_ALT2:
			val |= GPIO_ALT2_SEL >> pin2;
			break;
		case GPIO_ALT3:
			val |= GPIO_ALT3_SEL >> pin2;
			break;
		}
		out_be32((void *)GPIO0_OSRL + offs + offs2, val);

		/* setup requested output value */
		if (out_val == GPIO_OUT_0)
			out_be32((void *)GPIO0_OR + offs,
				 in_be32((void *)GPIO0_OR + offs) & ~mask);
		else if (out_val == GPIO_OUT_1)
			out_be32((void *)GPIO0_OR + offs,
				 in_be32((void *)GPIO0_OR + offs) | mask);

		/* now configure TCR to drive output if selected */
		out_be32((void *)GPIO0_TCR + offs,
			 in_be32((void *)GPIO0_TCR + offs) | mask);
	} else {
		val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
		val |= GPIO_IN_SEL >> pin2;
		out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
	}
}
#endif /* GPIO_OSRL */

void gpio_write_bit(int pin, int val)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (val)
		out_be32((void *)GPIO0_OR + offs,
			 in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
	else
		out_be32((void *)GPIO0_OR + offs,
			 in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
}

int gpio_read_out_bit(int pin)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
}

int gpio_read_in_bit(int pin)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
}

#if defined(CFG_4xx_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
	unsigned char i=0, j=0, offs=0, gpio_core;
	unsigned long reg, core_add;

	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
		j = 0;
		offs = 0;
		/* GPIO config of the GPIOs 0 to 31 */
		for (i=0; i<GPIO_MAX; i++, j++) {
			if (i == GPIO_MAX/2) {
				offs = 4;
				j = i-16;
			}

			core_add = gpio_tab[gpio_core][i].add;

			if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					break;

				case GPIO_ALT1:
					reg = in_be32((void *)GPIO_IS1(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out_be32((void *)GPIO_IS1(core_add+offs), reg);
					break;

				case GPIO_ALT2:
					reg = in_be32((void *)GPIO_IS2(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out_be32((void *)GPIO_IS2(core_add+offs), reg);
					break;

				case GPIO_ALT3:
					reg = in_be32((void *)GPIO_IS3(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out_be32((void *)GPIO_IS3(core_add+offs), reg);
					break;
				}
			}

			if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				u32 gpio_alt_sel = 0;

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					/*
					 * Setup output value
					 * 1 -> high level
					 * 0 -> low level
					 * else -> don't touch
					 */
					reg = in_be32((void *)GPIO_OR(core_add));
					if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
						reg |= (0x80000000 >> (i));
					else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
						reg &= ~(0x80000000 >> (i));
					out_be32((void *)GPIO_OR(core_add), reg);

					reg = in_be32((void *)GPIO_TCR(core_add)) |
						(0x80000000 >> (i));
					out_be32((void *)GPIO_TCR(core_add), reg);

					reg = in_be32((void *)GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out_be32((void *)GPIO_OS(core_add+offs), reg);
					reg = in_be32((void *)GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out_be32((void *)GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT1:
					gpio_alt_sel = GPIO_ALT1_SEL;
					break;

				case GPIO_ALT2:
					gpio_alt_sel = GPIO_ALT2_SEL;
					break;

				case GPIO_ALT3:
					gpio_alt_sel = GPIO_ALT3_SEL;
					break;
				}

				if (0 != gpio_alt_sel) {
					reg = in_be32((void *)GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (gpio_alt_sel >> (j*2));
					out_be32((void *)GPIO_OS(core_add+offs), reg);

					if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
						reg = in_be32((void *)GPIO_TCR(core_add))
							| (0x80000000 >> (i));
						out_be32((void *)GPIO_TCR(core_add), reg);
						reg = in_be32((void *)GPIO_TS(core_add+offs))
							& ~(GPIO_MASK >> (j*2));
						out_be32((void *)GPIO_TS(core_add+offs), reg);
					} else {
						reg = in_be32((void *)GPIO_TCR(core_add))
							& ~(0x80000000 >> (i));
						out_be32((void *)GPIO_TCR(core_add), reg);
						reg = in_be32((void *)GPIO_TS(core_add+offs))
							& ~(GPIO_MASK >> (j*2));
						reg = reg | (gpio_alt_sel >> (j*2));
						out_be32((void *)GPIO_TS(core_add+offs), reg);
					}
				}
			}
		}
	}
}
#endif /* CFG_4xx_GPIO_TABLE */
Commit	Line	Data
3cb86f3e SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
	27	#include <asm/gpio.h>
	28
aee747f1	29	#if defined(CFG_4xx_GPIO_TABLE)
5ab884b2	30	gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
3cb86f3e SR	31	#endif
	32
	33	#if defined(GPIO0_OSRL)
	34	/* Only some 4xx variants support alternate funtions on the GPIO's */
	35	void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
	36	{
	37	u32 mask;
	38	u32 mask2;
	39	u32 val;
	40	u32 offs = 0;
	41	u32 offs2 = 0;
	42	int pin2 = pin << 1;
	43
	44	if (pin >= GPIO_MAX) {
	45	offs = 0x100;
	46	pin -= GPIO_MAX;
	47	}
	48
	49	if (pin >= GPIO_MAX/2) {
3b9abdc4	50	offs2 = 0x4;
3cb86f3e SR	51	pin2 = (pin - GPIO_MAX/2) << 1;
	52	}
	53
	54	mask = 0x80000000 >> pin;
	55	mask2 = 0xc0000000 >> (pin2 << 1);
	56
	57	/* first set TCR to 0 */
aee747f1	58	out_be32((void )GPIO0_TCR + offs, in_be32((void )GPIO0_TCR + offs) & ~mask);
3cb86f3e SR	59
3cb86f3e SR	60	if (in_out == GPIO_OUT) {
aee747f1	61	val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
3cb86f3e SR	62	switch (gpio_alt) {
	63	case GPIO_ALT1:
	64	val \|= GPIO_ALT1_SEL >> pin2;
	65	break;
	66	case GPIO_ALT2:
	67	val \|= GPIO_ALT2_SEL >> pin2;
	68	break;
	69	case GPIO_ALT3:
	70	val \|= GPIO_ALT3_SEL >> pin2;
	71	break;
	72	}
aee747f1	73	out_be32((void *)GPIO0_OSRL + offs + offs2, val);
3cb86f3e SR	74
	75	/* setup requested output value */
	76	if (out_val == GPIO_OUT_0)
aee747f1 SR	77	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	78	in_be32((void *)GPIO0_OR + offs) & ~mask);
3cb86f3e	79	else if (out_val == GPIO_OUT_1)
aee747f1 SR	80	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	81	in_be32((void *)GPIO0_OR + offs) \| mask);
3cb86f3e SR	82
3cb86f3e SR	83	/* now configure TCR to drive output if selected */
aee747f1 SR	84	out_be32((void *)GPIO0_TCR + offs,
aee747f1 SR	85	in_be32((void *)GPIO0_TCR + offs) \| mask);
3cb86f3e	86	} else {
aee747f1	87	val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
3cb86f3e	88	val \|= GPIO_IN_SEL >> pin2;
aee747f1	89	out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
3cb86f3e SR	90	}
	91	}
	92	#endif /* GPIO_OSRL */
	93
	94	void gpio_write_bit(int pin, int val)
	95	{
	96	u32 offs = 0;
	97
	98	if (pin >= GPIO_MAX) {
	99	offs = 0x100;
	100	pin -= GPIO_MAX;
	101	}
	102
	103	if (val)
aee747f1 SR	104	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	105	in_be32((void *)GPIO0_OR + offs) \| GPIO_VAL(pin));
3cb86f3e	106	else
aee747f1 SR	107	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	108	in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
3cb86f3e SR	109	}
3cb86f3e SR	110
85f73737 SR	111	int gpio_read_out_bit(int pin)
	112	{
	113	u32 offs = 0;
	114
	115	if (pin >= GPIO_MAX) {
	116	offs = 0x100;
	117	pin -= GPIO_MAX;
	118	}
	119
aee747f1	120	return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
85f73737 SR	121	}
85f73737 SR	122
5ab884b2 LJ	123	int gpio_read_in_bit(int pin)
	124	{
	125	u32 offs = 0;
	126
	127	if (pin >= GPIO_MAX) {
	128	offs = 0x100;
	129	pin -= GPIO_MAX;
	130	}
	131
	132	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
	133	}
	134
aee747f1	135	#if defined(CFG_4xx_GPIO_TABLE)
3cb86f3e SR	136	void gpio_set_chip_configuration(void)
	137	{
	138	unsigned char i=0, j=0, offs=0, gpio_core;
	139	unsigned long reg, core_add;
	140
	141	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
	142	j = 0;
	143	offs = 0;
	144	/* GPIO config of the GPIOs 0 to 31 */
	145	for (i=0; i<GPIO_MAX; i++, j++) {
	146	if (i == GPIO_MAX/2) {
	147	offs = 4;
	148	j = i-16;
	149	}
	150
	151	core_add = gpio_tab[gpio_core][i].add;
	152
	153	if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) \|\|
	154	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
	155
	156	switch (gpio_tab[gpio_core][i].alt_nb) {
	157	case GPIO_SEL:
	158	break;
	159
	160	case GPIO_ALT1:
aee747f1	161	reg = in_be32((void *)GPIO_IS1(core_add+offs))
3cb86f3e SR	162	& ~(GPIO_MASK >> (j*2));
3cb86f3e SR	163	reg = reg \| (GPIO_IN_SEL >> (j*2));
aee747f1	164	out_be32((void *)GPIO_IS1(core_add+offs), reg);
3cb86f3e SR	165	break;
	166
	167	case GPIO_ALT2:
aee747f1	168	reg = in_be32((void *)GPIO_IS2(core_add+offs))
3cb86f3e SR	169	& ~(GPIO_MASK >> (j*2));
3cb86f3e SR	170	reg = reg \| (GPIO_IN_SEL >> (j*2));
aee747f1	171	out_be32((void *)GPIO_IS2(core_add+offs), reg);
3cb86f3e SR	172	break;
	173
	174	case GPIO_ALT3:
aee747f1	175	reg = in_be32((void *)GPIO_IS3(core_add+offs))
3cb86f3e SR	176	& ~(GPIO_MASK >> (j*2));
3cb86f3e SR	177	reg = reg \| (GPIO_IN_SEL >> (j*2));
aee747f1	178	out_be32((void *)GPIO_IS3(core_add+offs), reg);
3cb86f3e SR	179	break;
	180	}
	181	}
	182
	183	if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) \|\|
	184	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
	185
5ab884b2 LJ	186	u32 gpio_alt_sel = 0;
5ab884b2 LJ	187
3cb86f3e SR	188	switch (gpio_tab[gpio_core][i].alt_nb) {
3cb86f3e SR	189	case GPIO_SEL:
aee747f1 SR	190	/*
	191	* Setup output value
	192	* 1 -> high level
	193	* 0 -> low level
	194	* else -> don't touch
	195	*/
	196	reg = in_be32((void *)GPIO_OR(core_add));
	197	if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
	198	reg \|= (0x80000000 >> (i));
	199	else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
	200	reg &= ~(0x80000000 >> (i));
	201	out_be32((void *)GPIO_OR(core_add), reg);
	202
	203	reg = in_be32((void *)GPIO_TCR(core_add)) \|
	204	(0x80000000 >> (i));
	205	out_be32((void *)GPIO_TCR(core_add), reg);
	206
	207	reg = in_be32((void *)GPIO_OS(core_add+offs))
3cb86f3e	208	& ~(GPIO_MASK >> (j*2));
aee747f1 SR	209	out_be32((void *)GPIO_OS(core_add+offs), reg);
aee747f1 SR	210	reg = in_be32((void *)GPIO_TS(core_add+offs))
3cb86f3e	211	& ~(GPIO_MASK >> (j*2));
aee747f1	212	out_be32((void *)GPIO_TS(core_add+offs), reg);
3cb86f3e SR	213	break;
	214
	215	case GPIO_ALT1:
5ab884b2	216	gpio_alt_sel = GPIO_ALT1_SEL;
3cb86f3e SR	217	break;
	218
	219	case GPIO_ALT2:
5ab884b2	220	gpio_alt_sel = GPIO_ALT2_SEL;
3cb86f3e SR	221	break;
	222
	223	case GPIO_ALT3:
5ab884b2 LJ	224	gpio_alt_sel = GPIO_ALT3_SEL;
	225	break;
	226	}
	227
	228	if (0 != gpio_alt_sel) {
aee747f1	229	reg = in_be32((void *)GPIO_OS(core_add+offs))
3cb86f3e	230	& ~(GPIO_MASK >> (j*2));
5ab884b2	231	reg = reg \| (gpio_alt_sel >> (j*2));
aee747f1	232	out_be32((void *)GPIO_OS(core_add+offs), reg);
5ab884b2 LJ	233
	234	if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
	235	reg = in_be32((void *)GPIO_TCR(core_add))
	236	\| (0x80000000 >> (i));
	237	out_be32((void *)GPIO_TCR(core_add), reg);
	238	reg = in_be32((void *)GPIO_TS(core_add+offs))
	239	& ~(GPIO_MASK >> (j*2));
	240	out_be32((void *)GPIO_TS(core_add+offs), reg);
	241	} else {
	242	reg = in_be32((void *)GPIO_TCR(core_add))
	243	& ~(0x80000000 >> (i));
	244	out_be32((void *)GPIO_TCR(core_add), reg);
	245	reg = in_be32((void *)GPIO_TS(core_add+offs))
	246	& ~(GPIO_MASK >> (j*2));
	247	reg = reg \| (gpio_alt_sel >> (j*2));
	248	out_be32((void *)GPIO_TS(core_add+offs), reg);
	249	}
3cb86f3e SR	250	}
	251	}
	252	}
	253	}
	254	}
aee747f1	255	#endif /* CFG_4xx_GPIO_TABLE */