[people/ms/u-boot.git] / drivers / i2c / tegra_i2c.c

/*
 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Copyright (c) 2010-2011 NVIDIA Corporation
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
#include <asm/io.h>
#include <clk.h>
#include <reset.h>
#ifndef CONFIG_TEGRA186
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#endif
#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>

DECLARE_GLOBAL_DATA_PTR;

enum i2c_type {
	TYPE_114,
	TYPE_STD,
	TYPE_DVC,
};

/* Information about i2c controller */
struct i2c_bus {
	int			id;
	struct reset_ctl	reset_ctl;
	struct clk		clk;
	int			speed;
	int			pinmux_config;
	struct i2c_control	*control;
	struct i2c_ctlr		*regs;
	enum i2c_type		type;
	int			inited;	/* bus is inited */
};

static void set_packet_mode(struct i2c_bus *i2c_bus)
{
	u32 config;

	config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;

	if (i2c_bus->type == TYPE_DVC) {
		struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;

		writel(config, &dvc->cnfg);
	} else {
		writel(config, &i2c_bus->regs->cnfg);
		/*
		 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
		 * issues, i.e., some slaves may be wrongly detected.
		 */
		setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
	}
}

static void i2c_reset_controller(struct i2c_bus *i2c_bus)
{
	/* Reset I2C controller. */
	reset_assert(&i2c_bus->reset_ctl);
	udelay(1);
	reset_deassert(&i2c_bus->reset_ctl);
	udelay(1);

	/* re-program config register to packet mode */
	set_packet_mode(i2c_bus);
}

static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
{
	int ret;

	ret = reset_assert(&i2c_bus->reset_ctl);
	if (ret)
		return ret;
	ret = clk_enable(&i2c_bus->clk);
	if (ret)
		return ret;
	ret = clk_set_rate(&i2c_bus->clk, rate);
	if (IS_ERR_VALUE(ret))
		return ret;
	ret = reset_deassert(&i2c_bus->reset_ctl);
	if (ret)
		return ret;

	return 0;
}

static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
	if (!i2c_bus->speed)
		return;
	debug("%s: speed=%d\n", __func__, i2c_bus->speed);
	/*
	 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
	 * here, in section 23.3.1, but in fact we seem to need a factor of
	 * 16 to get the right frequency.
	 */
	i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);

	if (i2c_bus->type == TYPE_114) {
		/*
		 * T114 I2C went to a single clock source for standard/fast and
		 * HS clock speeds. The new clock rate setting calculation is:
		 *  SCL = CLK_SOURCE.I2C /
		 *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
		 *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
		 *
		 * NOTE: We do this here, after the initial clock/pll start,
		 * because if we read the clk_div reg before the controller
		 * is running, we hang, and we need it for the new calc.
		 */
		int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
		unsigned rate = CLK_MULT_STD_FAST_MODE *
				(clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
		debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
			clk_div_stdfst_mode);

		i2c_init_clock(i2c_bus, rate);
	}

	/* Reset I2C controller. */
	i2c_reset_controller(i2c_bus);

	/* Configure I2C controller. */
	if (i2c_bus->type == TYPE_DVC) {	/* only for DVC I2C */
		struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;

		setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
	}

#ifndef CONFIG_TEGRA186
	funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
#endif
}

static void send_packet_headers(
	struct i2c_bus *i2c_bus,
	struct i2c_trans_info *trans,
	u32 packet_id,
	bool end_with_repeated_start)
{
	u32 data;

	/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
	data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
	data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
	data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 1 sent (0x%x)\n", data);

	/* prepare header2 */
	data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 2 sent (0x%x)\n", data);

	/* prepare IO specific header: configure the slave address */
	data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;

	/* Enable Read if it is not a write transaction */
	if (!(trans->flags & I2C_IS_WRITE))
		data |= PKT_HDR3_READ_MODE_MASK;
	if (end_with_repeated_start)
		data |= PKT_HDR3_REPEAT_START_MASK;

	/* Write I2C specific header */
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 3 sent (0x%x)\n", data);
}

static int wait_for_tx_fifo_empty(struct i2c_control *control)
{
	u32 count;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
				>> TX_FIFO_EMPTY_CNT_SHIFT;
		if (count == I2C_FIFO_DEPTH)
			return 1;
		udelay(10);
		timeout_us -= 10;
	}

	return 0;
}

static int wait_for_rx_fifo_notempty(struct i2c_control *control)
{
	u32 count;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
				>> TX_FIFO_FULL_CNT_SHIFT;
		if (count)
			return 1;
		udelay(10);
		timeout_us -= 10;
	}

	return 0;
}

static int wait_for_transfer_complete(struct i2c_control *control)
{
	int int_status;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		int_status = readl(&control->int_status);
		if (int_status & I2C_INT_NO_ACK_MASK)
			return -int_status;
		if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
			return -int_status;
		if (int_status & I2C_INT_XFER_COMPLETE_MASK)
			return 0;

		udelay(10);
		timeout_us -= 10;
	}

	return -1;
}

static int send_recv_packets(struct i2c_bus *i2c_bus,
			     struct i2c_trans_info *trans)
{
	struct i2c_control *control = i2c_bus->control;
	u32 int_status;
	u32 words;
	u8 *dptr;
	u32 local;
	uchar last_bytes;
	int error = 0;
	int is_write = trans->flags & I2C_IS_WRITE;

	/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
	int_status = readl(&control->int_status);
	writel(int_status, &control->int_status);

	send_packet_headers(i2c_bus, trans, 1,
			    trans->flags & I2C_USE_REPEATED_START);

	words = DIV_ROUND_UP(trans->num_bytes, 4);
	last_bytes = trans->num_bytes & 3;
	dptr = trans->buf;

	while (words) {
		u32 *wptr = (u32 *)dptr;

		if (is_write) {
			/* deal with word alignment */
			if ((words == 1) && last_bytes) {
				local = 0;
				memcpy(&local, dptr, last_bytes);
			} else if ((unsigned long)dptr & 3) {
				memcpy(&local, dptr, sizeof(u32));
			} else {
				local = *wptr;
			}
			writel(local, &control->tx_fifo);
			debug("pkt data sent (0x%x)\n", local);
			if (!wait_for_tx_fifo_empty(control)) {
				error = -1;
				goto exit;
			}
		} else {
			if (!wait_for_rx_fifo_notempty(control)) {
				error = -1;
				goto exit;
			}
			/*
			 * for the last word, we read into our local buffer,
			 * in case that caller did not provide enough buffer.
			 */
			local = readl(&control->rx_fifo);
			if ((words == 1) && last_bytes)
				memcpy(dptr, (char *)&local, last_bytes);
			else if ((unsigned long)dptr & 3)
				memcpy(dptr, &local, sizeof(u32));
			else
				*wptr = local;
			debug("pkt data received (0x%x)\n", local);
		}
		words--;
		dptr += sizeof(u32);
	}

	if (wait_for_transfer_complete(control)) {
		error = -1;
		goto exit;
	}
	return 0;
exit:
	/* error, reset the controller. */
	i2c_reset_controller(i2c_bus);

	return error;
}

static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
				u32 len, bool end_with_repeated_start)
{
	int error;
	struct i2c_trans_info trans_info;

	trans_info.address = addr;
	trans_info.buf = data;
	trans_info.flags = I2C_IS_WRITE;
	if (end_with_repeated_start)
		trans_info.flags |= I2C_USE_REPEATED_START;
	trans_info.num_bytes = len;
	trans_info.is_10bit_address = 0;

	error = send_recv_packets(i2c_bus, &trans_info);
	if (error)
		debug("tegra_i2c_write_data: Error (%d) !!!\n", error);

	return error;
}

static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
			       u32 len)
{
	int error;
	struct i2c_trans_info trans_info;

	trans_info.address = addr | 1;
	trans_info.buf = data;
	trans_info.flags = 0;
	trans_info.num_bytes = len;
	trans_info.is_10bit_address = 0;

	error = send_recv_packets(i2c_bus, &trans_info);
	if (error)
		debug("tegra_i2c_read_data: Error (%d) !!!\n", error);

	return error;
}

static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
	struct i2c_bus *i2c_bus = dev_get_priv(dev);

	i2c_bus->speed = speed;
	i2c_init_controller(i2c_bus);

	return 0;
}

static int tegra_i2c_probe(struct udevice *dev)
{
	struct i2c_bus *i2c_bus = dev_get_priv(dev);
	int ret;
	bool is_dvc;

	i2c_bus->id = dev->seq;
	i2c_bus->type = dev_get_driver_data(dev);
	i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
	if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
		debug("%s: Cannot get regs address\n", __func__);
		return -EINVAL;
	}

	ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
	if (ret) {
		pr_err("reset_get_by_name() failed: %d\n", ret);
		return ret;
	}
	ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
	if (ret) {
		pr_err("clk_get_by_name() failed: %d\n", ret);
		return ret;
	}

#ifndef CONFIG_TEGRA186
	/*
	 * We don't have a binding for pinmux yet. Leave it out for now. So
	 * far no one needs anything other than the default.
	 */
	i2c_bus->pinmux_config = FUNCMUX_DEFAULT;

	/*
	 * We can't specify the pinmux config in the fdt, so I2C2 will not
	 * work on Seaboard. It normally has no devices on it anyway.
	 * You could add in this little hack if you need to use it.
	 * The correct solution is a pinmux binding in the fdt.
	 *
	 *	if (i2c_bus->clk.id == PERIPH_ID_I2C2)
	 *		i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
	 */
#endif

	is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
	if (is_dvc) {
		i2c_bus->control =
			&((struct dvc_ctlr *)i2c_bus->regs)->control;
	} else {
		i2c_bus->control = &i2c_bus->regs->control;
	}
	i2c_init_controller(i2c_bus);
	debug("%s: controller bus %d at %p, speed %d: ",
	      is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);

	return 0;
}

/* i2c write version without the register address */
static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
			  int len, bool end_with_repeated_start)
{
	int rc;

	debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
	debug("write_data: ");
	/* use rc for counter */
	for (rc = 0; rc < len; ++rc)
		debug(" 0x%02x", buffer[rc]);
	debug("\n");

	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
				  end_with_repeated_start);
	if (rc)
		debug("i2c_write_data(): rc=%d\n", rc);

	return rc;
}

/* i2c read version without the register address */
static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
			 int len)
{
	int rc;

	debug("inside i2c_read_data():\n");
	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
	if (rc) {
		debug("i2c_read_data(): rc=%d\n", rc);
		return rc;
	}

	debug("i2c_read_data: ");
	/* reuse rc for counter*/
	for (rc = 0; rc < len; ++rc)
		debug(" 0x%02x", buffer[rc]);
	debug("\n");

	return 0;
}

/* Probe to see if a chip is present. */
static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				uint chip_flags)
{
	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	int rc;
	u8 reg;

	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
				  false);

	return rc;
}

static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			  int nmsgs)
{
	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);

		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
					    msg->len);
		} else {
			ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
					     msg->len, next_is_read);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return 0;
}

int tegra_i2c_get_dvc_bus(struct udevice **busp)
{
	struct udevice *bus;

	for (uclass_first_device(UCLASS_I2C, &bus);
	     bus;
	     uclass_next_device(&bus)) {
		if (dev_get_driver_data(bus) == TYPE_DVC) {
			*busp = bus;
			return 0;
		}
	}

	return -ENODEV;
}

static const struct dm_i2c_ops tegra_i2c_ops = {
	.xfer		= tegra_i2c_xfer,
	.probe_chip	= tegra_i2c_probe_chip,
	.set_bus_speed	= tegra_i2c_set_bus_speed,
};

static const struct udevice_id tegra_i2c_ids[] = {
	{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
	{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
	{ }
};

U_BOOT_DRIVER(i2c_tegra) = {
	.name	= "i2c_tegra",
	.id	= UCLASS_I2C,
	.of_match = tegra_i2c_ids,
	.probe	= tegra_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct i2c_bus),
	.ops	= &tegra_i2c_ops,
};
Commit	Line	Data
96a78ac0 YL	1	/*
	2	* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
	3	* Copyright (c) 2010-2011 NVIDIA Corporation
	4	* NVIDIA Corporation <www.nvidia.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
96a78ac0 YL	7	*/
	8
	9	#include <common.h>
b0e6ef46 SG	10	#include <dm.h>
b0e6ef46 SG	11	#include <errno.h>
96a78ac0 YL	12	#include <i2c.h>
96a78ac0 YL	13	#include <asm/io.h>
3c27fa21 BW	14	#include <clk.h>
3c27fa21 BW	15	#include <reset.h>
fc607d9a	16	#ifndef CONFIG_TEGRA186
96a78ac0 YL	17	#include <asm/arch/clock.h>
96a78ac0 YL	18	#include <asm/arch/funcmux.h>
3c27fa21 BW	19	#endif
3c27fa21 BW	20	#include <asm/arch/gpio.h>
150c2493	21	#include <asm/arch-tegra/tegra_i2c.h>
96a78ac0 YL	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
b0e6ef46 SG	25	enum i2c_type {
	26	TYPE_114,
	27	TYPE_STD,
	28	TYPE_DVC,
	29	};
	30
96a78ac0 YL	31	/* Information about i2c controller */
	32	struct i2c_bus {
	33	int id;
3c27fa21 BW	34	struct reset_ctl reset_ctl;
3c27fa21 BW	35	struct clk clk;
96a78ac0 YL	36	int speed;
	37	int pinmux_config;
	38	struct i2c_control *control;
	39	struct i2c_ctlr *regs;
b0e6ef46	40	enum i2c_type type;
96a78ac0 YL	41	int inited; /* bus is inited */
	42	};
	43
96a78ac0 YL	44	static void set_packet_mode(struct i2c_bus *i2c_bus)
	45	{
	46	u32 config;
	47
	48	config = I2C_CNFG_NEW_MASTER_FSM_MASK \| I2C_CNFG_PACKET_MODE_MASK;
	49
b0e6ef46	50	if (i2c_bus->type == TYPE_DVC) {
96a78ac0 YL	51	struct dvc_ctlr dvc = (struct dvc_ctlr )i2c_bus->regs;
	52
	53	writel(config, &dvc->cnfg);
	54	} else {
	55	writel(config, &i2c_bus->regs->cnfg);
	56	/*
	57	* program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
	58	* issues, i.e., some slaves may be wrongly detected.
	59	*/
	60	setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
	61	}
	62	}
	63
	64	static void i2c_reset_controller(struct i2c_bus *i2c_bus)
	65	{
	66	/* Reset I2C controller. */
3c27fa21 BW	67	reset_assert(&i2c_bus->reset_ctl);
	68	udelay(1);
	69	reset_deassert(&i2c_bus->reset_ctl);
	70	udelay(1);
96a78ac0 YL	71
	72	/* re-program config register to packet mode */
	73	set_packet_mode(i2c_bus);
	74	}
	75
3c27fa21 BW	76	static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
	77	{
	78	int ret;
	79
	80	ret = reset_assert(&i2c_bus->reset_ctl);
	81	if (ret)
	82	return ret;
	83	ret = clk_enable(&i2c_bus->clk);
	84	if (ret)
	85	return ret;
	86	ret = clk_set_rate(&i2c_bus->clk, rate);
	87	if (IS_ERR_VALUE(ret))
	88	return ret;
	89	ret = reset_deassert(&i2c_bus->reset_ctl);
	90	if (ret)
	91	return ret;
	92
	93	return 0;
	94	}
3c27fa21	95
96a78ac0 YL	96	static void i2c_init_controller(struct i2c_bus *i2c_bus)
96a78ac0 YL	97	{
b0e6ef46 SG	98	if (!i2c_bus->speed)
	99	return;
	100	debug("%s: speed=%d\n", __func__, i2c_bus->speed);
96a78ac0 YL	101	/*
	102	* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
	103	* here, in section 23.3.1, but in fact we seem to need a factor of
	104	* 16 to get the right frequency.
	105	*/
3c27fa21	106	i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
e32624ef	107
b0e6ef46	108	if (i2c_bus->type == TYPE_114) {
e32624ef TW	109	/*
	110	* T114 I2C went to a single clock source for standard/fast and
	111	* HS clock speeds. The new clock rate setting calculation is:
	112	* SCL = CLK_SOURCE.I2C /
	113	* (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
	114	* I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
	115	*
	116	* NOTE: We do this here, after the initial clock/pll start,
	117	* because if we read the clk_div reg before the controller
	118	* is running, we hang, and we need it for the new calc.
	119	*/
	120	int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
3c27fa21 BW	121	unsigned rate = CLK_MULT_STD_FAST_MODE *
3c27fa21 BW	122	(clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
e32624ef TW	123	debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
	124	clk_div_stdfst_mode);
	125
3c27fa21	126	i2c_init_clock(i2c_bus, rate);
e32624ef	127	}
96a78ac0 YL	128
	129	/* Reset I2C controller. */
	130	i2c_reset_controller(i2c_bus);
	131
	132	/* Configure I2C controller. */
b0e6ef46	133	if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
96a78ac0 YL	134	struct dvc_ctlr dvc = (struct dvc_ctlr )i2c_bus->regs;
	135
	136	setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
	137	}
	138
3c27fa21	139	#ifndef CONFIG_TEGRA186
fc607d9a	140	funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
3c27fa21	141	#endif
96a78ac0 YL	142	}
	143
	144	static void send_packet_headers(
	145	struct i2c_bus *i2c_bus,
	146	struct i2c_trans_info *trans,
68049a08 SW	147	u32 packet_id,
68049a08 SW	148	bool end_with_repeated_start)
96a78ac0 YL	149	{
	150	u32 data;
	151
	152	/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
	153	data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
	154	data \|= packet_id << PKT_HDR1_PKT_ID_SHIFT;
	155	data \|= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
	156	writel(data, &i2c_bus->control->tx_fifo);
	157	debug("pkt header 1 sent (0x%x)\n", data);
	158
	159	/* prepare header2 */
	160	data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
	161	writel(data, &i2c_bus->control->tx_fifo);
	162	debug("pkt header 2 sent (0x%x)\n", data);
	163
	164	/* prepare IO specific header: configure the slave address */
	165	data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
	166
	167	/* Enable Read if it is not a write transaction */
	168	if (!(trans->flags & I2C_IS_WRITE))
	169	data \|= PKT_HDR3_READ_MODE_MASK;
68049a08 SW	170	if (end_with_repeated_start)
68049a08 SW	171	data \|= PKT_HDR3_REPEAT_START_MASK;
96a78ac0 YL	172
	173	/* Write I2C specific header */
	174	writel(data, &i2c_bus->control->tx_fifo);
	175	debug("pkt header 3 sent (0x%x)\n", data);
	176	}
	177
	178	static int wait_for_tx_fifo_empty(struct i2c_control *control)
	179	{
	180	u32 count;
	181	int timeout_us = I2C_TIMEOUT_USEC;
	182
	183	while (timeout_us >= 0) {
	184	count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
	185	>> TX_FIFO_EMPTY_CNT_SHIFT;
	186	if (count == I2C_FIFO_DEPTH)
	187	return 1;
	188	udelay(10);
	189	timeout_us -= 10;
	190	}
	191
	192	return 0;
	193	}
	194
	195	static int wait_for_rx_fifo_notempty(struct i2c_control *control)
	196	{
	197	u32 count;
	198	int timeout_us = I2C_TIMEOUT_USEC;
	199
	200	while (timeout_us >= 0) {
	201	count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
	202	>> TX_FIFO_FULL_CNT_SHIFT;
	203	if (count)
	204	return 1;
	205	udelay(10);
	206	timeout_us -= 10;
	207	}
	208
	209	return 0;
	210	}
	211
	212	static int wait_for_transfer_complete(struct i2c_control *control)
	213	{
	214	int int_status;
	215	int timeout_us = I2C_TIMEOUT_USEC;
	216
	217	while (timeout_us >= 0) {
	218	int_status = readl(&control->int_status);
	219	if (int_status & I2C_INT_NO_ACK_MASK)
	220	return -int_status;
	221	if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
	222	return -int_status;
	223	if (int_status & I2C_INT_XFER_COMPLETE_MASK)
	224	return 0;
	225
	226	udelay(10);
	227	timeout_us -= 10;
	228	}
	229
	230	return -1;
	231	}
	232
	233	static int send_recv_packets(struct i2c_bus *i2c_bus,
	234	struct i2c_trans_info *trans)
	235	{
236	struct i2c_control *control = i2c_bus->control;
237	u32 int_status;
238	u32 words;
239	u8 *dptr;
240	u32 local;
241	uchar last_bytes;
242	int error = 0;
243	int is_write = trans->flags & I2C_IS_WRITE;
244
245	/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
246	int_status = readl(&control->int_status);
247	writel(int_status, &control->int_status);
248
68049a08 SW	249	send_packet_headers(i2c_bus, trans, 1,
68049a08 SW	250	trans->flags & I2C_USE_REPEATED_START);
96a78ac0 YL	251
	252	words = DIV_ROUND_UP(trans->num_bytes, 4);
	253	last_bytes = trans->num_bytes & 3;
	254	dptr = trans->buf;
	255
	256	while (words) {
	257	u32 wptr = (u32 )dptr;
	258
	259	if (is_write) {
	260	/* deal with word alignment */
981b14f0 SW	261	if ((words == 1) && last_bytes) {
	262	local = 0;
	263	memcpy(&local, dptr, last_bytes);
8e67c5d0	264	} else if ((unsigned long)dptr & 3) {
96a78ac0	265	memcpy(&local, dptr, sizeof(u32));
96a78ac0	266	} else {
981b14f0	267	local = *wptr;
96a78ac0	268	}
981b14f0 SW	269	writel(local, &control->tx_fifo);
981b14f0 SW	270	debug("pkt data sent (0x%x)\n", local);
96a78ac0 YL	271	if (!wait_for_tx_fifo_empty(control)) {
	272	error = -1;
	273	goto exit;
	274	}
	275	} else {
	276	if (!wait_for_rx_fifo_notempty(control)) {
	277	error = -1;
	278	goto exit;
	279	}
	280	/*
	281	* for the last word, we read into our local buffer,
	282	* in case that caller did not provide enough buffer.
	283	*/
	284	local = readl(&control->rx_fifo);
	285	if ((words == 1) && last_bytes)
	286	memcpy(dptr, (char *)&local, last_bytes);
8e67c5d0	287	else if ((unsigned long)dptr & 3)
96a78ac0 YL	288	memcpy(dptr, &local, sizeof(u32));
	289	else
	290	*wptr = local;
	291	debug("pkt data received (0x%x)\n", local);
	292	}
	293	words--;
	294	dptr += sizeof(u32);
	295	}
	296
	297	if (wait_for_transfer_complete(control)) {
	298	error = -1;
	299	goto exit;
	300	}
	301	return 0;
	302	exit:
	303	/* error, reset the controller. */
	304	i2c_reset_controller(i2c_bus);
	305
	306	return error;
	307	}
	308
b0e6ef46	309	static int tegra_i2c_write_data(struct i2c_bus i2c_bus, u32 addr, u8 data,
68049a08	310	u32 len, bool end_with_repeated_start)
96a78ac0 YL	311	{
	312	int error;
	313	struct i2c_trans_info trans_info;
	314
	315	trans_info.address = addr;
	316	trans_info.buf = data;
	317	trans_info.flags = I2C_IS_WRITE;
68049a08 SW	318	if (end_with_repeated_start)
68049a08 SW	319	trans_info.flags \|= I2C_USE_REPEATED_START;
96a78ac0 YL	320	trans_info.num_bytes = len;
	321	trans_info.is_10bit_address = 0;
	322
b0e6ef46	323	error = send_recv_packets(i2c_bus, &trans_info);
96a78ac0	324	if (error)
29f3e3f2	325	debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
96a78ac0 YL	326
	327	return error;
	328	}
	329
b0e6ef46	330	static int tegra_i2c_read_data(struct i2c_bus i2c_bus, u32 addr, u8 data,
d84eb856	331	u32 len)
96a78ac0 YL	332	{
	333	int error;
	334	struct i2c_trans_info trans_info;
	335
	336	trans_info.address = addr \| 1;
	337	trans_info.buf = data;
	338	trans_info.flags = 0;
	339	trans_info.num_bytes = len;
	340	trans_info.is_10bit_address = 0;
	341
b0e6ef46	342	error = send_recv_packets(i2c_bus, &trans_info);
96a78ac0	343	if (error)
29f3e3f2	344	debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
96a78ac0 YL	345
	346	return error;
	347	}
	348
b0e6ef46	349	static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
96a78ac0	350	{
b0e6ef46	351	struct i2c_bus *i2c_bus = dev_get_priv(dev);
d84eb856	352
b0e6ef46 SG	353	i2c_bus->speed = speed;
b0e6ef46 SG	354	i2c_init_controller(i2c_bus);
96a78ac0 YL	355
	356	return 0;
	357	}
	358
b0e6ef46	359	static int tegra_i2c_probe(struct udevice *dev)
96a78ac0	360	{
b0e6ef46	361	struct i2c_bus *i2c_bus = dev_get_priv(dev);
3c27fa21	362	int ret;
b0e6ef46 SG	363	bool is_dvc;
	364
	365	i2c_bus->id = dev->seq;
39de8433	366	i2c_bus->type = dev_get_driver_data(dev);
d8554d08 SG	367	i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
	368	if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
	369	debug("%s: Cannot get regs address\n", __func__);
	370	return -EINVAL;
	371	}
96a78ac0	372
3c27fa21 BW	373	ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
3c27fa21 BW	374	if (ret) {
9b643e31	375	pr_err("reset_get_by_name() failed: %d\n", ret);
3c27fa21 BW	376	return ret;
3c27fa21 BW	377	}
b4ee081e	378	ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
3c27fa21	379	if (ret) {
9b643e31	380	pr_err("clk_get_by_name() failed: %d\n", ret);
3c27fa21 BW	381	return ret;
3c27fa21 BW	382	}
fc607d9a SW	383
	384	#ifndef CONFIG_TEGRA186
	385	/*
	386	* We don't have a binding for pinmux yet. Leave it out for now. So
	387	* far no one needs anything other than the default.
	388	*/
96a78ac0	389	i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
96a78ac0 YL	390
	391	/*
	392	* We can't specify the pinmux config in the fdt, so I2C2 will not
	393	* work on Seaboard. It normally has no devices on it anyway.
	394	* You could add in this little hack if you need to use it.
	395	* The correct solution is a pinmux binding in the fdt.
	396	*
fc607d9a	397	* if (i2c_bus->clk.id == PERIPH_ID_I2C2)
96a78ac0 YL	398	* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
96a78ac0 YL	399	*/
3c27fa21	400	#endif
96a78ac0	401
39de8433	402	is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
b0e6ef46 SG	403	if (is_dvc) {
	404	i2c_bus->control =
	405	&((struct dvc_ctlr *)i2c_bus->regs)->control;
	406	} else {
	407	i2c_bus->control = &i2c_bus->regs->control;
96a78ac0	408	}
b0e6ef46	409	i2c_init_controller(i2c_bus);
fc607d9a SW	410	debug("%s: controller bus %d at %p, speed %d: ",
fc607d9a SW	411	is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
96a78ac0 YL	412
	413	return 0;
	414	}
	415
96a78ac0	416	/* i2c write version without the register address */
b0e6ef46	417	static int i2c_write_data(struct i2c_bus i2c_bus, uchar chip, uchar buffer,
19d7bf3d	418	int len, bool end_with_repeated_start)
96a78ac0 YL	419	{
	420	int rc;
	421
	422	debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
	423	debug("write_data: ");
	424	/* use rc for counter */
	425	for (rc = 0; rc < len; ++rc)
	426	debug(" 0x%02x", buffer[rc]);
	427	debug("\n");
	428
	429	/* Shift 7-bit address over for lower-level i2c functions */
b0e6ef46	430	rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
68049a08	431	end_with_repeated_start);
96a78ac0 YL	432	if (rc)
	433	debug("i2c_write_data(): rc=%d\n", rc);
	434
	435	return rc;
	436	}
	437
	438	/* i2c read version without the register address */
b0e6ef46 SG	439	static int i2c_read_data(struct i2c_bus i2c_bus, uchar chip, uchar buffer,
b0e6ef46 SG	440	int len)
96a78ac0 YL	441	{
	442	int rc;
	443
	444	debug("inside i2c_read_data():\n");
	445	/* Shift 7-bit address over for lower-level i2c functions */
b0e6ef46	446	rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
96a78ac0 YL	447	if (rc) {
	448	debug("i2c_read_data(): rc=%d\n", rc);
	449	return rc;
	450	}
	451
	452	debug("i2c_read_data: ");
	453	/* reuse rc for counter*/
	454	for (rc = 0; rc < len; ++rc)
	455	debug(" 0x%02x", buffer[rc]);
	456	debug("\n");
	457
	458	return 0;
	459	}
	460
	461	/* Probe to see if a chip is present. */
b0e6ef46 SG	462	static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
b0e6ef46 SG	463	uint chip_flags)
96a78ac0	464	{
b0e6ef46	465	struct i2c_bus *i2c_bus = dev_get_priv(bus);
96a78ac0	466	int rc;
b0e6ef46	467	u8 reg;
96a78ac0	468
b0e6ef46 SG	469	/* Shift 7-bit address over for lower-level i2c functions */
	470	rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
	471	false);
	472
	473	return rc;
96a78ac0 YL	474	}
96a78ac0 YL	475
b0e6ef46 SG	476	static int tegra_i2c_xfer(struct udevice bus, struct i2c_msg msg,
b0e6ef46 SG	477	int nmsgs)
96a78ac0	478	{
b0e6ef46 SG	479	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	480	int ret;
	481
	482	debug("i2c_xfer: %d messages\n", nmsgs);
	483	for (; nmsgs > 0; nmsgs--, msg++) {
	484	bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
	485
	486	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	487	if (msg->flags & I2C_M_RD) {
	488	ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
	489	msg->len);
	490	} else {
	491	ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
	492	msg->len, next_is_read);
96a78ac0	493	}
b0e6ef46 SG	494	if (ret) {
	495	debug("i2c_write: error sending\n");
	496	return -EREMOTEIO;
96a78ac0 YL	497	}
	498	}
	499
	500	return 0;
	501	}
	502
b0e6ef46	503	int tegra_i2c_get_dvc_bus(struct udevice **busp)
96a78ac0	504	{
b0e6ef46 SG	505	struct udevice *bus;
	506
	507	for (uclass_first_device(UCLASS_I2C, &bus);
	508	bus;
	509	uclass_next_device(&bus)) {
39de8433	510	if (dev_get_driver_data(bus) == TYPE_DVC) {
b0e6ef46 SG	511	*busp = bus;
b0e6ef46 SG	512	return 0;
96a78ac0 YL	513	}
	514	}
	515
b0e6ef46	516	return -ENODEV;
96a78ac0 YL	517	}
96a78ac0 YL	518
b0e6ef46 SG	519	static const struct dm_i2c_ops tegra_i2c_ops = {
	520	.xfer = tegra_i2c_xfer,
	521	.probe_chip = tegra_i2c_probe_chip,
	522	.set_bus_speed = tegra_i2c_set_bus_speed,
	523	};
e31c1e50	524
b0e6ef46 SG	525	static const struct udevice_id tegra_i2c_ids[] = {
	526	{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
	527	{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
	528	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
	529	{ }
	530	};
	531
	532	U_BOOT_DRIVER(i2c_tegra) = {
	533	.name = "i2c_tegra",
	534	.id = UCLASS_I2C,
	535	.of_match = tegra_i2c_ids,
b0e6ef46	536	.probe = tegra_i2c_probe,
b0e6ef46 SG	537	.priv_auto_alloc_size = sizeof(struct i2c_bus),
	538	.ops = &tegra_i2c_ops,
	539	};