[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 * Sukumar Ghorai <s-ghorai@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation's version 2 of
 * the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>

/* common definitions for all OMAPs */
#define SYSCTL_SRC	(1 << 25)
#define SYSCTL_SRD	(1 << 26)

/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS	1000

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
			unsigned int siz);
static struct mmc hsmmc_dev[2];

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap4_sys_ctrl_regs *const ctrl =
		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;


	value = readl(&ctrl->control_pbiaslite);
	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
	writel(value, &ctrl->control_pbiaslite);
	/* set VMMC to 3V */
	twl6030_power_mmc_init();
	value = readl(&ctrl->control_pbiaslite);
	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
	writel(value, &ctrl->control_pbiaslite);
}
#endif

unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
	t2_t *t2_base = (t2_t *)T2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	u32 pbias_lite;

	pbias_lite = readl(&t2_base->pbias_lite);
	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
	writel(pbias_lite, &t2_base->pbias_lite);
#endif
#if defined(CONFIG_TWL4030_POWER)
	twl4030_power_mmc_init();
	mdelay(100);	/* ramp-up delay from Linux code */
#endif
#if defined(CONFIG_OMAP34XX)
	writel(pbias_lite | PBIASLITEPWRDNZ1 |
		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
		&t2_base->pbias_lite);

	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
		&t2_base->devconf0);

	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
		&t2_base->devconf1);

	writel(readl(&prcm_base->fclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->fclken1_core);

	writel(readl(&prcm_base->iclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->iclken1_core);
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	/* PBIAS config needed for MMC1 only */
	if (mmc->block_dev.dev == 0)
		omap4_vmmc_pbias_config(mmc);
#endif

	return 0;
}

void mmc_init_stream(struct hsmmc *mmc_base)
{
	ulong start;

	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);

	writel(MMC_CMD0, &mmc_base->cmd);
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc!\n", __func__);
			return;
		}
	}
	writel(CC_MASK, &mmc_base->stat)
		;
	writel(MMC_CMD0, &mmc_base->cmd)
		;
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}


static int mmc_init_setup(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int reg_val;
	unsigned int dsor;
	ulong start;

	mmc_board_init(mmc);

	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
		&mmc_base->sysconfig);
	start = get_timer(0);
	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for softresetall!\n",
				__func__);
			return TIMEOUT;
		}
	}
	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
		&mmc_base->capa);

	reg_val = readl(&mmc_base->con) & RESERVED_MASK;

	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);

	dsor = 240;
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);

	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);

	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
		&mmc_base->ie);

	mmc_init_stream(mmc_base);

	return 0;
}

/*
 * MMC controller internal finite state machine reset
 *
 * Used to reset command or data internal state machines, using respectively
 * SRC or SRD bit of SYSCTL register
 */
static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
{
	ulong start;

	mmc_reg_out(&mmc_base->sysctl, bit, bit);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & bit) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for sysctl %x to clear\n",
				__func__, bit);
			return;
		}
	}
}

static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			struct mmc_data *data)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int flags, mmc_stat;
	ulong start;

	start = get_timer(0);
	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting on cmd inhibit to clear\n",
					__func__);
			return TIMEOUT;
		}
	}
	writel(0xFFFFFFFF, &mmc_base->stat);
	start = get_timer(0);
	while (readl(&mmc_base->stat)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for STAT (%x) to clear\n",
				__func__, readl(&mmc_base->stat));
			return TIMEOUT;
		}
	}
	/*
	 * CMDREG
	 * CMDIDX[13:8]	: Command index
	 * DATAPRNT[5]	: Data Present Select
	 * ENCMDIDX[4]	: Command Index Check Enable
	 * ENCMDCRC[3]	: Command CRC Check Enable
	 * RSPTYP[1:0]
	 *	00 = No Response
	 *	01 = Length 136
	 *	10 = Length 48
	 *	11 = Length 48 Check busy after response
	 */
	/* Delay added before checking the status of frq change
	 * retry not supported by mmc.c(core file)
	 */
	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
		udelay(50000); /* wait 50 ms */

	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = 0;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		flags = RSP_TYPE_LGHT48B;
	else
		flags = RSP_TYPE_LGHT48;

	/* enable default flags */
	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= CCCE_CHECK;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= CICE_CHECK;

	if (data) {
		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
			data->blocksize = 512;
			writel(data->blocksize | (data->blocks << 16),
							&mmc_base->blk);
		} else
			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

		if (data->flags & MMC_DATA_READ)
			flags |= (DP_DATA | DDIR_READ);
		else
			flags |= (DP_DATA | DDIR_WRITE);
	}

	writel(cmd->cmdarg, &mmc_base->arg);
	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

	start = get_timer(0);
	do {
		mmc_stat = readl(&mmc_base->stat);
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s : timeout: No status update\n", __func__);
			return TIMEOUT;
		}
	} while (!mmc_stat);

	if ((mmc_stat & IE_CTO) != 0) {
		mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
		return TIMEOUT;
	} else if ((mmc_stat & ERRI_MASK) != 0)
		return -1;

	if (mmc_stat & CC_MASK) {
		writel(CC_MASK, &mmc_base->stat);
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (cmd->resp_type & MMC_RSP_136) {
				/* response type 2 */
				cmd->response[3] = readl(&mmc_base->rsp10);
				cmd->response[2] = readl(&mmc_base->rsp32);
				cmd->response[1] = readl(&mmc_base->rsp54);
				cmd->response[0] = readl(&mmc_base->rsp76);
			} else
				/* response types 1, 1b, 3, 4, 5, 6 */
				cmd->response[0] = readl(&mmc_base->rsp10);
		}
	}

	if (data && (data->flags & MMC_DATA_READ)) {
		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void mmc_set_ios(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int dsor = 0;
	ulong start;

	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	/* configure clock with 96Mhz system clock.
	 */
	if (mmc->clock != 0) {
		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
			dsor++;
	}

	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

int omap_mmc_init(int dev_index)
{
	struct mmc *mmc;

	mmc = &hsmmc_dev[dev_index];

	sprintf(mmc->name, "OMAP SD/MMC");
	mmc->send_cmd = mmc_send_cmd;
	mmc->set_ios = mmc_set_ios;
	mmc->init = mmc_init_setup;
	mmc->getcd = NULL;

	switch (dev_index) {
	case 0:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
		break;
#endif
	default:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
				MMC_MODE_HC;

	mmc->f_min = 400000;
	mmc->f_max = 52000000;

	mmc->b_max = 0;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		mmc->b_max = 1;
#endif

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
de941241 SG	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	* Sukumar Ghorai <s-ghorai@ti.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation's version 2 of
	12	* the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <common.h>
	27	#include <mmc.h>
	28	#include <part.h>
	29	#include <i2c.h>
	30	#include <twl4030.h>
14fa2dd0	31	#include <twl6030.h>
de941241 SG	32	#include <asm/io.h>
de941241 SG	33	#include <asm/arch/mmc_host_def.h>
96e0e7b3	34	#include <asm/arch/sys_proto.h>
de941241	35
25c719e2 GI	36	/* common definitions for all OMAPs */
	37	#define SYSCTL_SRC (1 << 25)
	38	#define SYSCTL_SRD (1 << 26)
	39
eb9a28f6 NM	40	/* If we fail after 1 second wait, something is really bad */
	41	#define MAX_RETRY_MS 1000
	42
933efe64 S	43	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size);
	44	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
	45	unsigned int siz);
de941241	46	static struct mmc hsmmc_dev[2];
14fa2dd0 B	47
	48	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	49	static void omap4_vmmc_pbias_config(struct mmc *mmc)
	50	{
	51	u32 value = 0;
	52	struct omap4_sys_ctrl_regs *const ctrl =
	53	(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
	54
	55
	56	value = readl(&ctrl->control_pbiaslite);
	57	value &= ~(MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ);
	58	writel(value, &ctrl->control_pbiaslite);
	59	/* set VMMC to 3V */
	60	twl6030_power_mmc_init();
	61	value = readl(&ctrl->control_pbiaslite);
	62	value \|= MMC1_PBIASLITE_VMODE \| MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ;
	63	writel(value, &ctrl->control_pbiaslite);
	64	}
	65	#endif
	66
	67	unsigned char mmc_board_init(struct mmc *mmc)
de941241	68	{
de941241 SG	69	#if defined(CONFIG_OMAP34XX)
	70	t2_t t2_base = (t2_t )T2_BASE;
	71	struct prcm prcm_base = (struct prcm )PRCM_BASE;
b1e725f2	72	u32 pbias_lite;
de941241	73
b1e725f2 GI	74	pbias_lite = readl(&t2_base->pbias_lite);
	75	pbias_lite &= ~(PBIASLITEPWRDNZ1 \| PBIASLITEPWRDNZ0);
	76	writel(pbias_lite, &t2_base->pbias_lite);
	77	#endif
	78	#if defined(CONFIG_TWL4030_POWER)
	79	twl4030_power_mmc_init();
	80	mdelay(100); /* ramp-up delay from Linux code */
	81	#endif
	82	#if defined(CONFIG_OMAP34XX)
	83	writel(pbias_lite \| PBIASLITEPWRDNZ1 \|
de941241 SG	84	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
	85	&t2_base->pbias_lite);
	86
	87	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
	88	&t2_base->devconf0);
	89
	90	writel(readl(&t2_base->devconf1) \| MMCSDIO2ADPCLKISEL,
	91	&t2_base->devconf1);
	92
	93	writel(readl(&prcm_base->fclken1_core) \|
	94	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	95	&prcm_base->fclken1_core);
	96
	97	writel(readl(&prcm_base->iclken1_core) \|
	98	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	99	&prcm_base->iclken1_core);
	100	#endif
	101
14fa2dd0 B	102	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	103	/* PBIAS config needed for MMC1 only */
	104	if (mmc->block_dev.dev == 0)
	105	omap4_vmmc_pbias_config(mmc);
	106	#endif
de941241 SG	107
	108	return 0;
	109	}
	110
933efe64	111	void mmc_init_stream(struct hsmmc *mmc_base)
de941241	112	{
eb9a28f6	113	ulong start;
de941241 SG	114
	115	writel(readl(&mmc_base->con) \| INIT_INITSTREAM, &mmc_base->con);
	116
	117	writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6 NM	118	start = get_timer(0);
	119	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	120	if (get_timer(0) - start > MAX_RETRY_MS) {
	121	printf("%s: timedout waiting for cc!\n", __func__);
	122	return;
	123	}
	124	}
de941241 SG	125	writel(CC_MASK, &mmc_base->stat)
	126	;
	127	writel(MMC_CMD0, &mmc_base->cmd)
	128	;
eb9a28f6 NM	129	start = get_timer(0);
	130	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	131	if (get_timer(0) - start > MAX_RETRY_MS) {
	132	printf("%s: timedout waiting for cc2!\n", __func__);
	133	return;
	134	}
	135	}
de941241 SG	136	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
	137	}
	138
	139
	140	static int mmc_init_setup(struct mmc *mmc)
	141	{
933efe64	142	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241 SG	143	unsigned int reg_val;
de941241 SG	144	unsigned int dsor;
eb9a28f6	145	ulong start;
de941241	146
14fa2dd0	147	mmc_board_init(mmc);
de941241 SG	148
	149	writel(readl(&mmc_base->sysconfig) \| MMC_SOFTRESET,
	150	&mmc_base->sysconfig);
eb9a28f6 NM	151	start = get_timer(0);
	152	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
	153	if (get_timer(0) - start > MAX_RETRY_MS) {
	154	printf("%s: timedout waiting for cc2!\n", __func__);
	155	return TIMEOUT;
	156	}
	157	}
de941241	158	writel(readl(&mmc_base->sysctl) \| SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6 NM	159	start = get_timer(0);
	160	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
	161	if (get_timer(0) - start > MAX_RETRY_MS) {
	162	printf("%s: timedout waiting for softresetall!\n",
	163	__func__);
	164	return TIMEOUT;
	165	}
	166	}
de941241 SG	167	writel(DTW_1_BITMODE \| SDBP_PWROFF \| SDVS_3V0, &mmc_base->hctl);
	168	writel(readl(&mmc_base->capa) \| VS30_3V0SUP \| VS18_1V8SUP,
	169	&mmc_base->capa);
	170
	171	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
	172
	173	writel(CTPL_MMC_SD \| reg_val \| WPP_ACTIVEHIGH \| CDP_ACTIVEHIGH \|
	174	MIT_CTO \| DW8_1_4BITMODE \| MODE_FUNC \| STR_BLOCK \|
	175	HR_NOHOSTRESP \| INIT_NOINIT \| NOOPENDRAIN, &mmc_base->con);
	176
	177	dsor = 240;
	178	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	179	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	180	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	181	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
eb9a28f6 NM	182	start = get_timer(0);
	183	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	184	if (get_timer(0) - start > MAX_RETRY_MS) {
	185	printf("%s: timedout waiting for ics!\n", __func__);
	186	return TIMEOUT;
	187	}
	188	}
de941241 SG	189	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	190
	191	writel(readl(&mmc_base->hctl) \| SDBP_PWRON, &mmc_base->hctl);
	192
	193	writel(IE_BADA \| IE_CERR \| IE_DEB \| IE_DCRC \| IE_DTO \| IE_CIE \|
	194	IE_CEB \| IE_CCRC \| IE_CTO \| IE_BRR \| IE_BWR \| IE_TC \| IE_CC,
	195	&mmc_base->ie);
	196
	197	mmc_init_stream(mmc_base);
	198
	199	return 0;
	200	}
	201
25c719e2 GI	202	/*
	203	* MMC controller internal finite state machine reset
	204	*
	205	* Used to reset command or data internal state machines, using respectively
	206	* SRC or SRD bit of SYSCTL register
	207	*/
	208	static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
	209	{
	210	ulong start;
	211
	212	mmc_reg_out(&mmc_base->sysctl, bit, bit);
	213
	214	start = get_timer(0);
	215	while ((readl(&mmc_base->sysctl) & bit) != 0) {
	216	if (get_timer(0) - start > MAX_RETRY_MS) {
	217	printf("%s: timedout waiting for sysctl %x to clear\n",
	218	__func__, bit);
	219	return;
	220	}
	221	}
	222	}
de941241 SG	223
	224	static int mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	225	struct mmc_data *data)
	226	{
933efe64	227	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	228	unsigned int flags, mmc_stat;
eb9a28f6	229	ulong start;
de941241	230
eb9a28f6	231	start = get_timer(0);
a7778f8f	232	while ((readl(&mmc_base->pstate) & (DATI_MASK \| CMDI_MASK)) != 0) {
eb9a28f6	233	if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f TR	234	printf("%s: timedout waiting on cmd inhibit to clear\n",
a7778f8f TR	235	__func__);
eb9a28f6 NM	236	return TIMEOUT;
	237	}
	238	}
de941241	239	writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6 NM	240	start = get_timer(0);
	241	while (readl(&mmc_base->stat)) {
	242	if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de GI	243	printf("%s: timedout waiting for STAT (%x) to clear\n",
15ceb1de GI	244	__func__, readl(&mmc_base->stat));
eb9a28f6 NM	245	return TIMEOUT;
	246	}
	247	}
de941241 SG	248	/*
	249	* CMDREG
	250	* CMDIDX[13:8] : Command index
	251	* DATAPRNT[5] : Data Present Select
	252	* ENCMDIDX[4] : Command Index Check Enable
	253	* ENCMDCRC[3] : Command CRC Check Enable
	254	* RSPTYP[1:0]
	255	* 00 = No Response
	256	* 01 = Length 136
	257	* 10 = Length 48
	258	* 11 = Length 48 Check busy after response
	259	*/
	260	/* Delay added before checking the status of frq change
	261	* retry not supported by mmc.c(core file)
	262	*/
	263	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
	264	udelay(50000); /* wait 50 ms */
	265
	266	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	267	flags = 0;
	268	else if (cmd->resp_type & MMC_RSP_136)
	269	flags = RSP_TYPE_LGHT136 \| CICE_NOCHECK;
	270	else if (cmd->resp_type & MMC_RSP_BUSY)
	271	flags = RSP_TYPE_LGHT48B;
	272	else
	273	flags = RSP_TYPE_LGHT48;
	274
	275	/* enable default flags */
	276	flags = flags \| (CMD_TYPE_NORMAL \| CICE_NOCHECK \| CCCE_NOCHECK \|
	277	MSBS_SGLEBLK \| ACEN_DISABLE \| BCE_DISABLE \| DE_DISABLE);
	278
	279	if (cmd->resp_type & MMC_RSP_CRC)
	280	flags \|= CCCE_CHECK;
	281	if (cmd->resp_type & MMC_RSP_OPCODE)
	282	flags \|= CICE_CHECK;
	283
	284	if (data) {
	285	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) \|\|
	286	(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
	287	flags \|= (MSBS_MULTIBLK \| BCE_ENABLE);
	288	data->blocksize = 512;
	289	writel(data->blocksize \| (data->blocks << 16),
	290	&mmc_base->blk);
	291	} else
	292	writel(data->blocksize \| NBLK_STPCNT, &mmc_base->blk);
	293
	294	if (data->flags & MMC_DATA_READ)
	295	flags \|= (DP_DATA \| DDIR_READ);
	296	else
	297	flags \|= (DP_DATA \| DDIR_WRITE);
	298	}
	299
	300	writel(cmd->cmdarg, &mmc_base->arg);
	301	writel((cmd->cmdidx << 24) \| flags, &mmc_base->cmd);
	302
eb9a28f6	303	start = get_timer(0);
de941241 SG	304	do {
de941241 SG	305	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	306	if (get_timer(0) - start > MAX_RETRY_MS) {
	307	printf("%s : timeout: No status update\n", __func__);
	308	return TIMEOUT;
	309	}
	310	} while (!mmc_stat);
de941241	311
25c719e2 GI	312	if ((mmc_stat & IE_CTO) != 0) {
25c719e2 GI	313	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
de941241	314	return TIMEOUT;
25c719e2	315	} else if ((mmc_stat & ERRI_MASK) != 0)
de941241 SG	316	return -1;
	317
	318	if (mmc_stat & CC_MASK) {
	319	writel(CC_MASK, &mmc_base->stat);
	320	if (cmd->resp_type & MMC_RSP_PRESENT) {
	321	if (cmd->resp_type & MMC_RSP_136) {
	322	/* response type 2 */
	323	cmd->response[3] = readl(&mmc_base->rsp10);
	324	cmd->response[2] = readl(&mmc_base->rsp32);
	325	cmd->response[1] = readl(&mmc_base->rsp54);
	326	cmd->response[0] = readl(&mmc_base->rsp76);
	327	} else
	328	/* response types 1, 1b, 3, 4, 5, 6 */
	329	cmd->response[0] = readl(&mmc_base->rsp10);
	330	}
	331	}
	332
	333	if (data && (data->flags & MMC_DATA_READ)) {
	334	mmc_read_data(mmc_base, data->dest,
	335	data->blocksize * data->blocks);
	336	} else if (data && (data->flags & MMC_DATA_WRITE)) {
	337	mmc_write_data(mmc_base, data->src,
	338	data->blocksize * data->blocks);
	339	}
	340	return 0;
	341	}
	342
933efe64	343	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size)
de941241 SG	344	{
	345	unsigned int output_buf = (unsigned int )buf;
	346	unsigned int mmc_stat;
	347	unsigned int count;
	348
	349	/*
	350	* Start Polled Read
	351	*/
	352	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	353	count /= 4;
	354
	355	while (size) {
eb9a28f6	356	ulong start = get_timer(0);
de941241 SG	357	do {
de941241 SG	358	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	359	if (get_timer(0) - start > MAX_RETRY_MS) {
	360	printf("%s: timedout waiting for status!\n",
	361	__func__);
	362	return TIMEOUT;
	363	}
de941241 SG	364	} while (mmc_stat == 0);
de941241 SG	365
25c719e2 GI	366	if ((mmc_stat & (IE_DTO \| IE_DCRC \| IE_DEB)) != 0)
	367	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
	368
de941241 SG	369	if ((mmc_stat & ERRI_MASK) != 0)
	370	return 1;
	371
	372	if (mmc_stat & BRR_MASK) {
	373	unsigned int k;
	374
	375	writel(readl(&mmc_base->stat) \| BRR_MASK,
	376	&mmc_base->stat);
	377	for (k = 0; k < count; k++) {
	378	*output_buf = readl(&mmc_base->data);
	379	output_buf++;
	380	}
	381	size -= (count*4);
	382	}
	383
	384	if (mmc_stat & BWR_MASK)
	385	writel(readl(&mmc_base->stat) \| BWR_MASK,
	386	&mmc_base->stat);
	387
	388	if (mmc_stat & TC_MASK) {
	389	writel(readl(&mmc_base->stat) \| TC_MASK,
	390	&mmc_base->stat);
	391	break;
	392	}
	393	}
	394	return 0;
	395	}
	396
933efe64 S	397	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
933efe64 S	398	unsigned int size)
de941241 SG	399	{
	400	unsigned int input_buf = (unsigned int )buf;
	401	unsigned int mmc_stat;
	402	unsigned int count;
	403
	404	/*
	405	* Start Polled Read
	406	*/
	407	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	408	count /= 4;
	409
	410	while (size) {
eb9a28f6	411	ulong start = get_timer(0);
de941241 SG	412	do {
de941241 SG	413	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	414	if (get_timer(0) - start > MAX_RETRY_MS) {
	415	printf("%s: timedout waiting for status!\n",
	416	__func__);
	417	return TIMEOUT;
	418	}
de941241 SG	419	} while (mmc_stat == 0);
de941241 SG	420
25c719e2 GI	421	if ((mmc_stat & (IE_DTO \| IE_DCRC \| IE_DEB)) != 0)
	422	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
	423
de941241 SG	424	if ((mmc_stat & ERRI_MASK) != 0)
	425	return 1;
	426
	427	if (mmc_stat & BWR_MASK) {
	428	unsigned int k;
	429
	430	writel(readl(&mmc_base->stat) \| BWR_MASK,
	431	&mmc_base->stat);
	432	for (k = 0; k < count; k++) {
	433	writel(*input_buf, &mmc_base->data);
	434	input_buf++;
	435	}
	436	size -= (count*4);
	437	}
	438
	439	if (mmc_stat & BRR_MASK)
	440	writel(readl(&mmc_base->stat) \| BRR_MASK,
	441	&mmc_base->stat);
	442
	443	if (mmc_stat & TC_MASK) {
	444	writel(readl(&mmc_base->stat) \| TC_MASK,
	445	&mmc_base->stat);
	446	break;
	447	}
	448	}
	449	return 0;
	450	}
	451
	452	static void mmc_set_ios(struct mmc *mmc)
	453	{
933efe64	454	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	455	unsigned int dsor = 0;
eb9a28f6	456	ulong start;
de941241 SG	457
	458	/* configue bus width */
	459	switch (mmc->bus_width) {
	460	case 8:
	461	writel(readl(&mmc_base->con) \| DTW_8_BITMODE,
	462	&mmc_base->con);
	463	break;
	464
	465	case 4:
	466	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	467	&mmc_base->con);
	468	writel(readl(&mmc_base->hctl) \| DTW_4_BITMODE,
	469	&mmc_base->hctl);
	470	break;
	471
	472	case 1:
	473	default:
	474	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	475	&mmc_base->con);
	476	writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
	477	&mmc_base->hctl);
	478	break;
	479	}
	480
	481	/* configure clock with 96Mhz system clock.
	482	*/
	483	if (mmc->clock != 0) {
	484	dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
	485	if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
	486	dsor++;
	487	}
	488
	489	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	490	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	491
	492	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	493	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
	494
eb9a28f6 NM	495	start = get_timer(0);
	496	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	497	if (get_timer(0) - start > MAX_RETRY_MS) {
	498	printf("%s: timedout waiting for ics!\n", __func__);
	499	return;
	500	}
	501	}
de941241 SG	502	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	503	}
	504
	505	int omap_mmc_init(int dev_index)
	506	{
	507	struct mmc *mmc;
	508
	509	mmc = &hsmmc_dev[dev_index];
	510
	511	sprintf(mmc->name, "OMAP SD/MMC");
	512	mmc->send_cmd = mmc_send_cmd;
	513	mmc->set_ios = mmc_set_ios;
	514	mmc->init = mmc_init_setup;
48972d90	515	mmc->getcd = NULL;
de941241 SG	516
	517	switch (dev_index) {
	518	case 0:
933efe64	519	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241	520	break;
1037d585	521	#ifdef OMAP_HSMMC2_BASE
de941241	522	case 1:
933efe64	523	mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
de941241	524	break;
1037d585 TR	525	#endif
1037d585 TR	526	#ifdef OMAP_HSMMC3_BASE
de941241	527	case 2:
933efe64	528	mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
de941241	529	break;
1037d585	530	#endif
de941241	531	default:
933efe64	532	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 SG	533	return 1;
	534	}
	535	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
ecd9af88 B	536	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
ecd9af88 B	537	MMC_MODE_HC;
de941241 SG	538
	539	mmc->f_min = 400000;
	540	mmc->f_max = 52000000;
	541
8feafcc4 JR	542	mmc->b_max = 0;
8feafcc4 JR	543
4ca9244d JR	544	#if defined(CONFIG_OMAP34XX)
	545	/*
	546	* Silicon revs 2.1 and older do not support multiblock transfers.
	547	*/
	548	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
	549	mmc->b_max = 1;
	550	#endif
	551
de941241 SG	552	mmc_register(mmc);
	553
	554	return 0;
	555	}