[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 * Sukumar Ghorai <s-ghorai@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation's version 2 of
 * the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <twl6035.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>

/* common definitions for all OMAPs */
#define SYSCTL_SRC	(1 << 25)
#define SYSCTL_SRD	(1 << 26)

struct omap_hsmmc_data {
	struct hsmmc *base_addr;
	int cd_gpio;
};

/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS	1000

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
			unsigned int siz);
static struct mmc hsmmc_dev[3];
static struct omap_hsmmc_data hsmmc_dev_data[3];

#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
static int omap_mmc_setup_gpio_in(int gpio, const char *label)
{
	if (!gpio_is_valid(gpio))
		return -1;

	if (gpio_request(gpio, label) < 0)
		return -1;

	if (gpio_direction_input(gpio) < 0)
		return -1;

	return gpio;
}

static int omap_mmc_getcd(struct mmc *mmc)
{
	int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
	return gpio_get_value(cd_gpio);
}
#else
static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
{
	return -1;
}

#define omap_mmc_getcd NULL
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap_sys_ctrl_regs *const ctrl =
		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;


	value = readl(&ctrl->control_pbiaslite);
	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
	writel(value, &ctrl->control_pbiaslite);
	/* set VMMC to 3V */
	twl6030_power_mmc_init();
	value = readl(&ctrl->control_pbiaslite);
	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
	writel(value, &ctrl->control_pbiaslite);
}
#endif

#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
static void omap5_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap_sys_ctrl_regs *const ctrl =
		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;

	value = readl(&ctrl->control_pbias);
	value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
	value |= SDCARD_BIAS_HIZ_MODE;
	writel(value, &ctrl->control_pbias);

	twl6035_mmc1_poweron_ldo();

	value = readl(&ctrl->control_pbias);
	value &= ~SDCARD_BIAS_HIZ_MODE;
	value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
	writel(value, &ctrl->control_pbias);

	value = readl(&ctrl->control_pbias);
	if (value & (1 << 23)) {
		value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
		value |= SDCARD_BIAS_HIZ_MODE;
		writel(value, &ctrl->control_pbias);
	}
}
#endif

unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
	t2_t *t2_base = (t2_t *)T2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	u32 pbias_lite;

	pbias_lite = readl(&t2_base->pbias_lite);
	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
	writel(pbias_lite, &t2_base->pbias_lite);
#endif
#if defined(CONFIG_TWL4030_POWER)
	twl4030_power_mmc_init();
	mdelay(100);	/* ramp-up delay from Linux code */
#endif
#if defined(CONFIG_OMAP34XX)
	writel(pbias_lite | PBIASLITEPWRDNZ1 |
		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
		&t2_base->pbias_lite);

	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
		&t2_base->devconf0);

	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
		&t2_base->devconf1);

	/* Change from default of 52MHz to 26MHz if necessary */
	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
			&t2_base->ctl_prog_io1);

	writel(readl(&prcm_base->fclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->fclken1_core);

	writel(readl(&prcm_base->iclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->iclken1_core);
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	/* PBIAS config needed for MMC1 only */
	if (mmc->block_dev.dev == 0)
		omap4_vmmc_pbias_config(mmc);
#endif
#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
	if (mmc->block_dev.dev == 0)
		omap5_pbias_config(mmc);
#endif

	return 0;
}

void mmc_init_stream(struct hsmmc *mmc_base)
{
	ulong start;

	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);

	writel(MMC_CMD0, &mmc_base->cmd);
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc!\n", __func__);
			return;
		}
	}
	writel(CC_MASK, &mmc_base->stat)
		;
	writel(MMC_CMD0, &mmc_base->cmd)
		;
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}


static int mmc_init_setup(struct mmc *mmc)
{
	struct hsmmc *mmc_base;
	unsigned int reg_val;
	unsigned int dsor;
	ulong start;

	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
	mmc_board_init(mmc);

	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
		&mmc_base->sysconfig);
	start = get_timer(0);
	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for softresetall!\n",
				__func__);
			return TIMEOUT;
		}
	}
	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
		&mmc_base->capa);

	reg_val = readl(&mmc_base->con) & RESERVED_MASK;

	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);

	dsor = 240;
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);

	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);

	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
		&mmc_base->ie);

	mmc_init_stream(mmc_base);

	return 0;
}

/*
 * MMC controller internal finite state machine reset
 *
 * Used to reset command or data internal state machines, using respectively
 * SRC or SRD bit of SYSCTL register
 */
static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
{
	ulong start;

	mmc_reg_out(&mmc_base->sysctl, bit, bit);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & bit) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for sysctl %x to clear\n",
				__func__, bit);
			return;
		}
	}
}

static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			struct mmc_data *data)
{
	struct hsmmc *mmc_base;
	unsigned int flags, mmc_stat;
	ulong start;

	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
	start = get_timer(0);
	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting on cmd inhibit to clear\n",
					__func__);
			return TIMEOUT;
		}
	}
	writel(0xFFFFFFFF, &mmc_base->stat);
	start = get_timer(0);
	while (readl(&mmc_base->stat)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for STAT (%x) to clear\n",
				__func__, readl(&mmc_base->stat));
			return TIMEOUT;
		}
	}
	/*
	 * CMDREG
	 * CMDIDX[13:8]	: Command index
	 * DATAPRNT[5]	: Data Present Select
	 * ENCMDIDX[4]	: Command Index Check Enable
	 * ENCMDCRC[3]	: Command CRC Check Enable
	 * RSPTYP[1:0]
	 *	00 = No Response
	 *	01 = Length 136
	 *	10 = Length 48
	 *	11 = Length 48 Check busy after response
	 */
	/* Delay added before checking the status of frq change
	 * retry not supported by mmc.c(core file)
	 */
	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
		udelay(50000); /* wait 50 ms */

	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = 0;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		flags = RSP_TYPE_LGHT48B;
	else
		flags = RSP_TYPE_LGHT48;

	/* enable default flags */
	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= CCCE_CHECK;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= CICE_CHECK;

	if (data) {
		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
			data->blocksize = 512;
			writel(data->blocksize | (data->blocks << 16),
							&mmc_base->blk);
		} else
			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

		if (data->flags & MMC_DATA_READ)
			flags |= (DP_DATA | DDIR_READ);
		else
			flags |= (DP_DATA | DDIR_WRITE);
	}

	writel(cmd->cmdarg, &mmc_base->arg);
	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

	start = get_timer(0);
	do {
		mmc_stat = readl(&mmc_base->stat);
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s : timeout: No status update\n", __func__);
			return TIMEOUT;
		}
	} while (!mmc_stat);

	if ((mmc_stat & IE_CTO) != 0) {
		mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
		return TIMEOUT;
	} else if ((mmc_stat & ERRI_MASK) != 0)
		return -1;

	if (mmc_stat & CC_MASK) {
		writel(CC_MASK, &mmc_base->stat);
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (cmd->resp_type & MMC_RSP_136) {
				/* response type 2 */
				cmd->response[3] = readl(&mmc_base->rsp10);
				cmd->response[2] = readl(&mmc_base->rsp32);
				cmd->response[1] = readl(&mmc_base->rsp54);
				cmd->response[0] = readl(&mmc_base->rsp76);
			} else
				/* response types 1, 1b, 3, 4, 5, 6 */
				cmd->response[0] = readl(&mmc_base->rsp10);
		}
	}

	if (data && (data->flags & MMC_DATA_READ)) {
		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void mmc_set_ios(struct mmc *mmc)
{
	struct hsmmc *mmc_base;
	unsigned int dsor = 0;
	ulong start;

	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	/* configure clock with 96Mhz system clock.
	 */
	if (mmc->clock != 0) {
		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
			dsor++;
	}

	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio)
{
	struct mmc *mmc = &hsmmc_dev[dev_index];
	struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];

	sprintf(mmc->name, "OMAP SD/MMC");
	mmc->send_cmd = mmc_send_cmd;
	mmc->set_ios = mmc_set_ios;
	mmc->init = mmc_init_setup;
	mmc->getcd = omap_mmc_getcd;
	mmc->getwp = NULL;
	mmc->priv = priv_data;

	switch (dev_index) {
	case 0:
		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
		break;
#endif
	default:
		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
				MMC_MODE_HC) & ~host_caps_mask;

	mmc->f_min = 400000;

	if (f_max != 0)
		mmc->f_max = f_max;
	else {
		if (mmc->host_caps & MMC_MODE_HS) {
			if (mmc->host_caps & MMC_MODE_HS_52MHz)
				mmc->f_max = 52000000;
			else
				mmc->f_max = 26000000;
		} else
			mmc->f_max = 20000000;
	}

	mmc->b_max = 0;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		mmc->b_max = 1;
#endif

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
de941241 SG	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	* Sukumar Ghorai <s-ghorai@ti.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation's version 2 of
	12	* the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <common.h>
	27	#include <mmc.h>
	28	#include <part.h>
	29	#include <i2c.h>
	30	#include <twl4030.h>
14fa2dd0	31	#include <twl6030.h>
dd23e59d	32	#include <twl6035.h>
e874d5b0	33	#include <asm/gpio.h>
de941241 SG	34	#include <asm/io.h>
de941241 SG	35	#include <asm/arch/mmc_host_def.h>
96e0e7b3	36	#include <asm/arch/sys_proto.h>
de941241	37
25c719e2 GI	38	/* common definitions for all OMAPs */
	39	#define SYSCTL_SRC (1 << 25)
	40	#define SYSCTL_SRD (1 << 26)
	41
cc22b0c0 NK	42	struct omap_hsmmc_data {
cc22b0c0 NK	43	struct hsmmc *base_addr;
e874d5b0	44	int cd_gpio;
cc22b0c0 NK	45	};
cc22b0c0 NK	46
eb9a28f6 NM	47	/* If we fail after 1 second wait, something is really bad */
	48	#define MAX_RETRY_MS 1000
	49
933efe64 S	50	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size);
	51	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
	52	unsigned int siz);
5964dadd	53	static struct mmc hsmmc_dev[3];
cc22b0c0	54	static struct omap_hsmmc_data hsmmc_dev_data[3];
14fa2dd0	55
e874d5b0 NK	56	#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) \|\| \
	57	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
	58	static int omap_mmc_setup_gpio_in(int gpio, const char *label)
	59	{
	60	if (!gpio_is_valid(gpio))
	61	return -1;
	62
	63	if (gpio_request(gpio, label) < 0)
	64	return -1;
	65
	66	if (gpio_direction_input(gpio) < 0)
	67	return -1;
	68
	69	return gpio;
	70	}
	71
	72	static int omap_mmc_getcd(struct mmc *mmc)
	73	{
	74	int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
	75	return gpio_get_value(cd_gpio);
	76	}
	77	#else
	78	static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
	79	{
	80	return -1;
	81	}
	82
	83	#define omap_mmc_getcd NULL
	84	#endif
	85
14fa2dd0 B	86	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	87	static void omap4_vmmc_pbias_config(struct mmc *mmc)
	88	{
	89	u32 value = 0;
002a2c0c S	90	struct omap_sys_ctrl_regs *const ctrl =
002a2c0c S	91	(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
14fa2dd0 B	92
	93
	94	value = readl(&ctrl->control_pbiaslite);
	95	value &= ~(MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ);
	96	writel(value, &ctrl->control_pbiaslite);
	97	/* set VMMC to 3V */
	98	twl6030_power_mmc_init();
	99	value = readl(&ctrl->control_pbiaslite);
	100	value \|= MMC1_PBIASLITE_VMODE \| MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ;
	101	writel(value, &ctrl->control_pbiaslite);
	102	}
	103	#endif
	104
dd23e59d B	105	#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
	106	static void omap5_pbias_config(struct mmc *mmc)
	107	{
	108	u32 value = 0;
	109	struct omap_sys_ctrl_regs *const ctrl =
	110	(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
	111
	112	value = readl(&ctrl->control_pbias);
	113	value &= ~(SDCARD_PWRDNZ \| SDCARD_BIAS_PWRDNZ);
	114	value \|= SDCARD_BIAS_HIZ_MODE;
	115	writel(value, &ctrl->control_pbias);
	116
	117	twl6035_mmc1_poweron_ldo();
	118
	119	value = readl(&ctrl->control_pbias);
	120	value &= ~SDCARD_BIAS_HIZ_MODE;
	121	value \|= SDCARD_PBIASLITE_VMODE \| SDCARD_PWRDNZ \| SDCARD_BIAS_PWRDNZ;
	122	writel(value, &ctrl->control_pbias);
	123
	124	value = readl(&ctrl->control_pbias);
	125	if (value & (1 << 23)) {
	126	value &= ~(SDCARD_PWRDNZ \| SDCARD_BIAS_PWRDNZ);
	127	value \|= SDCARD_BIAS_HIZ_MODE;
	128	writel(value, &ctrl->control_pbias);
	129	}
	130	}
	131	#endif
	132
14fa2dd0	133	unsigned char mmc_board_init(struct mmc *mmc)
de941241	134	{
de941241 SG	135	#if defined(CONFIG_OMAP34XX)
	136	t2_t t2_base = (t2_t )T2_BASE;
	137	struct prcm prcm_base = (struct prcm )PRCM_BASE;
b1e725f2	138	u32 pbias_lite;
de941241	139
b1e725f2 GI	140	pbias_lite = readl(&t2_base->pbias_lite);
	141	pbias_lite &= ~(PBIASLITEPWRDNZ1 \| PBIASLITEPWRDNZ0);
	142	writel(pbias_lite, &t2_base->pbias_lite);
	143	#endif
	144	#if defined(CONFIG_TWL4030_POWER)
	145	twl4030_power_mmc_init();
	146	mdelay(100); /* ramp-up delay from Linux code */
	147	#endif
	148	#if defined(CONFIG_OMAP34XX)
	149	writel(pbias_lite \| PBIASLITEPWRDNZ1 \|
de941241 SG	150	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
	151	&t2_base->pbias_lite);
	152
	153	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
	154	&t2_base->devconf0);
	155
	156	writel(readl(&t2_base->devconf1) \| MMCSDIO2ADPCLKISEL,
	157	&t2_base->devconf1);
	158
bbbc1ae9 JS	159	/* Change from default of 52MHz to 26MHz if necessary */
	160	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
	161	writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
	162	&t2_base->ctl_prog_io1);
	163
de941241 SG	164	writel(readl(&prcm_base->fclken1_core) \|
	165	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	166	&prcm_base->fclken1_core);
	167
	168	writel(readl(&prcm_base->iclken1_core) \|
	169	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	170	&prcm_base->iclken1_core);
	171	#endif
	172
14fa2dd0 B	173	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	174	/* PBIAS config needed for MMC1 only */
	175	if (mmc->block_dev.dev == 0)
	176	omap4_vmmc_pbias_config(mmc);
	177	#endif
dd23e59d B	178	#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
	179	if (mmc->block_dev.dev == 0)
	180	omap5_pbias_config(mmc);
	181	#endif
de941241 SG	182
	183	return 0;
	184	}
	185
933efe64	186	void mmc_init_stream(struct hsmmc *mmc_base)
de941241	187	{
eb9a28f6	188	ulong start;
de941241 SG	189
	190	writel(readl(&mmc_base->con) \| INIT_INITSTREAM, &mmc_base->con);
	191
	192	writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6 NM	193	start = get_timer(0);
	194	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	195	if (get_timer(0) - start > MAX_RETRY_MS) {
	196	printf("%s: timedout waiting for cc!\n", __func__);
	197	return;
	198	}
	199	}
de941241 SG	200	writel(CC_MASK, &mmc_base->stat)
	201	;
	202	writel(MMC_CMD0, &mmc_base->cmd)
	203	;
eb9a28f6 NM	204	start = get_timer(0);
	205	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	206	if (get_timer(0) - start > MAX_RETRY_MS) {
	207	printf("%s: timedout waiting for cc2!\n", __func__);
	208	return;
	209	}
	210	}
de941241 SG	211	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
	212	}
	213
	214
	215	static int mmc_init_setup(struct mmc *mmc)
	216	{
cc22b0c0	217	struct hsmmc *mmc_base;
de941241 SG	218	unsigned int reg_val;
de941241 SG	219	unsigned int dsor;
eb9a28f6	220	ulong start;
de941241	221
cc22b0c0	222	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
14fa2dd0	223	mmc_board_init(mmc);
de941241 SG	224
	225	writel(readl(&mmc_base->sysconfig) \| MMC_SOFTRESET,
	226	&mmc_base->sysconfig);
eb9a28f6 NM	227	start = get_timer(0);
	228	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
	229	if (get_timer(0) - start > MAX_RETRY_MS) {
	230	printf("%s: timedout waiting for cc2!\n", __func__);
	231	return TIMEOUT;
	232	}
	233	}
de941241	234	writel(readl(&mmc_base->sysctl) \| SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6 NM	235	start = get_timer(0);
	236	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
	237	if (get_timer(0) - start > MAX_RETRY_MS) {
	238	printf("%s: timedout waiting for softresetall!\n",
	239	__func__);
	240	return TIMEOUT;
	241	}
	242	}
de941241 SG	243	writel(DTW_1_BITMODE \| SDBP_PWROFF \| SDVS_3V0, &mmc_base->hctl);
	244	writel(readl(&mmc_base->capa) \| VS30_3V0SUP \| VS18_1V8SUP,
	245	&mmc_base->capa);
	246
	247	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
	248
	249	writel(CTPL_MMC_SD \| reg_val \| WPP_ACTIVEHIGH \| CDP_ACTIVEHIGH \|
	250	MIT_CTO \| DW8_1_4BITMODE \| MODE_FUNC \| STR_BLOCK \|
	251	HR_NOHOSTRESP \| INIT_NOINIT \| NOOPENDRAIN, &mmc_base->con);
	252
	253	dsor = 240;
	254	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	255	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	256	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	257	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
eb9a28f6 NM	258	start = get_timer(0);
	259	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	260	if (get_timer(0) - start > MAX_RETRY_MS) {
	261	printf("%s: timedout waiting for ics!\n", __func__);
	262	return TIMEOUT;
	263	}
	264	}
de941241 SG	265	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	266
	267	writel(readl(&mmc_base->hctl) \| SDBP_PWRON, &mmc_base->hctl);
	268
	269	writel(IE_BADA \| IE_CERR \| IE_DEB \| IE_DCRC \| IE_DTO \| IE_CIE \|
	270	IE_CEB \| IE_CCRC \| IE_CTO \| IE_BRR \| IE_BWR \| IE_TC \| IE_CC,
	271	&mmc_base->ie);
	272
	273	mmc_init_stream(mmc_base);
	274
	275	return 0;
	276	}
	277
25c719e2 GI	278	/*
	279	* MMC controller internal finite state machine reset
	280	*
	281	* Used to reset command or data internal state machines, using respectively
	282	* SRC or SRD bit of SYSCTL register
	283	*/
	284	static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
	285	{
	286	ulong start;
	287
	288	mmc_reg_out(&mmc_base->sysctl, bit, bit);
	289
	290	start = get_timer(0);
	291	while ((readl(&mmc_base->sysctl) & bit) != 0) {
	292	if (get_timer(0) - start > MAX_RETRY_MS) {
	293	printf("%s: timedout waiting for sysctl %x to clear\n",
	294	__func__, bit);
	295	return;
	296	}
	297	}
	298	}
de941241 SG	299
	300	static int mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	301	struct mmc_data *data)
	302	{
cc22b0c0	303	struct hsmmc *mmc_base;
de941241	304	unsigned int flags, mmc_stat;
eb9a28f6	305	ulong start;
de941241	306
cc22b0c0	307	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
eb9a28f6	308	start = get_timer(0);
a7778f8f	309	while ((readl(&mmc_base->pstate) & (DATI_MASK \| CMDI_MASK)) != 0) {
eb9a28f6	310	if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f TR	311	printf("%s: timedout waiting on cmd inhibit to clear\n",
a7778f8f TR	312	__func__);
eb9a28f6 NM	313	return TIMEOUT;
	314	}
	315	}
de941241	316	writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6 NM	317	start = get_timer(0);
	318	while (readl(&mmc_base->stat)) {
	319	if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de GI	320	printf("%s: timedout waiting for STAT (%x) to clear\n",
15ceb1de GI	321	__func__, readl(&mmc_base->stat));
eb9a28f6 NM	322	return TIMEOUT;
	323	}
	324	}
de941241 SG	325	/*
	326	* CMDREG
	327	* CMDIDX[13:8] : Command index
	328	* DATAPRNT[5] : Data Present Select
	329	* ENCMDIDX[4] : Command Index Check Enable
	330	* ENCMDCRC[3] : Command CRC Check Enable
	331	* RSPTYP[1:0]
	332	* 00 = No Response
	333	* 01 = Length 136
	334	* 10 = Length 48
	335	* 11 = Length 48 Check busy after response
	336	*/
	337	/* Delay added before checking the status of frq change
	338	* retry not supported by mmc.c(core file)
	339	*/
	340	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
	341	udelay(50000); /* wait 50 ms */
	342
	343	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	344	flags = 0;
	345	else if (cmd->resp_type & MMC_RSP_136)
	346	flags = RSP_TYPE_LGHT136 \| CICE_NOCHECK;
	347	else if (cmd->resp_type & MMC_RSP_BUSY)
	348	flags = RSP_TYPE_LGHT48B;
	349	else
	350	flags = RSP_TYPE_LGHT48;
	351
	352	/* enable default flags */
	353	flags = flags \| (CMD_TYPE_NORMAL \| CICE_NOCHECK \| CCCE_NOCHECK \|
	354	MSBS_SGLEBLK \| ACEN_DISABLE \| BCE_DISABLE \| DE_DISABLE);
	355
	356	if (cmd->resp_type & MMC_RSP_CRC)
	357	flags \|= CCCE_CHECK;
	358	if (cmd->resp_type & MMC_RSP_OPCODE)
	359	flags \|= CICE_CHECK;
	360
	361	if (data) {
	362	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) \|\|
	363	(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
	364	flags \|= (MSBS_MULTIBLK \| BCE_ENABLE);
	365	data->blocksize = 512;
	366	writel(data->blocksize \| (data->blocks << 16),
	367	&mmc_base->blk);
	368	} else
	369	writel(data->blocksize \| NBLK_STPCNT, &mmc_base->blk);
	370
	371	if (data->flags & MMC_DATA_READ)
	372	flags \|= (DP_DATA \| DDIR_READ);
	373	else
	374	flags \|= (DP_DATA \| DDIR_WRITE);
	375	}
	376
	377	writel(cmd->cmdarg, &mmc_base->arg);
	378	writel((cmd->cmdidx << 24) \| flags, &mmc_base->cmd);
	379
eb9a28f6	380	start = get_timer(0);
de941241 SG	381	do {
de941241 SG	382	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	383	if (get_timer(0) - start > MAX_RETRY_MS) {
	384	printf("%s : timeout: No status update\n", __func__);
	385	return TIMEOUT;
	386	}
	387	} while (!mmc_stat);
de941241	388
25c719e2 GI	389	if ((mmc_stat & IE_CTO) != 0) {
25c719e2 GI	390	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
de941241	391	return TIMEOUT;
25c719e2	392	} else if ((mmc_stat & ERRI_MASK) != 0)
de941241 SG	393	return -1;
	394
	395	if (mmc_stat & CC_MASK) {
	396	writel(CC_MASK, &mmc_base->stat);
	397	if (cmd->resp_type & MMC_RSP_PRESENT) {
	398	if (cmd->resp_type & MMC_RSP_136) {
	399	/* response type 2 */
	400	cmd->response[3] = readl(&mmc_base->rsp10);
	401	cmd->response[2] = readl(&mmc_base->rsp32);
	402	cmd->response[1] = readl(&mmc_base->rsp54);
	403	cmd->response[0] = readl(&mmc_base->rsp76);
	404	} else
	405	/* response types 1, 1b, 3, 4, 5, 6 */
	406	cmd->response[0] = readl(&mmc_base->rsp10);
	407	}
	408	}
	409
	410	if (data && (data->flags & MMC_DATA_READ)) {
	411	mmc_read_data(mmc_base, data->dest,
	412	data->blocksize * data->blocks);
	413	} else if (data && (data->flags & MMC_DATA_WRITE)) {
	414	mmc_write_data(mmc_base, data->src,
	415	data->blocksize * data->blocks);
	416	}
	417	return 0;
	418	}
	419
933efe64	420	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size)
de941241 SG	421	{
	422	unsigned int output_buf = (unsigned int )buf;
	423	unsigned int mmc_stat;
	424	unsigned int count;
	425
	426	/*
	427	* Start Polled Read
	428	*/
	429	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	430	count /= 4;
	431
	432	while (size) {
eb9a28f6	433	ulong start = get_timer(0);
de941241 SG	434	do {
de941241 SG	435	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	436	if (get_timer(0) - start > MAX_RETRY_MS) {
	437	printf("%s: timedout waiting for status!\n",
	438	__func__);
	439	return TIMEOUT;
	440	}
de941241 SG	441	} while (mmc_stat == 0);
de941241 SG	442
25c719e2 GI	443	if ((mmc_stat & (IE_DTO \| IE_DCRC \| IE_DEB)) != 0)
	444	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
	445
de941241 SG	446	if ((mmc_stat & ERRI_MASK) != 0)
	447	return 1;
	448
	449	if (mmc_stat & BRR_MASK) {
	450	unsigned int k;
	451
	452	writel(readl(&mmc_base->stat) \| BRR_MASK,
	453	&mmc_base->stat);
	454	for (k = 0; k < count; k++) {
	455	*output_buf = readl(&mmc_base->data);
	456	output_buf++;
	457	}
	458	size -= (count*4);
	459	}
	460
	461	if (mmc_stat & BWR_MASK)
	462	writel(readl(&mmc_base->stat) \| BWR_MASK,
	463	&mmc_base->stat);
	464
	465	if (mmc_stat & TC_MASK) {
	466	writel(readl(&mmc_base->stat) \| TC_MASK,
	467	&mmc_base->stat);
	468	break;
	469	}
	470	}
	471	return 0;
	472	}
	473
933efe64 S	474	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
933efe64 S	475	unsigned int size)
de941241 SG	476	{
	477	unsigned int input_buf = (unsigned int )buf;
	478	unsigned int mmc_stat;
	479	unsigned int count;
	480
	481	/*
	482	* Start Polled Read
	483	*/
	484	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	485	count /= 4;
	486
	487	while (size) {
eb9a28f6	488	ulong start = get_timer(0);
de941241 SG	489	do {
de941241 SG	490	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	491	if (get_timer(0) - start > MAX_RETRY_MS) {
	492	printf("%s: timedout waiting for status!\n",
	493	__func__);
	494	return TIMEOUT;
	495	}
de941241 SG	496	} while (mmc_stat == 0);
de941241 SG	497
25c719e2 GI	498	if ((mmc_stat & (IE_DTO \| IE_DCRC \| IE_DEB)) != 0)
	499	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
	500
de941241 SG	501	if ((mmc_stat & ERRI_MASK) != 0)
	502	return 1;
	503
	504	if (mmc_stat & BWR_MASK) {
	505	unsigned int k;
	506
	507	writel(readl(&mmc_base->stat) \| BWR_MASK,
	508	&mmc_base->stat);
	509	for (k = 0; k < count; k++) {
	510	writel(*input_buf, &mmc_base->data);
	511	input_buf++;
	512	}
	513	size -= (count*4);
	514	}
	515
	516	if (mmc_stat & BRR_MASK)
	517	writel(readl(&mmc_base->stat) \| BRR_MASK,
	518	&mmc_base->stat);
	519
	520	if (mmc_stat & TC_MASK) {
	521	writel(readl(&mmc_base->stat) \| TC_MASK,
	522	&mmc_base->stat);
	523	break;
	524	}
	525	}
	526	return 0;
	527	}
	528
	529	static void mmc_set_ios(struct mmc *mmc)
	530	{
cc22b0c0	531	struct hsmmc *mmc_base;
de941241	532	unsigned int dsor = 0;
eb9a28f6	533	ulong start;
de941241	534
cc22b0c0	535	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
de941241 SG	536	/* configue bus width */
	537	switch (mmc->bus_width) {
	538	case 8:
	539	writel(readl(&mmc_base->con) \| DTW_8_BITMODE,
	540	&mmc_base->con);
	541	break;
	542
	543	case 4:
	544	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	545	&mmc_base->con);
	546	writel(readl(&mmc_base->hctl) \| DTW_4_BITMODE,
	547	&mmc_base->hctl);
	548	break;
	549
	550	case 1:
	551	default:
	552	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	553	&mmc_base->con);
	554	writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
	555	&mmc_base->hctl);
	556	break;
	557	}
	558
	559	/* configure clock with 96Mhz system clock.
	560	*/
	561	if (mmc->clock != 0) {
	562	dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
	563	if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
	564	dsor++;
	565	}
	566
	567	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	568	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	569
	570	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	571	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
	572
eb9a28f6 NM	573	start = get_timer(0);
	574	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	575	if (get_timer(0) - start > MAX_RETRY_MS) {
	576	printf("%s: timedout waiting for ics!\n", __func__);
	577	return;
	578	}
	579	}
de941241 SG	580	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	581	}
	582
e874d5b0	583	int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio)
de941241	584	{
cc22b0c0 NK	585	struct mmc *mmc = &hsmmc_dev[dev_index];
cc22b0c0 NK	586	struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
de941241 SG	587
	588	sprintf(mmc->name, "OMAP SD/MMC");
	589	mmc->send_cmd = mmc_send_cmd;
	590	mmc->set_ios = mmc_set_ios;
	591	mmc->init = mmc_init_setup;
e874d5b0	592	mmc->getcd = omap_mmc_getcd;
d23d8d7e	593	mmc->getwp = NULL;
cc22b0c0	594	mmc->priv = priv_data;
de941241 SG	595
	596	switch (dev_index) {
	597	case 0:
cc22b0c0	598	priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241	599	break;
1037d585	600	#ifdef OMAP_HSMMC2_BASE
de941241	601	case 1:
cc22b0c0	602	priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
de941241	603	break;
1037d585 TR	604	#endif
1037d585 TR	605	#ifdef OMAP_HSMMC3_BASE
de941241	606	case 2:
cc22b0c0	607	priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
de941241	608	break;
1037d585	609	#endif
de941241	610	default:
cc22b0c0	611	priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 SG	612	return 1;
de941241 SG	613	}
e874d5b0	614	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
de941241	615	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
bbbc1ae9 JS	616	mmc->host_caps = (MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
bbbc1ae9 JS	617	MMC_MODE_HC) & ~host_caps_mask;
de941241 SG	618
de941241 SG	619	mmc->f_min = 400000;
bbbc1ae9 JS	620
	621	if (f_max != 0)
	622	mmc->f_max = f_max;
	623	else {
	624	if (mmc->host_caps & MMC_MODE_HS) {
	625	if (mmc->host_caps & MMC_MODE_HS_52MHz)
	626	mmc->f_max = 52000000;
	627	else
	628	mmc->f_max = 26000000;
	629	} else
	630	mmc->f_max = 20000000;
	631	}
de941241	632
8feafcc4 JR	633	mmc->b_max = 0;
8feafcc4 JR	634
4ca9244d JR	635	#if defined(CONFIG_OMAP34XX)
	636	/*
	637	* Silicon revs 2.1 and older do not support multiblock transfers.
	638	*/
	639	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
	640	mmc->b_max = 1;
	641	#endif
	642
de941241 SG	643	mmc_register(mmc);
	644
	645	return 0;
	646	}