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Commit | Line | Data |
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af62a557 LW |
1 | /* |
2 | * Copyright 2011, Marvell Semiconductor Inc. | |
3 | * Lei Wen <leiwen@marvell.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
af62a557 LW |
6 | * |
7 | * Back ported to the 8xx platform (from the 8260 platform) by | |
8 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
2a809093 | 12 | #include <errno.h> |
af62a557 LW |
13 | #include <malloc.h> |
14 | #include <mmc.h> | |
15 | #include <sdhci.h> | |
16 | ||
492d3223 SR |
17 | #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) |
18 | void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; | |
19 | #else | |
af62a557 | 20 | void *aligned_buffer; |
492d3223 | 21 | #endif |
af62a557 LW |
22 | |
23 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
24 | { | |
25 | unsigned long timeout; | |
26 | ||
27 | /* Wait max 100 ms */ | |
28 | timeout = 100; | |
29 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); | |
30 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { | |
31 | if (timeout == 0) { | |
30e6d979 DR |
32 | printf("%s: Reset 0x%x never completed.\n", |
33 | __func__, (int)mask); | |
af62a557 LW |
34 | return; |
35 | } | |
36 | timeout--; | |
37 | udelay(1000); | |
38 | } | |
39 | } | |
40 | ||
41 | static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) | |
42 | { | |
43 | int i; | |
44 | if (cmd->resp_type & MMC_RSP_136) { | |
45 | /* CRC is stripped so we need to do some shifting. */ | |
46 | for (i = 0; i < 4; i++) { | |
47 | cmd->response[i] = sdhci_readl(host, | |
48 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
49 | if (i != 3) | |
50 | cmd->response[i] |= sdhci_readb(host, | |
51 | SDHCI_RESPONSE + (3-i)*4-1); | |
52 | } | |
53 | } else { | |
54 | cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); | |
55 | } | |
56 | } | |
57 | ||
58 | static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) | |
59 | { | |
60 | int i; | |
61 | char *offs; | |
62 | for (i = 0; i < data->blocksize; i += 4) { | |
63 | offs = data->dest + i; | |
64 | if (data->flags == MMC_DATA_READ) | |
65 | *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); | |
66 | else | |
67 | sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); | |
68 | } | |
69 | } | |
70 | ||
71 | static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, | |
72 | unsigned int start_addr) | |
73 | { | |
a004abde | 74 | unsigned int stat, rdy, mask, timeout, block = 0; |
7dde50d7 | 75 | bool transfer_done = false; |
45a68fe2 | 76 | #ifdef CONFIG_MMC_SDHCI_SDMA |
804c7f42 | 77 | unsigned char ctrl; |
2c011847 | 78 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
804c7f42 | 79 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
2c011847 | 80 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
804c7f42 | 81 | #endif |
af62a557 | 82 | |
5d48e422 | 83 | timeout = 1000000; |
af62a557 LW |
84 | rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; |
85 | mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; | |
86 | do { | |
87 | stat = sdhci_readl(host, SDHCI_INT_STATUS); | |
88 | if (stat & SDHCI_INT_ERROR) { | |
30e6d979 DR |
89 | printf("%s: Error detected in status(0x%X)!\n", |
90 | __func__, stat); | |
2cb5d67c | 91 | return -EIO; |
af62a557 | 92 | } |
7dde50d7 | 93 | if (!transfer_done && (stat & rdy)) { |
af62a557 LW |
94 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) |
95 | continue; | |
96 | sdhci_writel(host, rdy, SDHCI_INT_STATUS); | |
97 | sdhci_transfer_pio(host, data); | |
98 | data->dest += data->blocksize; | |
7dde50d7 AD |
99 | if (++block >= data->blocks) { |
100 | /* Keep looping until the SDHCI_INT_DATA_END is | |
101 | * cleared, even if we finished sending all the | |
102 | * blocks. | |
103 | */ | |
104 | transfer_done = true; | |
105 | continue; | |
106 | } | |
af62a557 | 107 | } |
45a68fe2 | 108 | #ifdef CONFIG_MMC_SDHCI_SDMA |
7dde50d7 | 109 | if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { |
af62a557 | 110 | sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); |
3e81c772 | 111 | start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); |
af62a557 LW |
112 | start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; |
113 | sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); | |
114 | } | |
115 | #endif | |
a004abde LW |
116 | if (timeout-- > 0) |
117 | udelay(10); | |
118 | else { | |
30e6d979 | 119 | printf("%s: Transfer data timeout\n", __func__); |
2cb5d67c | 120 | return -ETIMEDOUT; |
a004abde | 121 | } |
af62a557 LW |
122 | } while (!(stat & SDHCI_INT_DATA_END)); |
123 | return 0; | |
124 | } | |
125 | ||
56b34bc6 PM |
126 | /* |
127 | * No command will be sent by driver if card is busy, so driver must wait | |
128 | * for card ready state. | |
129 | * Every time when card is busy after timeout then (last) timeout value will be | |
130 | * increased twice but only if it doesn't exceed global defined maximum. | |
65a25b20 | 131 | * Each function call will use last timeout value. |
56b34bc6 | 132 | */ |
65a25b20 | 133 | #define SDHCI_CMD_MAX_TIMEOUT 3200 |
d8ce77b2 | 134 | #define SDHCI_CMD_DEFAULT_TIMEOUT 100 |
d90bb439 | 135 | #define SDHCI_READ_STATUS_TIMEOUT 1000 |
56b34bc6 | 136 | |
ef1e4eda SG |
137 | #ifdef CONFIG_DM_MMC_OPS |
138 | static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, | |
139 | struct mmc_data *data) | |
140 | { | |
141 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
142 | ||
143 | #else | |
6588c78b | 144 | static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, |
ef1e4eda | 145 | struct mmc_data *data) |
af62a557 | 146 | { |
ef1e4eda | 147 | #endif |
93bfd616 | 148 | struct sdhci_host *host = mmc->priv; |
af62a557 LW |
149 | unsigned int stat = 0; |
150 | int ret = 0; | |
151 | int trans_bytes = 0, is_aligned = 1; | |
152 | u32 mask, flags, mode; | |
56b34bc6 | 153 | unsigned int time = 0, start_addr = 0; |
19d2e342 | 154 | int mmc_dev = mmc_get_blk_desc(mmc)->devnum; |
29905a45 | 155 | unsigned start = get_timer(0); |
af62a557 | 156 | |
56b34bc6 | 157 | /* Timeout unit - ms */ |
d8ce77b2 | 158 | static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; |
af62a557 LW |
159 | |
160 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); | |
161 | mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; | |
162 | ||
163 | /* We shouldn't wait for data inihibit for stop commands, even | |
164 | though they might use busy signaling */ | |
165 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
166 | mask &= ~SDHCI_DATA_INHIBIT; | |
167 | ||
168 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { | |
56b34bc6 | 169 | if (time >= cmd_timeout) { |
30e6d979 | 170 | printf("%s: MMC: %d busy ", __func__, mmc_dev); |
65a25b20 | 171 | if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { |
56b34bc6 PM |
172 | cmd_timeout += cmd_timeout; |
173 | printf("timeout increasing to: %u ms.\n", | |
174 | cmd_timeout); | |
175 | } else { | |
176 | puts("timeout.\n"); | |
915ffa52 | 177 | return -ECOMM; |
56b34bc6 | 178 | } |
af62a557 | 179 | } |
56b34bc6 | 180 | time++; |
af62a557 LW |
181 | udelay(1000); |
182 | } | |
183 | ||
184 | mask = SDHCI_INT_RESPONSE; | |
185 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
186 | flags = SDHCI_CMD_RESP_NONE; | |
187 | else if (cmd->resp_type & MMC_RSP_136) | |
188 | flags = SDHCI_CMD_RESP_LONG; | |
189 | else if (cmd->resp_type & MMC_RSP_BUSY) { | |
190 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
17ea3c86 JC |
191 | if (data) |
192 | mask |= SDHCI_INT_DATA_END; | |
af62a557 LW |
193 | } else |
194 | flags = SDHCI_CMD_RESP_SHORT; | |
195 | ||
196 | if (cmd->resp_type & MMC_RSP_CRC) | |
197 | flags |= SDHCI_CMD_CRC; | |
198 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
199 | flags |= SDHCI_CMD_INDEX; | |
200 | if (data) | |
201 | flags |= SDHCI_CMD_DATA; | |
202 | ||
30e6d979 | 203 | /* Set Transfer mode regarding to data flag */ |
af62a557 LW |
204 | if (data != 0) { |
205 | sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); | |
206 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
207 | trans_bytes = data->blocks * data->blocksize; | |
208 | if (data->blocks > 1) | |
209 | mode |= SDHCI_TRNS_MULTI; | |
210 | ||
211 | if (data->flags == MMC_DATA_READ) | |
212 | mode |= SDHCI_TRNS_READ; | |
213 | ||
45a68fe2 | 214 | #ifdef CONFIG_MMC_SDHCI_SDMA |
af62a557 | 215 | if (data->flags == MMC_DATA_READ) |
3c1fcb77 | 216 | start_addr = (unsigned long)data->dest; |
af62a557 | 217 | else |
3c1fcb77 | 218 | start_addr = (unsigned long)data->src; |
af62a557 LW |
219 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && |
220 | (start_addr & 0x7) != 0x0) { | |
221 | is_aligned = 0; | |
3c1fcb77 | 222 | start_addr = (unsigned long)aligned_buffer; |
af62a557 LW |
223 | if (data->flags != MMC_DATA_READ) |
224 | memcpy(aligned_buffer, data->src, trans_bytes); | |
225 | } | |
226 | ||
492d3223 SR |
227 | #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) |
228 | /* | |
229 | * Always use this bounce-buffer when | |
230 | * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined | |
231 | */ | |
232 | is_aligned = 0; | |
233 | start_addr = (unsigned long)aligned_buffer; | |
234 | if (data->flags != MMC_DATA_READ) | |
235 | memcpy(aligned_buffer, data->src, trans_bytes); | |
236 | #endif | |
237 | ||
af62a557 LW |
238 | sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); |
239 | mode |= SDHCI_TRNS_DMA; | |
240 | #endif | |
241 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
242 | data->blocksize), | |
243 | SDHCI_BLOCK_SIZE); | |
244 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); | |
245 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); | |
5e1c23cd KL |
246 | } else if (cmd->resp_type & MMC_RSP_BUSY) { |
247 | sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); | |
af62a557 LW |
248 | } |
249 | ||
250 | sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); | |
45a68fe2 | 251 | #ifdef CONFIG_MMC_SDHCI_SDMA |
fa7720b2 KL |
252 | if (data != 0) { |
253 | trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); | |
254 | flush_cache(start_addr, trans_bytes); | |
255 | } | |
af62a557 LW |
256 | #endif |
257 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); | |
29905a45 | 258 | start = get_timer(0); |
af62a557 LW |
259 | do { |
260 | stat = sdhci_readl(host, SDHCI_INT_STATUS); | |
261 | if (stat & SDHCI_INT_ERROR) | |
262 | break; | |
af62a557 | 263 | |
bae4a1fd MY |
264 | if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { |
265 | if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { | |
266 | return 0; | |
267 | } else { | |
268 | printf("%s: Timeout for status update!\n", | |
269 | __func__); | |
915ffa52 | 270 | return -ETIMEDOUT; |
bae4a1fd | 271 | } |
3a638320 | 272 | } |
bae4a1fd | 273 | } while ((stat & mask) != mask); |
3a638320 | 274 | |
af62a557 LW |
275 | if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { |
276 | sdhci_cmd_done(host, cmd); | |
277 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
278 | } else | |
279 | ret = -1; | |
280 | ||
281 | if (!ret && data) | |
282 | ret = sdhci_transfer_data(host, data, start_addr); | |
283 | ||
13243f2e TB |
284 | if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) |
285 | udelay(1000); | |
286 | ||
af62a557 LW |
287 | stat = sdhci_readl(host, SDHCI_INT_STATUS); |
288 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); | |
289 | if (!ret) { | |
290 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && | |
291 | !is_aligned && (data->flags == MMC_DATA_READ)) | |
292 | memcpy(data->dest, aligned_buffer, trans_bytes); | |
293 | return 0; | |
294 | } | |
295 | ||
296 | sdhci_reset(host, SDHCI_RESET_CMD); | |
297 | sdhci_reset(host, SDHCI_RESET_DATA); | |
298 | if (stat & SDHCI_INT_TIMEOUT) | |
915ffa52 | 299 | return -ETIMEDOUT; |
af62a557 | 300 | else |
915ffa52 | 301 | return -ECOMM; |
af62a557 LW |
302 | } |
303 | ||
304 | static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) | |
305 | { | |
93bfd616 | 306 | struct sdhci_host *host = mmc->priv; |
899fb9e3 | 307 | unsigned int div, clk = 0, timeout; |
af62a557 | 308 | |
79667b7b WY |
309 | /* Wait max 20 ms */ |
310 | timeout = 200; | |
311 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
312 | (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { | |
313 | if (timeout == 0) { | |
314 | printf("%s: Timeout to wait cmd & data inhibit\n", | |
315 | __func__); | |
2cb5d67c | 316 | return -EBUSY; |
79667b7b WY |
317 | } |
318 | ||
319 | timeout--; | |
320 | udelay(100); | |
321 | } | |
322 | ||
899fb9e3 | 323 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
af62a557 LW |
324 | |
325 | if (clock == 0) | |
326 | return 0; | |
327 | ||
113e5dfc | 328 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { |
6dffdbc3 WY |
329 | /* |
330 | * Check if the Host Controller supports Programmable Clock | |
331 | * Mode. | |
332 | */ | |
333 | if (host->clk_mul) { | |
334 | for (div = 1; div <= 1024; div++) { | |
6d0e34bf | 335 | if ((host->max_clk * host->clk_mul / div) |
6dffdbc3 | 336 | <= clock) |
af62a557 LW |
337 | break; |
338 | } | |
6dffdbc3 WY |
339 | |
340 | /* | |
341 | * Set Programmable Clock Mode in the Clock | |
342 | * Control register. | |
343 | */ | |
344 | clk = SDHCI_PROG_CLOCK_MODE; | |
345 | div--; | |
346 | } else { | |
347 | /* Version 3.00 divisors must be a multiple of 2. */ | |
6d0e34bf | 348 | if (host->max_clk <= clock) { |
6dffdbc3 WY |
349 | div = 1; |
350 | } else { | |
351 | for (div = 2; | |
352 | div < SDHCI_MAX_DIV_SPEC_300; | |
353 | div += 2) { | |
6d0e34bf | 354 | if ((host->max_clk / div) <= clock) |
6dffdbc3 WY |
355 | break; |
356 | } | |
357 | } | |
358 | div >>= 1; | |
af62a557 LW |
359 | } |
360 | } else { | |
361 | /* Version 2.00 divisors must be a power of 2. */ | |
362 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { | |
6d0e34bf | 363 | if ((host->max_clk / div) <= clock) |
af62a557 LW |
364 | break; |
365 | } | |
6dffdbc3 | 366 | div >>= 1; |
af62a557 | 367 | } |
af62a557 | 368 | |
bf9c4d14 | 369 | if (host->ops && host->ops->set_clock) |
62226b68 | 370 | host->ops->set_clock(host, div); |
b09ed6e4 | 371 | |
6dffdbc3 | 372 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
af62a557 LW |
373 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
374 | << SDHCI_DIVIDER_HI_SHIFT; | |
375 | clk |= SDHCI_CLOCK_INT_EN; | |
376 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
377 | ||
378 | /* Wait max 20 ms */ | |
379 | timeout = 20; | |
380 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
381 | & SDHCI_CLOCK_INT_STABLE)) { | |
382 | if (timeout == 0) { | |
30e6d979 DR |
383 | printf("%s: Internal clock never stabilised.\n", |
384 | __func__); | |
2cb5d67c | 385 | return -EBUSY; |
af62a557 LW |
386 | } |
387 | timeout--; | |
388 | udelay(1000); | |
389 | } | |
390 | ||
391 | clk |= SDHCI_CLOCK_CARD_EN; | |
392 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) | |
397 | { | |
398 | u8 pwr = 0; | |
399 | ||
400 | if (power != (unsigned short)-1) { | |
401 | switch (1 << power) { | |
402 | case MMC_VDD_165_195: | |
403 | pwr = SDHCI_POWER_180; | |
404 | break; | |
405 | case MMC_VDD_29_30: | |
406 | case MMC_VDD_30_31: | |
407 | pwr = SDHCI_POWER_300; | |
408 | break; | |
409 | case MMC_VDD_32_33: | |
410 | case MMC_VDD_33_34: | |
411 | pwr = SDHCI_POWER_330; | |
412 | break; | |
413 | } | |
414 | } | |
415 | ||
416 | if (pwr == 0) { | |
417 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
418 | return; | |
419 | } | |
420 | ||
421 | pwr |= SDHCI_POWER_ON; | |
422 | ||
423 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
424 | } | |
425 | ||
ef1e4eda SG |
426 | #ifdef CONFIG_DM_MMC_OPS |
427 | static int sdhci_set_ios(struct udevice *dev) | |
428 | { | |
429 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
430 | #else | |
07b0b9c0 | 431 | static int sdhci_set_ios(struct mmc *mmc) |
af62a557 | 432 | { |
ef1e4eda | 433 | #endif |
af62a557 | 434 | u32 ctrl; |
93bfd616 | 435 | struct sdhci_host *host = mmc->priv; |
af62a557 | 436 | |
bf9c4d14 | 437 | if (host->ops && host->ops->set_control_reg) |
62226b68 | 438 | host->ops->set_control_reg(host); |
236bfecf | 439 | |
af62a557 LW |
440 | if (mmc->clock != host->clock) |
441 | sdhci_set_clock(mmc, mmc->clock); | |
442 | ||
443 | /* Set bus width */ | |
444 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
445 | if (mmc->bus_width == 8) { | |
446 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
113e5dfc JC |
447 | if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || |
448 | (host->quirks & SDHCI_QUIRK_USE_WIDE8)) | |
af62a557 LW |
449 | ctrl |= SDHCI_CTRL_8BITBUS; |
450 | } else { | |
f88a429f MR |
451 | if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || |
452 | (host->quirks & SDHCI_QUIRK_USE_WIDE8)) | |
af62a557 LW |
453 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
454 | if (mmc->bus_width == 4) | |
455 | ctrl |= SDHCI_CTRL_4BITBUS; | |
456 | else | |
457 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
458 | } | |
459 | ||
460 | if (mmc->clock > 26000000) | |
461 | ctrl |= SDHCI_CTRL_HISPD; | |
462 | else | |
463 | ctrl &= ~SDHCI_CTRL_HISPD; | |
464 | ||
236bfecf JC |
465 | if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) |
466 | ctrl &= ~SDHCI_CTRL_HISPD; | |
467 | ||
af62a557 | 468 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
07b0b9c0 | 469 | |
210841c6 SR |
470 | /* If available, call the driver specific "post" set_ios() function */ |
471 | if (host->ops && host->ops->set_ios_post) | |
472 | host->ops->set_ios_post(host); | |
473 | ||
ef1e4eda | 474 | return 0; |
af62a557 LW |
475 | } |
476 | ||
6588c78b | 477 | static int sdhci_init(struct mmc *mmc) |
af62a557 | 478 | { |
93bfd616 | 479 | struct sdhci_host *host = mmc->priv; |
af62a557 | 480 | |
8d549b61 MY |
481 | sdhci_reset(host, SDHCI_RESET_ALL); |
482 | ||
af62a557 LW |
483 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { |
484 | aligned_buffer = memalign(8, 512*1024); | |
485 | if (!aligned_buffer) { | |
30e6d979 DR |
486 | printf("%s: Aligned buffer alloc failed!!!\n", |
487 | __func__); | |
2cb5d67c | 488 | return -ENOMEM; |
af62a557 LW |
489 | } |
490 | } | |
491 | ||
93bfd616 | 492 | sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); |
470dcc75 | 493 | |
bf9c4d14 | 494 | if (host->ops && host->ops->get_cd) |
6f88a3a5 | 495 | host->ops->get_cd(host); |
470dcc75 | 496 | |
ce0c1bc1 | 497 | /* Enable only interrupts served by the SD controller */ |
30e6d979 DR |
498 | sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, |
499 | SDHCI_INT_ENABLE); | |
ce0c1bc1 ŁM |
500 | /* Mask all sdhci interrupt sources */ |
501 | sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); | |
af62a557 | 502 | |
af62a557 LW |
503 | return 0; |
504 | } | |
505 | ||
ef1e4eda SG |
506 | #ifdef CONFIG_DM_MMC_OPS |
507 | int sdhci_probe(struct udevice *dev) | |
508 | { | |
509 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
510 | ||
511 | return sdhci_init(mmc); | |
512 | } | |
ab769f22 | 513 | |
ef1e4eda SG |
514 | const struct dm_mmc_ops sdhci_ops = { |
515 | .send_cmd = sdhci_send_command, | |
516 | .set_ios = sdhci_set_ios, | |
517 | }; | |
518 | #else | |
ab769f22 PA |
519 | static const struct mmc_ops sdhci_ops = { |
520 | .send_cmd = sdhci_send_command, | |
521 | .set_ios = sdhci_set_ios, | |
522 | .init = sdhci_init, | |
523 | }; | |
ef1e4eda | 524 | #endif |
ab769f22 | 525 | |
14bed52d | 526 | int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, |
6d0e34bf | 527 | u32 f_max, u32 f_min) |
af62a557 | 528 | { |
6dffdbc3 | 529 | u32 caps, caps_1; |
14bed52d JC |
530 | |
531 | caps = sdhci_readl(host, SDHCI_CAPABILITIES); | |
15bd0995 | 532 | |
45a68fe2 | 533 | #ifdef CONFIG_MMC_SDHCI_SDMA |
15bd0995 MY |
534 | if (!(caps & SDHCI_CAN_DO_SDMA)) { |
535 | printf("%s: Your controller doesn't support SDMA!!\n", | |
536 | __func__); | |
537 | return -EINVAL; | |
538 | } | |
539 | #endif | |
895549a2 JC |
540 | if (host->quirks & SDHCI_QUIRK_REG32_RW) |
541 | host->version = | |
542 | sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; | |
543 | else | |
544 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); | |
14bed52d JC |
545 | |
546 | cfg->name = host->name; | |
2a809093 SG |
547 | #ifndef CONFIG_DM_MMC_OPS |
548 | cfg->ops = &sdhci_ops; | |
af62a557 | 549 | #endif |
6d0e34bf | 550 | if (host->max_clk == 0) { |
14bed52d | 551 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) |
6d0e34bf | 552 | host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> |
2a809093 | 553 | SDHCI_CLOCK_BASE_SHIFT; |
af62a557 | 554 | else |
6d0e34bf | 555 | host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> |
2a809093 | 556 | SDHCI_CLOCK_BASE_SHIFT; |
6d0e34bf | 557 | host->max_clk *= 1000000; |
af62a557 | 558 | } |
6d0e34bf | 559 | if (host->max_clk == 0) { |
6c67954c MY |
560 | printf("%s: Hardware doesn't specify base clock frequency\n", |
561 | __func__); | |
2a809093 | 562 | return -EINVAL; |
6c67954c | 563 | } |
6d0e34bf SH |
564 | if (f_max && (f_max < host->max_clk)) |
565 | cfg->f_max = f_max; | |
566 | else | |
567 | cfg->f_max = host->max_clk; | |
568 | if (f_min) | |
569 | cfg->f_min = f_min; | |
af62a557 | 570 | else { |
14bed52d | 571 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) |
2a809093 | 572 | cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; |
af62a557 | 573 | else |
2a809093 | 574 | cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; |
af62a557 | 575 | } |
2a809093 | 576 | cfg->voltages = 0; |
af62a557 | 577 | if (caps & SDHCI_CAN_VDD_330) |
2a809093 | 578 | cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
af62a557 | 579 | if (caps & SDHCI_CAN_VDD_300) |
2a809093 | 580 | cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
af62a557 | 581 | if (caps & SDHCI_CAN_VDD_180) |
2a809093 | 582 | cfg->voltages |= MMC_VDD_165_195; |
236bfecf | 583 | |
3137e645 MY |
584 | if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) |
585 | cfg->voltages |= host->voltages; | |
586 | ||
2a809093 | 587 | cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; |
3fd0a9ba JC |
588 | |
589 | /* Since Host Controller Version3.0 */ | |
14bed52d | 590 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { |
ecd7b246 JC |
591 | if (!(caps & SDHCI_CAN_DO_8BIT)) |
592 | cfg->host_caps &= ~MMC_MODE_8BIT; | |
3fd0a9ba JC |
593 | |
594 | /* Find out whether clock multiplier is supported */ | |
595 | caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
596 | host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> | |
597 | SDHCI_CLOCK_MUL_SHIFT; | |
1695b29a | 598 | } |
42979002 | 599 | |
14bed52d JC |
600 | if (host->host_caps) |
601 | cfg->host_caps |= host->host_caps; | |
42979002 | 602 | |
2a809093 | 603 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
93bfd616 | 604 | |
2a809093 SG |
605 | return 0; |
606 | } | |
607 | ||
ef1e4eda SG |
608 | #ifdef CONFIG_BLK |
609 | int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) | |
610 | { | |
611 | return mmc_bind(dev, mmc, cfg); | |
612 | } | |
613 | #else | |
6d0e34bf | 614 | int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) |
2a809093 | 615 | { |
6c67954c MY |
616 | int ret; |
617 | ||
6d0e34bf | 618 | ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); |
6c67954c MY |
619 | if (ret) |
620 | return ret; | |
2a809093 | 621 | |
93bfd616 PA |
622 | host->mmc = mmc_create(&host->cfg, host); |
623 | if (host->mmc == NULL) { | |
624 | printf("%s: mmc create fail!\n", __func__); | |
2cb5d67c | 625 | return -ENOMEM; |
93bfd616 | 626 | } |
af62a557 LW |
627 | |
628 | return 0; | |
629 | } | |
ef1e4eda | 630 | #endif |