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ba56f625 WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
265817c7 WD |
3 | * This source code has been made available to you by IBM on an AS-IS |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 9 | * |
265817c7 WD |
10 | * Any user of this software should understand that IBM cannot provide |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
ba56f625 | 13 | * |
265817c7 WD |
14 | * Any person who transfers this source code or any derivative work |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 17 | * |
265817c7 WD |
18 | * COPYRIGHT I B M CORPORATION 1995 |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
20 | *-----------------------------------------------------------------------------*/ |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
265817c7 | 23 | * File Name: enetemac.c |
ba56f625 | 24 | * |
265817c7 | 25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 26 | * |
265817c7 | 27 | * Author: Mark Wisner |
ba56f625 WD |
28 | * |
29 | * Change Activity- | |
30 | * | |
265817c7 WD |
31 | * Date Description of Change BY |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 70 | *-----------------------------------------------------------------------------* |
265817c7 WD |
71 | * 17-Nov-03 travis.sawyer@sandburst.com |
72 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
73 | * in the 440GX. This port should work with the 440GP | |
74 | * (2 EMACs) also | |
75 | * 15-Aug-05 sr@denx.de | |
76 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
77 | now handling all 4xx cpu's. | |
ba56f625 WD |
78 | *-----------------------------------------------------------------------------*/ |
79 | ||
80 | #include <config.h> | |
ba56f625 WD |
81 | #include <common.h> |
82 | #include <net.h> | |
83 | #include <asm/processor.h> | |
2d83476a | 84 | #include <asm/io.h> |
ff768cb1 SR |
85 | #include <asm/cache.h> |
86 | #include <asm/mmu.h> | |
ba56f625 | 87 | #include <commproc.h> |
d6c61aab SR |
88 | #include <ppc4xx.h> |
89 | #include <ppc4xx_enet.h> | |
ba56f625 WD |
90 | #include <405_mal.h> |
91 | #include <miiphy.h> | |
92 | #include <malloc.h> | |
ba56f625 | 93 | |
3a1ed1e1 | 94 | #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) |
d6c61aab SR |
95 | #error "CONFIG_MII has to be defined!" |
96 | #endif | |
ba56f625 | 97 | |
1e25f957 SR |
98 | #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) |
99 | #error "CONFIG_NET_MULTI has to be defined for NetConsole" | |
100 | #endif | |
101 | ||
265817c7 | 102 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
1338e6a8 | 103 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ |
ba56f625 | 104 | |
ba56f625 WD |
105 | /* Ethernet Transmit and Receive Buffers */ |
106 | /* AS.HARNOIS | |
107 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
108 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
109 | */ | |
265817c7 | 110 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
111 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
112 | ||
ba56f625 WD |
113 | /*-----------------------------------------------------------------------------+ |
114 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
115 | * Interrupt Controller). | |
116 | *-----------------------------------------------------------------------------*/ | |
d1631fe1 SR |
117 | #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS)) |
118 | ||
119 | #if defined(CONFIG_HAS_ETH3) | |
120 | #if !defined(CONFIG_440GX) | |
121 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ | |
122 | UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) | |
123 | #else | |
124 | /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */ | |
125 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) | |
126 | #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) | |
127 | #endif /* !defined(CONFIG_440GX) */ | |
128 | #elif defined(CONFIG_HAS_ETH2) | |
129 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ | |
130 | UIC_MASK(ETH_IRQ_NUM(2))) | |
131 | #elif defined(CONFIG_HAS_ETH1) | |
132 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) | |
133 | #else | |
134 | #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0)) | |
135 | #endif | |
136 | ||
137 | /* | |
138 | * Define a default version for UIC_ETHxB for non 440GX so that we can | |
139 | * use common code for all 4xx variants | |
140 | */ | |
141 | #if !defined(UIC_ETHxB) | |
142 | #define UIC_ETHxB 0 | |
143 | #endif | |
144 | ||
145 | #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR) | |
146 | #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE) | |
147 | #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE) | |
148 | #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB) | |
149 | #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB) | |
150 | ||
151 | #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
152 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
153 | ||
154 | /* | |
155 | * We have 3 different interrupt types: | |
156 | * - MAL interrupts indicating successful transfer | |
157 | * - MAL error interrupts indicating MAL related errors | |
158 | * - EMAC interrupts indicating EMAC related errors | |
159 | * | |
160 | * All those interrupts can be on different UIC's, but since | |
161 | * now at least all interrupts from one type are on the same | |
162 | * UIC. Only exception is 440GX where the EMAC interrupts are | |
163 | * spread over two UIC's! | |
164 | */ | |
5de85140 SR |
165 | #if defined(CONFIG_440GX) |
166 | #define UIC_BASE_MAL UIC1_DCR_BASE | |
167 | #define UIC_BASE_MAL_ERR UIC2_DCR_BASE | |
168 | #define UIC_BASE_EMAC UIC2_DCR_BASE | |
169 | #define UIC_BASE_EMAC_B UIC3_DCR_BASE | |
170 | #else | |
d1631fe1 SR |
171 | #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) |
172 | #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) | |
173 | #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) | |
d1631fe1 SR |
174 | #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) |
175 | #endif | |
ba56f625 | 176 | |
d6c61aab | 177 | #undef INFO_4XX_ENET |
ba56f625 | 178 | |
265817c7 WD |
179 | #define BI_PHYMODE_NONE 0 |
180 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a | 181 | #define BI_PHYMODE_RGMII 2 |
887e2ec9 SR |
182 | #define BI_PHYMODE_GMII 3 |
183 | #define BI_PHYMODE_RTBI 4 | |
184 | #define BI_PHYMODE_TBI 5 | |
dbbd1257 | 185 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 186 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 187 | defined(CONFIG_405EX) |
887e2ec9 SR |
188 | #define BI_PHYMODE_SMII 6 |
189 | #define BI_PHYMODE_MII 7 | |
8ac41e3e SR |
190 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
191 | #define BI_PHYMODE_RMII 8 | |
192 | #endif | |
887e2ec9 | 193 | #endif |
78d78236 | 194 | #define BI_PHYMODE_SGMII 9 |
3c74e32a | 195 | |
1941cce7 | 196 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 197 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 198 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 199 | defined(CONFIG_405EX) |
887e2ec9 SR |
200 | #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) |
201 | #endif | |
d6c61aab | 202 | |
8ac41e3e SR |
203 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
204 | #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) | |
205 | #endif | |
206 | ||
207 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
208 | #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ | |
209 | #else | |
210 | #define MAL_RX_CHAN_MUL 1 | |
211 | #endif | |
212 | ||
78d78236 VG |
213 | /*--------------------------------------------------------------------+ |
214 | * Fixed PHY (PHY-less) support for Ethernet Ports. | |
215 | *--------------------------------------------------------------------*/ | |
216 | ||
217 | /* | |
218 | * Some boards do not have a PHY for each ethernet port. These ports | |
219 | * are known as Fixed PHY (or PHY-less) ports. For such ports, set | |
220 | * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and | |
6d0f6bcf | 221 | * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and |
78d78236 VG |
222 | * duplex should be for these ports in the board configuration |
223 | * file. | |
224 | * | |
225 | * For Example: | |
226 | * #define CONFIG_FIXED_PHY 0xFFFFFFFF | |
227 | * | |
228 | * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY | |
229 | * #define CONFIG_PHY1_ADDR 1 | |
230 | * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY | |
231 | * #define CONFIG_PHY3_ADDR 3 | |
232 | * | |
6d0f6bcf | 233 | * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ |
78d78236 VG |
234 | * {devnum, speed, duplex}, |
235 | * | |
6d0f6bcf JCPV |
236 | * #define CONFIG_SYS_FIXED_PHY_PORTS \ |
237 | * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \ | |
238 | * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF) | |
78d78236 VG |
239 | */ |
240 | ||
241 | #ifndef CONFIG_FIXED_PHY | |
242 | #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ | |
243 | #endif | |
244 | ||
6d0f6bcf JCPV |
245 | #ifndef CONFIG_SYS_FIXED_PHY_PORTS |
246 | #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ | |
78d78236 VG |
247 | #endif |
248 | ||
249 | struct fixed_phy_port { | |
250 | unsigned int devnum; /* ethernet port */ | |
251 | unsigned int speed; /* specified speed 10,100 or 1000 */ | |
252 | unsigned int duplex; /* specified duplex FULL or HALF */ | |
253 | }; | |
254 | ||
255 | static const struct fixed_phy_port fixed_phy_port[] = { | |
6d0f6bcf | 256 | CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ |
78d78236 VG |
257 | }; |
258 | ||
ba56f625 WD |
259 | /*-----------------------------------------------------------------------------+ |
260 | * Global variables. TX and RX descriptors and buffers. | |
261 | *-----------------------------------------------------------------------------*/ | |
d6c61aab | 262 | #if !defined(CONFIG_NET_MULTI) |
4f92ac36 | 263 | struct eth_device *emac0_dev = NULL; |
d6c61aab SR |
264 | #endif |
265 | ||
1e25f957 SR |
266 | /* |
267 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
268 | * supported by the cpu) | |
353f2688 SR |
269 | * |
270 | * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the | |
271 | * EMAC count is possible. As it is needed for the Kilauea/Haleakala | |
272 | * 405EX/405EXr eval board, using the same binary. | |
1e25f957 | 273 | */ |
353f2688 SR |
274 | #if defined(CONFIG_BOARD_EMAC_COUNT) |
275 | #define LAST_EMAC_NUM board_emac_count() | |
276 | #else /* CONFIG_BOARD_EMAC_COUNT */ | |
1e25f957 SR |
277 | #if defined(CONFIG_HAS_ETH3) |
278 | #define LAST_EMAC_NUM 4 | |
279 | #elif defined(CONFIG_HAS_ETH2) | |
280 | #define LAST_EMAC_NUM 3 | |
281 | #elif defined(CONFIG_HAS_ETH1) | |
282 | #define LAST_EMAC_NUM 2 | |
283 | #else | |
284 | #define LAST_EMAC_NUM 1 | |
285 | #endif | |
353f2688 | 286 | #endif /* CONFIG_BOARD_EMAC_COUNT */ |
d6c61aab | 287 | |
5fb692ca SR |
288 | /* normal boards start with EMAC0 */ |
289 | #if !defined(CONFIG_EMAC_NR_START) | |
290 | #define CONFIG_EMAC_NR_START 0 | |
291 | #endif | |
292 | ||
ff768cb1 SR |
293 | #define MAL_RX_DESC_SIZE 2048 |
294 | #define MAL_TX_DESC_SIZE 2048 | |
295 | #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) | |
296 | ||
ba56f625 WD |
297 | /*-----------------------------------------------------------------------------+ |
298 | * Prototypes and externals. | |
299 | *-----------------------------------------------------------------------------*/ | |
300 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
301 | ||
302 | int enetInt (struct eth_device *dev); | |
303 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
304 | unsigned long uic, unsigned long maldef, | |
305 | unsigned long mal_errr); | |
306 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
307 | ||
63ff004c MB |
308 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
309 | extern int emac4xx_miiphy_read (char *devname, unsigned char addr, | |
310 | unsigned char reg, unsigned short *value); | |
311 | extern int emac4xx_miiphy_write (char *devname, unsigned char addr, | |
312 | unsigned char reg, unsigned short value); | |
d6c61aab | 313 | |
353f2688 SR |
314 | int board_emac_count(void); |
315 | ||
8ac41e3e SR |
316 | static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) |
317 | { | |
318 | #if defined(CONFIG_440SPE) || \ | |
319 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
320 | defined(CONFIG_405EX) | |
321 | u32 val; | |
322 | ||
323 | mfsdr(sdr_mfr, val); | |
324 | val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); | |
325 | mtsdr(sdr_mfr, val); | |
326 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
327 | u32 val; | |
328 | ||
329 | mfsdr(SDR0_ETH_CFG, val); | |
330 | val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
331 | mtsdr(SDR0_ETH_CFG, val); | |
332 | #endif | |
333 | } | |
334 | ||
335 | static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) | |
336 | { | |
337 | #if defined(CONFIG_440SPE) || \ | |
338 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
339 | defined(CONFIG_405EX) | |
340 | u32 val; | |
341 | ||
342 | mfsdr(sdr_mfr, val); | |
343 | val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); | |
344 | mtsdr(sdr_mfr, val); | |
345 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
346 | u32 val; | |
347 | ||
348 | mfsdr(SDR0_ETH_CFG, val); | |
349 | val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
350 | mtsdr(SDR0_ETH_CFG, val); | |
351 | #endif | |
352 | } | |
353 | ||
ba56f625 | 354 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 355 | | ppc_4xx_eth_halt |
ba56f625 | 356 | | Disable MAL channel, and EMACn |
ba56f625 | 357 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 358 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 359 | { |
d6c61aab | 360 | EMAC_4XX_HW_PST hw_p = dev->priv; |
9ad31989 | 361 | u32 val = 10000; |
ba56f625 | 362 | |
2d83476a | 363 | out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ |
ba56f625 WD |
364 | |
365 | /* 1st reset MAL channel */ | |
366 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab SR |
367 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
368 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
369 | #else | |
ba56f625 | 370 | mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 371 | #endif |
ba56f625 WD |
372 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
373 | ||
374 | /* wait for reset */ | |
d6c61aab | 375 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 | 376 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
9ad31989 SR |
377 | val--; |
378 | if (val == 0) | |
ba56f625 | 379 | break; |
ba56f625 WD |
380 | } |
381 | ||
6c5879f3 | 382 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 383 | emac_loopback_enable(hw_p); |
6c5879f3 | 384 | |
8ac41e3e | 385 | /* EMAC RESET */ |
2d83476a | 386 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
ba56f625 | 387 | |
6c5879f3 | 388 | /* remove clocks for EMAC internal loopback */ |
8ac41e3e | 389 | emac_loopback_disable(hw_p); |
6c5879f3 | 390 | |
a93316c5 | 391 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 392 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 393 | #endif |
c157d8e2 | 394 | |
4c9e8557 SR |
395 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
396 | /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ | |
9ad31989 SR |
397 | mfsdr(SDR0_ETH_CFG, val); |
398 | val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
399 | mtsdr(SDR0_ETH_CFG, val); | |
4c9e8557 SR |
400 | #endif |
401 | ||
ba56f625 WD |
402 | return; |
403 | } | |
404 | ||
846b0dd2 | 405 | #if defined (CONFIG_440GX) |
d6c61aab | 406 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
407 | { |
408 | unsigned long pfc1; | |
409 | unsigned long zmiifer; | |
410 | unsigned long rmiifer; | |
411 | ||
412 | mfsdr(sdr_pfc1, pfc1); | |
413 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); | |
414 | ||
415 | zmiifer = 0; | |
416 | rmiifer = 0; | |
417 | ||
418 | switch (pfc1) { | |
419 | case 1: | |
420 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
421 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
422 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
423 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
424 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
425 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
426 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
427 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
428 | break; | |
429 | case 2: | |
f6e495f5 SR |
430 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); |
431 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
432 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
433 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
855a496f WD |
434 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
435 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
436 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
437 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
438 | break; | |
439 | case 3: | |
440 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
441 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
442 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
443 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
444 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
445 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
446 | break; | |
447 | case 4: | |
448 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
449 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
450 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
451 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
452 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
453 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
454 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
455 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
456 | break; | |
457 | case 5: | |
458 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
459 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
460 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
461 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
462 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
463 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
464 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
465 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
466 | break; | |
467 | case 6: | |
468 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
469 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
470 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
471 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
472 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
473 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
474 | break; |
475 | case 0: | |
476 | default: | |
477 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
478 | rmiifer = 0x0; | |
479 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
480 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
481 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
482 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
483 | break; | |
484 | } | |
485 | ||
486 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
487 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
488 | ||
ff768cb1 SR |
489 | out_be32((void *)ZMII_FER, zmiifer); |
490 | out_be32((void *)RGMII_FER, rmiifer); | |
855a496f WD |
491 | |
492 | return ((int)pfc1); | |
855a496f | 493 | } |
6c5879f3 | 494 | #endif /* CONFIG_440_GX */ |
855a496f | 495 | |
887e2ec9 SR |
496 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
497 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
498 | { | |
499 | unsigned long zmiifer=0x0; | |
37ed6cdd | 500 | unsigned long pfc1; |
887e2ec9 | 501 | |
37ed6cdd MF |
502 | mfsdr(sdr_pfc1, pfc1); |
503 | pfc1 &= SDR0_PFC1_SELECT_MASK; | |
504 | ||
2f15278c | 505 | switch (pfc1) { |
37ed6cdd | 506 | case SDR0_PFC1_SELECT_CONFIG_2: |
887e2ec9 | 507 | /* 1 x GMII port */ |
2d83476a SR |
508 | out_be32((void *)ZMII_FER, 0x00); |
509 | out_be32((void *)RGMII_FER, 0x00000037); | |
887e2ec9 SR |
510 | bis->bi_phymode[0] = BI_PHYMODE_GMII; |
511 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
512 | break; | |
37ed6cdd | 513 | case SDR0_PFC1_SELECT_CONFIG_4: |
887e2ec9 | 514 | /* 2 x RGMII ports */ |
2d83476a SR |
515 | out_be32((void *)ZMII_FER, 0x00); |
516 | out_be32((void *)RGMII_FER, 0x00000055); | |
887e2ec9 SR |
517 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
518 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
519 | break; | |
37ed6cdd | 520 | case SDR0_PFC1_SELECT_CONFIG_6: |
887e2ec9 | 521 | /* 2 x SMII ports */ |
2d83476a SR |
522 | out_be32((void *)ZMII_FER, |
523 | ((ZMII_FER_SMII) << ZMII_FER_V(0)) | | |
524 | ((ZMII_FER_SMII) << ZMII_FER_V(1))); | |
525 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
526 | bis->bi_phymode[0] = BI_PHYMODE_SMII; |
527 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
528 | break; | |
529 | case SDR0_PFC1_SELECT_CONFIG_1_2: | |
530 | /* only 1 x MII supported */ | |
2d83476a SR |
531 | out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); |
532 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
533 | bis->bi_phymode[0] = BI_PHYMODE_MII; |
534 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
887e2ec9 SR |
535 | break; |
536 | default: | |
537 | break; | |
538 | } | |
539 | ||
540 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
2d83476a | 541 | zmiifer = in_be32((void *)ZMII_FER); |
887e2ec9 | 542 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); |
2d83476a | 543 | out_be32((void *)ZMII_FER, zmiifer); |
887e2ec9 SR |
544 | |
545 | return ((int)0x0); | |
546 | } | |
547 | #endif /* CONFIG_440EPX */ | |
548 | ||
dbbd1257 SR |
549 | #if defined(CONFIG_405EX) |
550 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
551 | { | |
1740c1bf | 552 | u32 rgmiifer = 0; |
dbbd1257 SR |
553 | |
554 | /* | |
1740c1bf GE |
555 | * The 405EX(r)'s RGMII bridge can operate in one of several |
556 | * modes, only one of which (2 x RGMII) allows the | |
557 | * simultaneous use of both EMACs on the 405EX. | |
dbbd1257 | 558 | */ |
1740c1bf GE |
559 | |
560 | switch (CONFIG_EMAC_PHY_MODE) { | |
561 | ||
562 | case EMAC_PHY_MODE_NONE: | |
563 | /* No ports */ | |
564 | rgmiifer |= RGMII_FER_DIS << 0; | |
565 | rgmiifer |= RGMII_FER_DIS << 4; | |
566 | out_be32((void *)RGMII_FER, rgmiifer); | |
567 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
568 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
569 | break; | |
570 | case EMAC_PHY_MODE_NONE_RGMII: | |
571 | /* 1 x RGMII port on channel 0 */ | |
572 | rgmiifer |= RGMII_FER_RGMII << 0; | |
573 | rgmiifer |= RGMII_FER_DIS << 4; | |
574 | out_be32((void *)RGMII_FER, rgmiifer); | |
575 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
576 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
577 | break; | |
578 | case EMAC_PHY_MODE_RGMII_NONE: | |
579 | /* 1 x RGMII port on channel 1 */ | |
580 | rgmiifer |= RGMII_FER_DIS << 0; | |
581 | rgmiifer |= RGMII_FER_RGMII << 4; | |
582 | out_be32((void *)RGMII_FER, rgmiifer); | |
583 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
584 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
585 | break; | |
586 | case EMAC_PHY_MODE_RGMII_RGMII: | |
dbbd1257 | 587 | /* 2 x RGMII ports */ |
1740c1bf GE |
588 | rgmiifer |= RGMII_FER_RGMII << 0; |
589 | rgmiifer |= RGMII_FER_RGMII << 4; | |
590 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
591 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
592 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
593 | break; | |
1740c1bf GE |
594 | case EMAC_PHY_MODE_NONE_GMII: |
595 | /* 1 x GMII port on channel 0 */ | |
596 | rgmiifer |= RGMII_FER_GMII << 0; | |
597 | rgmiifer |= RGMII_FER_DIS << 4; | |
598 | out_be32((void *)RGMII_FER, rgmiifer); | |
599 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
600 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
601 | break; | |
602 | case EMAC_PHY_MODE_NONE_MII: | |
603 | /* 1 x MII port on channel 0 */ | |
604 | rgmiifer |= RGMII_FER_MII << 0; | |
605 | rgmiifer |= RGMII_FER_DIS << 4; | |
606 | out_be32((void *)RGMII_FER, rgmiifer); | |
607 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
608 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
609 | break; | |
610 | case EMAC_PHY_MODE_GMII_NONE: | |
611 | /* 1 x GMII port on channel 1 */ | |
612 | rgmiifer |= RGMII_FER_DIS << 0; | |
613 | rgmiifer |= RGMII_FER_GMII << 4; | |
614 | out_be32((void *)RGMII_FER, rgmiifer); | |
615 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
616 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
617 | break; | |
618 | case EMAC_PHY_MODE_MII_NONE: | |
619 | /* 1 x MII port on channel 1 */ | |
620 | rgmiifer |= RGMII_FER_DIS << 0; | |
621 | rgmiifer |= RGMII_FER_MII << 4; | |
622 | out_be32((void *)RGMII_FER, rgmiifer); | |
623 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
624 | bis->bi_phymode[1] = BI_PHYMODE_MII; | |
dbbd1257 SR |
625 | break; |
626 | default: | |
627 | break; | |
628 | } | |
629 | ||
630 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
1740c1bf GE |
631 | rgmiifer = in_be32((void *)RGMII_FER); |
632 | rgmiifer |= (1 << (19-devnum)); | |
633 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
634 | |
635 | return ((int)0x0); | |
636 | } | |
637 | #endif /* CONFIG_405EX */ | |
638 | ||
8ac41e3e SR |
639 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
640 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
641 | { | |
642 | u32 eth_cfg; | |
643 | u32 zmiifer; /* ZMII0_FER reg. */ | |
644 | u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ | |
645 | u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ | |
4c9e8557 | 646 | int mode; |
8ac41e3e SR |
647 | |
648 | zmiifer = 0; | |
649 | rmiifer = 0; | |
650 | rmiifer1 = 0; | |
651 | ||
4c9e8557 SR |
652 | #if defined(CONFIG_460EX) |
653 | mode = 9; | |
78d78236 VG |
654 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
655 | if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && | |
656 | ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0)) | |
657 | mode = 11; /* config SGMII */ | |
4c9e8557 SR |
658 | #else |
659 | mode = 10; | |
78d78236 VG |
660 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
661 | if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && | |
662 | ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) && | |
663 | ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0)) | |
664 | mode = 12; /* config SGMII */ | |
4c9e8557 SR |
665 | #endif |
666 | ||
8ac41e3e SR |
667 | /* TODO: |
668 | * NOTE: 460GT has 2 RGMII bridge cores: | |
669 | * emac0 ------ RGMII0_BASE | |
670 | * | | |
671 | * emac1 -----+ | |
672 | * | |
673 | * emac2 ------ RGMII1_BASE | |
674 | * | | |
675 | * emac3 -----+ | |
676 | * | |
677 | * 460EX has 1 RGMII bridge core: | |
678 | * and RGMII1_BASE is disabled | |
679 | * emac0 ------ RGMII0_BASE | |
680 | * | | |
681 | * emac1 -----+ | |
682 | */ | |
683 | ||
684 | /* | |
685 | * Right now only 2*RGMII is supported. Please extend when needed. | |
686 | * sr - 2008-02-19 | |
78d78236 VG |
687 | * Add SGMII support. |
688 | * vg - 2008-07-28 | |
8ac41e3e | 689 | */ |
4c9e8557 | 690 | switch (mode) { |
8ac41e3e SR |
691 | case 1: |
692 | /* 1 MII - 460EX */ | |
693 | /* GMC0 EMAC4_0, ZMII Bridge */ | |
694 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
695 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
696 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
697 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
698 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
699 | break; | |
700 | case 2: | |
701 | /* 2 MII - 460GT */ | |
702 | /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ | |
703 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
704 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); | |
705 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
706 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
707 | bis->bi_phymode[2] = BI_PHYMODE_MII; | |
708 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
709 | break; | |
710 | case 3: | |
711 | /* 2 RMII - 460EX */ | |
712 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
713 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
714 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
715 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
716 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
717 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
718 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
719 | break; | |
720 | case 4: | |
721 | /* 4 RMII - 460GT */ | |
722 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ | |
723 | /* ZMII Bridge */ | |
724 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
725 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
726 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
727 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
728 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
729 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
730 | bis->bi_phymode[2] = BI_PHYMODE_RMII; | |
731 | bis->bi_phymode[3] = BI_PHYMODE_RMII; | |
732 | break; | |
733 | case 5: | |
734 | /* 2 SMII - 460EX */ | |
735 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
736 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
737 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
738 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
739 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
740 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
741 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
742 | break; | |
743 | case 6: | |
744 | /* 4 SMII - 460GT */ | |
745 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ | |
746 | /* ZMII Bridge */ | |
747 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
748 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
749 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
750 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
751 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
752 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
753 | bis->bi_phymode[2] = BI_PHYMODE_SMII; | |
754 | bis->bi_phymode[3] = BI_PHYMODE_SMII; | |
755 | break; | |
756 | case 7: | |
757 | /* This is the default mode that we want for board bringup - Maple */ | |
758 | /* 1 GMII - 460EX */ | |
759 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
760 | rmiifer |= RGMII_FER_MDIO(0); | |
761 | ||
762 | if (devnum == 0) { | |
763 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
764 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
765 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
766 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
767 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
768 | } else { | |
769 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ | |
770 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
771 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
772 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
773 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
774 | } | |
775 | break; | |
776 | case 8: | |
777 | /* 2 GMII - 460GT */ | |
778 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
779 | /* GMC1 EMAC4_2, RGMII Bridge 1 */ | |
780 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
781 | rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ | |
782 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
783 | rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ | |
784 | ||
785 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
786 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
787 | bis->bi_phymode[2] = BI_PHYMODE_GMII; | |
788 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
789 | break; | |
790 | case 9: | |
791 | /* 2 RGMII - 460EX */ | |
792 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
793 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
794 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
795 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
796 | ||
797 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
798 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
799 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
800 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
801 | break; | |
802 | case 10: | |
803 | /* 4 RGMII - 460GT */ | |
804 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
805 | /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ | |
806 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
807 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
808 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
809 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
810 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
811 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
812 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
813 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
814 | break; | |
78d78236 VG |
815 | case 11: |
816 | /* 2 SGMII - 460EX */ | |
817 | bis->bi_phymode[0] = BI_PHYMODE_SGMII; | |
818 | bis->bi_phymode[1] = BI_PHYMODE_SGMII; | |
819 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
820 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
821 | break; | |
822 | case 12: | |
823 | /* 3 SGMII - 460GT */ | |
824 | bis->bi_phymode[0] = BI_PHYMODE_SGMII; | |
825 | bis->bi_phymode[1] = BI_PHYMODE_SGMII; | |
826 | bis->bi_phymode[2] = BI_PHYMODE_SGMII; | |
827 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
828 | break; | |
8ac41e3e SR |
829 | default: |
830 | break; | |
831 | } | |
832 | ||
833 | /* Set EMAC for MDIO */ | |
834 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
835 | eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; | |
836 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
837 | ||
838 | out_be32((void *)RGMII_FER, rmiifer); | |
839 | #if defined(CONFIG_460GT) | |
840 | out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); | |
841 | #endif | |
842 | ||
843 | /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ | |
844 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
845 | eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
846 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | #endif /* CONFIG_460EX || CONFIG_460GT */ | |
851 | ||
ff768cb1 SR |
852 | static inline void *malloc_aligned(u32 size, u32 align) |
853 | { | |
854 | return (void *)(((u32)malloc(size + align) + align - 1) & | |
855 | ~(align - 1)); | |
856 | } | |
857 | ||
d6c61aab | 858 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 859 | { |
ff768cb1 | 860 | int i; |
d6c61aab | 861 | unsigned long reg = 0; |
ba56f625 WD |
862 | unsigned long msr; |
863 | unsigned long speed; | |
864 | unsigned long duplex; | |
865 | unsigned long failsafe; | |
866 | unsigned mode_reg; | |
867 | unsigned short devnum; | |
868 | unsigned short reg_short; | |
887e2ec9 SR |
869 | #if defined(CONFIG_440GX) || \ |
870 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 871 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 872 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 873 | defined(CONFIG_405EX) |
d6c61aab | 874 | sys_info_t sysinfo; |
887e2ec9 | 875 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 876 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 877 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 878 | defined(CONFIG_405EX) |
6e7fb6ea SR |
879 | int ethgroup = -1; |
880 | #endif | |
6c5879f3 | 881 | #endif |
ff768cb1 SR |
882 | u32 bd_cached; |
883 | u32 bd_uncached = 0; | |
4fae35a5 AG |
884 | #ifdef CONFIG_4xx_DCACHE |
885 | static u32 last_used_ea = 0; | |
886 | #endif | |
e54ec0f0 SR |
887 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
888 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ | |
889 | defined(CONFIG_405EX) | |
890 | int rgmii_channel; | |
891 | #endif | |
6c5879f3 | 892 | |
d6c61aab | 893 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
894 | |
895 | /* before doing anything, figure out if we have a MAC address */ | |
896 | /* if not, bail */ | |
4f92ac36 SR |
897 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
898 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 899 | return -1; |
4f92ac36 | 900 | } |
ba56f625 | 901 | |
887e2ec9 SR |
902 | #if defined(CONFIG_440GX) || \ |
903 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 904 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 905 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 906 | defined(CONFIG_405EX) |
ba56f625 WD |
907 | /* Need to get the OPB frequency so we can access the PHY */ |
908 | get_sys_info (&sysinfo); | |
d6c61aab | 909 | #endif |
ba56f625 | 910 | |
ba56f625 WD |
911 | msr = mfmsr (); |
912 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
913 | ||
914 | devnum = hw_p->devnum; | |
915 | ||
d6c61aab | 916 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
917 | /* AS.HARNOIS |
918 | * We should have : | |
265817c7 | 919 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
920 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
921 | * is possible that new packets (without relationship with | |
922 | * current transfer) have got the time to arrived before | |
923 | * netloop calls eth_halt | |
924 | */ | |
925 | printf ("About preceeding transfer (eth%d):\n" | |
926 | "- Sent packet number %d\n" | |
927 | "- Received packet number %d\n" | |
928 | "- Handled packet number %d\n", | |
929 | hw_p->devnum, | |
930 | hw_p->stats.pkts_tx, | |
931 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
932 | ||
933 | hw_p->stats.pkts_tx = 0; | |
934 | hw_p->stats.pkts_rx = 0; | |
935 | hw_p->stats.pkts_handled = 0; | |
6c5879f3 | 936 | hw_p->print_speed = 1; /* print speed message again next time */ |
ba56f625 WD |
937 | #endif |
938 | ||
265817c7 WD |
939 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
940 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
941 | |
942 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
943 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
944 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
945 | ||
946 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
947 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
948 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
949 | ||
6c5879f3 | 950 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
951 | /* set RMII mode */ |
952 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
953 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
954 | /* NOTE: only one emac at a time */ | |
955 | reg = 0; | |
2d83476a | 956 | out_be32((void *)ZMII_FER, 0); |
ba56f625 | 957 | udelay (100); |
ba56f625 | 958 | |
8ac41e3e | 959 | #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
2d83476a | 960 | out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
8ac41e3e SR |
961 | #elif defined(CONFIG_440GX) || \ |
962 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
963 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
d6c61aab | 964 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
0e6d798c | 965 | #endif |
c57c7980 | 966 | |
2d83476a | 967 | out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
6e7fb6ea | 968 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
dbbd1257 SR |
969 | #if defined(CONFIG_405EX) |
970 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); | |
971 | #endif | |
d6c61aab | 972 | |
8ac41e3e | 973 | sync(); |
0e6d798c | 974 | |
6c5879f3 | 975 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 976 | emac_loopback_enable(hw_p); |
0e6d798c | 977 | |
8ac41e3e | 978 | /* EMAC RESET */ |
2d83476a | 979 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
ba56f625 | 980 | |
8ac41e3e SR |
981 | /* remove clocks for EMAC internal loopback */ |
982 | emac_loopback_disable(hw_p); | |
983 | ||
ba56f625 | 984 | failsafe = 1000; |
2d83476a | 985 | while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { |
ba56f625 WD |
986 | udelay (1000); |
987 | failsafe--; | |
988 | } | |
887e2ec9 SR |
989 | if (failsafe <= 0) |
990 | printf("\nProblem resetting EMAC!\n"); | |
ba56f625 | 991 | |
887e2ec9 SR |
992 | #if defined(CONFIG_440GX) || \ |
993 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 994 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 995 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 996 | defined(CONFIG_405EX) |
ba56f625 WD |
997 | /* Whack the M1 register */ |
998 | mode_reg = 0x0; | |
999 | mode_reg &= ~0x00000038; | |
1000 | if (sysinfo.freqOPB <= 50000000); | |
1001 | else if (sysinfo.freqOPB <= 66666667) | |
1002 | mode_reg |= EMAC_M1_OBCI_66; | |
1003 | else if (sysinfo.freqOPB <= 83333333) | |
1004 | mode_reg |= EMAC_M1_OBCI_83; | |
1005 | else if (sysinfo.freqOPB <= 100000000) | |
1006 | mode_reg |= EMAC_M1_OBCI_100; | |
1007 | else | |
1008 | mode_reg |= EMAC_M1_OBCI_GT100; | |
1009 | ||
2d83476a | 1010 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
6e7fb6ea | 1011 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
ba56f625 | 1012 | |
78d78236 VG |
1013 | #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ |
1014 | defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR) | |
1015 | if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { | |
1016 | /* | |
1017 | * In SGMII mode, GPCS access is needed for | |
1018 | * communication with the internal SGMII SerDes. | |
1019 | */ | |
1020 | switch (devnum) { | |
1021 | #if defined(CONFIG_GPCS_PHY_ADDR) | |
1022 | case 0: | |
1023 | reg = CONFIG_GPCS_PHY_ADDR; | |
1024 | break; | |
1025 | #endif | |
1026 | #if defined(CONFIG_GPCS_PHY1_ADDR) | |
1027 | case 1: | |
1028 | reg = CONFIG_GPCS_PHY1_ADDR; | |
1029 | break; | |
1030 | #endif | |
1031 | #if defined(CONFIG_GPCS_PHY2_ADDR) | |
1032 | case 2: | |
1033 | reg = CONFIG_GPCS_PHY2_ADDR; | |
1034 | break; | |
1035 | #endif | |
1036 | #if defined(CONFIG_GPCS_PHY3_ADDR) | |
1037 | case 3: | |
1038 | reg = CONFIG_GPCS_PHY3_ADDR; | |
1039 | break; | |
1040 | #endif | |
1041 | } | |
1042 | ||
1043 | mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); | |
1044 | mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg); | |
1045 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); | |
1046 | ||
1047 | /* Configure GPCS interface to recommended setting for SGMII */ | |
1048 | miiphy_reset(dev->name, reg); | |
1049 | miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */ | |
1050 | miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */ | |
1051 | miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */ | |
1052 | } | |
1053 | #endif /* defined(CONFIG_GPCS_PHY_ADDR) */ | |
1054 | ||
ba56f625 WD |
1055 | /* wait for PHY to complete auto negotiation */ |
1056 | reg_short = 0; | |
ba56f625 WD |
1057 | switch (devnum) { |
1058 | case 0: | |
1059 | reg = CONFIG_PHY_ADDR; | |
1060 | break; | |
d6c61aab | 1061 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
1062 | case 1: |
1063 | reg = CONFIG_PHY1_ADDR; | |
1064 | break; | |
d6c61aab | 1065 | #endif |
4c9e8557 | 1066 | #if defined (CONFIG_PHY2_ADDR) |
ba56f625 WD |
1067 | case 2: |
1068 | reg = CONFIG_PHY2_ADDR; | |
1069 | break; | |
4c9e8557 SR |
1070 | #endif |
1071 | #if defined (CONFIG_PHY3_ADDR) | |
ba56f625 WD |
1072 | case 3: |
1073 | reg = CONFIG_PHY3_ADDR; | |
1074 | break; | |
1075 | #endif | |
1076 | default: | |
1077 | reg = CONFIG_PHY_ADDR; | |
1078 | break; | |
1079 | } | |
1080 | ||
3c74e32a WD |
1081 | bis->bi_phynum[devnum] = reg; |
1082 | ||
78d78236 VG |
1083 | if (reg == CONFIG_FIXED_PHY) |
1084 | goto get_speed; | |
1085 | ||
d6c61aab | 1086 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
1087 | /* |
1088 | * Reset the phy, only if its the first time through | |
1089 | * otherwise, just check the speeds & feeds | |
1090 | */ | |
1091 | if (hw_p->first_init == 0) { | |
ec0c2ec7 | 1092 | #if defined(CONFIG_M88E1111_PHY) |
887e2ec9 SR |
1093 | miiphy_write (dev->name, reg, 0x14, 0x0ce3); |
1094 | miiphy_write (dev->name, reg, 0x18, 0x4101); | |
1095 | miiphy_write (dev->name, reg, 0x09, 0x0e00); | |
1096 | miiphy_write (dev->name, reg, 0x04, 0x01e1); | |
1097 | #endif | |
78d78236 VG |
1098 | #if defined(CONFIG_M88E1112_PHY) |
1099 | if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { | |
1100 | /* | |
1101 | * Marvell 88E1112 PHY needs to have the SGMII MAC | |
1102 | * interace (page 2) properly configured to | |
1103 | * communicate with the 460EX/GT GPCS interface. | |
1104 | */ | |
1105 | ||
1106 | /* Set access to Page 2 */ | |
1107 | miiphy_write(dev->name, reg, 0x16, 0x0002); | |
1108 | ||
1109 | miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */ | |
1110 | miiphy_read(dev->name, reg, 0x1a, ®_short); | |
1111 | reg_short |= 0x8000; /* bypass Auto-Negotiation */ | |
1112 | miiphy_write(dev->name, reg, 0x1a, reg_short); | |
1113 | miiphy_reset(dev->name, reg); /* reset MAC interface */ | |
1114 | ||
1115 | /* Reset access to Page 0 */ | |
1116 | miiphy_write(dev->name, reg, 0x16, 0x0000); | |
1117 | } | |
1118 | #endif /* defined(CONFIG_M88E1112_PHY) */ | |
63ff004c | 1119 | miiphy_reset (dev->name, reg); |
ba56f625 | 1120 | |
887e2ec9 SR |
1121 | #if defined(CONFIG_440GX) || \ |
1122 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1123 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1124 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1125 | defined(CONFIG_405EX) |
887e2ec9 | 1126 | |
0e6d798c | 1127 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 1128 | /* |
17f50f22 SR |
1129 | * Cicada 8201 PHY needs to have an extended register whacked |
1130 | * for RGMII mode. | |
fc1cfcdb | 1131 | */ |
887e2ec9 | 1132 | if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { |
b79316f2 | 1133 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 1134 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 1135 | #else |
63ff004c | 1136 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 1137 | #endif |
17f50f22 SR |
1138 | /* |
1139 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
1140 | * Interoperability problem with Intel 82547EI phys | |
1141 | * This work around (provided by Vitesse) changes | |
1142 | * the default timer convergence from 8ms to 12ms | |
1143 | */ | |
63ff004c MB |
1144 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
1145 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
1146 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
1147 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
1148 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
1149 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
1150 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
1151 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
1152 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
1153 | /* end Vitesse/Cicada errata */ |
1154 | } | |
6ca8646c | 1155 | #endif /* defined(CONFIG_CIS8201_PHY) */ |
5fb692ca SR |
1156 | |
1157 | #if defined(CONFIG_ET1011C_PHY) | |
1158 | /* | |
1159 | * Agere ET1011c PHY needs to have an extended register whacked | |
1160 | * for RGMII mode. | |
1161 | */ | |
1162 | if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { | |
1163 | miiphy_read (dev->name, reg, 0x16, ®_short); | |
1164 | reg_short &= ~(0x7); | |
1165 | reg_short |= 0x6; /* RGMII DLL Delay*/ | |
1166 | miiphy_write (dev->name, reg, 0x16, reg_short); | |
1167 | ||
1168 | miiphy_read (dev->name, reg, 0x17, ®_short); | |
1169 | reg_short &= ~(0x40); | |
1170 | miiphy_write (dev->name, reg, 0x17, reg_short); | |
1171 | ||
1172 | miiphy_write(dev->name, reg, 0x1c, 0x74f0); | |
1173 | } | |
6ca8646c | 1174 | #endif /* defined(CONFIG_ET1011C_PHY) */ |
5fb692ca | 1175 | |
6ca8646c | 1176 | #endif /* defined(CONFIG_440GX) ... */ |
a06752e3 | 1177 | /* Start/Restart autonegotiation */ |
63ff004c | 1178 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
1179 | udelay (1000); |
1180 | } | |
d6c61aab | 1181 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 1182 | |
63ff004c | 1183 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
1184 | |
1185 | /* | |
0e6d798c | 1186 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 WD |
1187 | */ |
1188 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
1189 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
1190 | puts ("Waiting for PHY auto negotiation to complete"); | |
1191 | i = 0; | |
1192 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
1193 | /* | |
1194 | * Timeout reached ? | |
1195 | */ | |
1196 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
1197 | puts (" TIMEOUT !\n"); | |
1198 | break; | |
1199 | } | |
1200 | ||
1201 | if ((i++ % 1000) == 0) { | |
1202 | putc ('.'); | |
1203 | } | |
1204 | udelay (1000); /* 1 ms */ | |
63ff004c | 1205 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
1206 | } |
1207 | puts (" done\n"); | |
1208 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
1209 | } | |
d6c61aab | 1210 | |
78d78236 VG |
1211 | get_speed: |
1212 | if (reg == CONFIG_FIXED_PHY) { | |
1213 | for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { | |
1214 | if (devnum == fixed_phy_port[i].devnum) { | |
1215 | speed = fixed_phy_port[i].speed; | |
1216 | duplex = fixed_phy_port[i].duplex; | |
1217 | break; | |
1218 | } | |
1219 | } | |
1220 | ||
1221 | if (i == ARRAY_SIZE(fixed_phy_port)) { | |
1222 | printf("ERROR: PHY (%s) not configured correctly!\n", | |
1223 | dev->name); | |
1224 | return -1; | |
1225 | } | |
1226 | } else { | |
1227 | speed = miiphy_speed(dev->name, reg); | |
1228 | duplex = miiphy_duplex(dev->name, reg); | |
1229 | } | |
ba56f625 WD |
1230 | |
1231 | if (hw_p->print_speed) { | |
1232 | hw_p->print_speed = 0; | |
5fb692ca SR |
1233 | printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", |
1234 | (int) speed, (duplex == HALF) ? "HALF" : "FULL", | |
1235 | hw_p->devnum); | |
ba56f625 WD |
1236 | } |
1237 | ||
8ac41e3e SR |
1238 | #if defined(CONFIG_440) && \ |
1239 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ | |
1240 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | |
1241 | !defined(CONFIG_460EX) && !defined(CONFIG_460GT) | |
846b0dd2 | 1242 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
1243 | mfsdr(sdr_mfr, reg); |
1244 | if (speed == 100) { | |
1245 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
1246 | } else { | |
1247 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
1248 | } | |
1249 | mtsdr(sdr_mfr, reg); | |
1250 | #endif | |
c57c7980 | 1251 | |
ba56f625 | 1252 | /* Set ZMII/RGMII speed according to the phy link speed */ |
ff768cb1 | 1253 | reg = in_be32((void *)ZMII_SSR); |
855a496f | 1254 | if ( (speed == 100) || (speed == 1000) ) |
ff768cb1 | 1255 | out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
ba56f625 | 1256 | else |
ff768cb1 | 1257 | out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
ba56f625 WD |
1258 | |
1259 | if ((devnum == 2) || (devnum == 3)) { | |
1260 | if (speed == 1000) | |
1261 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
1262 | else if (speed == 100) | |
1263 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
887e2ec9 | 1264 | else if (speed == 10) |
ba56f625 | 1265 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); |
887e2ec9 SR |
1266 | else { |
1267 | printf("Error in RGMII Speed\n"); | |
1268 | return -1; | |
1269 | } | |
ff768cb1 | 1270 | out_be32((void *)RGMII_SSR, reg); |
ba56f625 | 1271 | } |
6e7fb6ea | 1272 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
ba56f625 | 1273 | |
dbbd1257 | 1274 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 1275 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1276 | defined(CONFIG_405EX) |
e54ec0f0 SR |
1277 | if (devnum >= 2) |
1278 | rgmii_channel = devnum - 2; | |
1279 | else | |
1280 | rgmii_channel = devnum; | |
1281 | ||
887e2ec9 | 1282 | if (speed == 1000) |
e54ec0f0 | 1283 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1284 | else if (speed == 100) |
e54ec0f0 | 1285 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1286 | else if (speed == 10) |
e54ec0f0 | 1287 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 SR |
1288 | else { |
1289 | printf("Error in RGMII Speed\n"); | |
1290 | return -1; | |
1291 | } | |
2d83476a | 1292 | out_be32((void *)RGMII_SSR, reg); |
8ac41e3e SR |
1293 | #if defined(CONFIG_460GT) |
1294 | if ((devnum == 2) || (devnum == 3)) | |
1295 | out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); | |
1296 | #endif | |
887e2ec9 SR |
1297 | #endif |
1298 | ||
ba56f625 | 1299 | /* set the Mal configuration reg */ |
887e2ec9 SR |
1300 | #if defined(CONFIG_440GX) || \ |
1301 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1302 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1303 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1304 | defined(CONFIG_405EX) |
17f50f22 SR |
1305 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
1306 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); | |
1307 | #else | |
1308 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
ba56f625 | 1309 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 SR |
1310 | if (get_pvr() == PVR_440GP_RB) { |
1311 | mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); | |
1312 | } | |
1313 | #endif | |
ba56f625 | 1314 | |
ba56f625 WD |
1315 | /* |
1316 | * Malloc MAL buffer desciptors, make sure they are | |
1317 | * aligned on cache line boundary size | |
1318 | * (401/403/IOP480 = 16, 405 = 32) | |
1319 | * and doesn't cross cache block boundaries. | |
1320 | */ | |
ff768cb1 SR |
1321 | if (hw_p->first_init == 0) { |
1322 | debug("*** Allocating descriptor memory ***\n"); | |
ba56f625 | 1323 | |
ff768cb1 SR |
1324 | bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); |
1325 | if (!bd_cached) { | |
b002144e | 1326 | printf("%s: Error allocating MAL descriptor buffers!\n", __func__); |
ff768cb1 SR |
1327 | return -1; |
1328 | } | |
b79316f2 | 1329 | |
ff768cb1 | 1330 | #ifdef CONFIG_4xx_DCACHE |
ba79fde5 | 1331 | flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); |
4fae35a5 | 1332 | if (!last_used_ea) |
6d0f6bcf JCPV |
1333 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1334 | bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE; | |
5e3dca57 | 1335 | #else |
4fae35a5 | 1336 | bd_uncached = bis->bi_memsize; |
5e3dca57 | 1337 | #endif |
4fae35a5 AG |
1338 | else |
1339 | bd_uncached = last_used_ea + MAL_ALLOC_SIZE; | |
1340 | ||
1341 | last_used_ea = bd_uncached; | |
ff768cb1 SR |
1342 | program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, |
1343 | TLB_WORD2_I_ENABLE); | |
1344 | #else | |
1345 | bd_uncached = bd_cached; | |
1346 | #endif | |
1347 | hw_p->tx_phys = bd_cached; | |
1348 | hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; | |
1349 | hw_p->tx = (mal_desc_t *)(bd_uncached); | |
1350 | hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); | |
1351 | debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx); | |
ba56f625 WD |
1352 | } |
1353 | ||
1354 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
1355 | hw_p->tx[i].ctrl = 0; | |
1356 | hw_p->tx[i].data_len = 0; | |
ff768cb1 SR |
1357 | if (hw_p->first_init == 0) |
1358 | hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, | |
1359 | L1_CACHE_BYTES); | |
ba56f625 WD |
1360 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
1361 | if ((NUM_TX_BUFF - 1) == i) | |
1362 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
1363 | hw_p->tx_run[i] = -1; | |
ff768cb1 | 1364 | debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr); |
ba56f625 WD |
1365 | } |
1366 | ||
1367 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
1368 | hw_p->rx[i].ctrl = 0; | |
1369 | hw_p->rx[i].data_len = 0; | |
ff768cb1 | 1370 | hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; |
ba56f625 WD |
1371 | if ((NUM_RX_BUFF - 1) == i) |
1372 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
1373 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
1374 | hw_p->rx_ready[i] = -1; | |
ff768cb1 | 1375 | debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr); |
ba56f625 WD |
1376 | } |
1377 | ||
1378 | reg = 0x00000000; | |
1379 | ||
1380 | reg |= dev->enetaddr[0]; /* set high address */ | |
1381 | reg = reg << 8; | |
1382 | reg |= dev->enetaddr[1]; | |
1383 | ||
2d83476a | 1384 | out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); |
ba56f625 WD |
1385 | |
1386 | reg = 0x00000000; | |
1387 | reg |= dev->enetaddr[2]; /* set low address */ | |
1388 | reg = reg << 8; | |
1389 | reg |= dev->enetaddr[3]; | |
1390 | reg = reg << 8; | |
1391 | reg |= dev->enetaddr[4]; | |
1392 | reg = reg << 8; | |
1393 | reg |= dev->enetaddr[5]; | |
1394 | ||
2d83476a | 1395 | out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); |
ba56f625 WD |
1396 | |
1397 | switch (devnum) { | |
1398 | case 1: | |
1399 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1400 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
ff768cb1 | 1401 | mtdcr (maltxctp2r, hw_p->tx_phys); |
c157d8e2 | 1402 | #else |
ff768cb1 | 1403 | mtdcr (maltxctp1r, hw_p->tx_phys); |
c157d8e2 | 1404 | #endif |
d6c61aab | 1405 | #if defined(CONFIG_440) |
c157d8e2 | 1406 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 1407 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 1408 | #endif |
8ac41e3e SR |
1409 | |
1410 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
4c9e8557 | 1411 | mtdcr (malrxctp8r, hw_p->rx_phys); |
8ac41e3e SR |
1412 | /* set RX buffer size */ |
1413 | mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); | |
1414 | #else | |
ff768cb1 | 1415 | mtdcr (malrxctp1r, hw_p->rx_phys); |
ba56f625 WD |
1416 | /* set RX buffer size */ |
1417 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
8ac41e3e | 1418 | #endif |
ba56f625 | 1419 | break; |
846b0dd2 | 1420 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1421 | case 2: |
1422 | /* setup MAL tx & rx channel pointers */ | |
1423 | mtdcr (maltxbattr, 0x0); | |
ba56f625 | 1424 | mtdcr (malrxbattr, 0x0); |
ff768cb1 SR |
1425 | mtdcr (maltxctp2r, hw_p->tx_phys); |
1426 | mtdcr (malrxctp2r, hw_p->rx_phys); | |
ba56f625 WD |
1427 | /* set RX buffer size */ |
1428 | mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); | |
1429 | break; | |
1430 | case 3: | |
1431 | /* setup MAL tx & rx channel pointers */ | |
1432 | mtdcr (maltxbattr, 0x0); | |
ff768cb1 | 1433 | mtdcr (maltxctp3r, hw_p->tx_phys); |
ba56f625 | 1434 | mtdcr (malrxbattr, 0x0); |
ff768cb1 | 1435 | mtdcr (malrxctp3r, hw_p->rx_phys); |
ba56f625 WD |
1436 | /* set RX buffer size */ |
1437 | mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); | |
1438 | break; | |
c57c7980 | 1439 | #endif /* CONFIG_440GX */ |
4c9e8557 SR |
1440 | #if defined (CONFIG_460GT) |
1441 | case 2: | |
1442 | /* setup MAL tx & rx channel pointers */ | |
1443 | mtdcr (maltxbattr, 0x0); | |
1444 | mtdcr (malrxbattr, 0x0); | |
1445 | mtdcr (maltxctp2r, hw_p->tx_phys); | |
1446 | mtdcr (malrxctp16r, hw_p->rx_phys); | |
1447 | /* set RX buffer size */ | |
1448 | mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); | |
1449 | break; | |
1450 | case 3: | |
1451 | /* setup MAL tx & rx channel pointers */ | |
1452 | mtdcr (maltxbattr, 0x0); | |
1453 | mtdcr (malrxbattr, 0x0); | |
1454 | mtdcr (maltxctp3r, hw_p->tx_phys); | |
1455 | mtdcr (malrxctp24r, hw_p->rx_phys); | |
1456 | /* set RX buffer size */ | |
1457 | mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); | |
1458 | break; | |
1459 | #endif /* CONFIG_460GT */ | |
ba56f625 WD |
1460 | case 0: |
1461 | default: | |
1462 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1463 | #if defined(CONFIG_440) |
ba56f625 | 1464 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 1465 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 1466 | #endif |
ff768cb1 SR |
1467 | mtdcr (maltxctp0r, hw_p->tx_phys); |
1468 | mtdcr (malrxctp0r, hw_p->rx_phys); | |
ba56f625 WD |
1469 | /* set RX buffer size */ |
1470 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
1471 | break; | |
1472 | } | |
1473 | ||
1474 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 1475 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
1476 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
1477 | #else | |
ba56f625 | 1478 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 1479 | #endif |
ba56f625 WD |
1480 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
1481 | ||
1482 | /* set transmit enable & receive enable */ | |
2d83476a | 1483 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
ba56f625 | 1484 | |
2d83476a | 1485 | mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); |
76957cb3 SR |
1486 | |
1487 | /* set rx-/tx-fifo size */ | |
1488 | mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; | |
ba56f625 WD |
1489 | |
1490 | /* set speed */ | |
6e7fb6ea | 1491 | if (speed == _1000BASET) { |
738815c0 SR |
1492 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
1493 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
6e7fb6ea | 1494 | unsigned long pfc1; |
887e2ec9 | 1495 | |
6e7fb6ea SR |
1496 | mfsdr (sdr_pfc1, pfc1); |
1497 | pfc1 |= SDR0_PFC1_EM_1000; | |
1498 | mtsdr (sdr_pfc1, pfc1); | |
1499 | #endif | |
855a496f | 1500 | mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; |
6e7fb6ea | 1501 | } else if (speed == _100BASET) |
ba56f625 WD |
1502 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; |
1503 | else | |
1504 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
1505 | if (duplex == FULL) | |
1506 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
1507 | ||
2d83476a | 1508 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
ba56f625 WD |
1509 | |
1510 | /* Enable broadcast and indvidual address */ | |
1511 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
2d83476a | 1512 | out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); |
ba56f625 WD |
1513 | |
1514 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
1515 | ||
1516 | /* set transmit request threshold register */ | |
2d83476a | 1517 | out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
ba56f625 | 1518 | |
265817c7 | 1519 | /* set receive low/high water mark register */ |
d6c61aab | 1520 | #if defined(CONFIG_440) |
6c5879f3 | 1521 | /* 440s has a 64 byte burst length */ |
2d83476a | 1522 | out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
d6c61aab SR |
1523 | #else |
1524 | /* 405s have a 16 byte burst length */ | |
2d83476a | 1525 | out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
d6c61aab | 1526 | #endif /* defined(CONFIG_440) */ |
2d83476a | 1527 | out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
ba56f625 WD |
1528 | |
1529 | /* Set fifo limit entry in tx mode 0 */ | |
2d83476a | 1530 | out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); |
ba56f625 | 1531 | /* Frame gap set */ |
2d83476a | 1532 | out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
ba56f625 WD |
1533 | |
1534 | /* Set EMAC IER */ | |
d6c61aab | 1535 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
1536 | if (speed == _100BASET) |
1537 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
1538 | ||
2d83476a SR |
1539 | out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ |
1540 | out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
ba56f625 WD |
1541 | |
1542 | if (hw_p->first_init == 0) { | |
1543 | /* | |
1544 | * Connect interrupt service routines | |
1545 | */ | |
dbbd1257 SR |
1546 | irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), |
1547 | (interrupt_handler_t *) enetInt, dev); | |
ba56f625 | 1548 | } |
ba56f625 WD |
1549 | |
1550 | mtmsr (msr); /* enable interrupts again */ | |
1551 | ||
1552 | hw_p->bis = bis; | |
1553 | hw_p->first_init = 1; | |
1554 | ||
802b769b | 1555 | return 0; |
ba56f625 WD |
1556 | } |
1557 | ||
1558 | ||
d6c61aab | 1559 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
ba56f625 WD |
1560 | int len) |
1561 | { | |
1562 | struct enet_frame *ef_ptr; | |
1563 | ulong time_start, time_now; | |
1564 | unsigned long temp_txm0; | |
d6c61aab | 1565 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1566 | |
1567 | ef_ptr = (struct enet_frame *) ptr; | |
1568 | ||
1569 | /*-----------------------------------------------------------------------+ | |
1570 | * Copy in our address into the frame. | |
1571 | *-----------------------------------------------------------------------*/ | |
1572 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
1573 | ||
1574 | /*-----------------------------------------------------------------------+ | |
1575 | * If frame is too long or too short, modify length. | |
1576 | *-----------------------------------------------------------------------*/ | |
1577 | /* TBS: where does the fragment go???? */ | |
1578 | if (len > ENET_MAX_MTU) | |
1579 | len = ENET_MAX_MTU; | |
1580 | ||
1581 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
1582 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
ba79fde5 | 1583 | flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); |
ba56f625 WD |
1584 | |
1585 | /*-----------------------------------------------------------------------+ | |
1586 | * set TX Buffer busy, and send it | |
1587 | *-----------------------------------------------------------------------*/ | |
1588 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
1589 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
1590 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
1591 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
1592 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
1593 | ||
1594 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
1595 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
1596 | ||
8ac41e3e | 1597 | sync(); |
ba56f625 | 1598 | |
2d83476a SR |
1599 | out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, |
1600 | in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
d6c61aab | 1601 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1602 | hw_p->stats.pkts_tx++; |
1603 | #endif | |
1604 | ||
1605 | /*-----------------------------------------------------------------------+ | |
1606 | * poll unitl the packet is sent and then make sure it is OK | |
1607 | *-----------------------------------------------------------------------*/ | |
1608 | time_start = get_timer (0); | |
1609 | while (1) { | |
2d83476a | 1610 | temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); |
ba56f625 WD |
1611 | /* loop until either TINT turns on or 3 seconds elapse */ |
1612 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
1613 | /* transmit is done, so now check for errors | |
1614 | * If there is an error, an interrupt should | |
1615 | * happen when we return | |
1616 | */ | |
1617 | time_now = get_timer (0); | |
1618 | if ((time_now - time_start) > 3000) { | |
1619 | return (-1); | |
1620 | } | |
1621 | } else { | |
1622 | return (len); | |
1623 | } | |
1624 | } | |
1625 | } | |
1626 | ||
ba56f625 WD |
1627 | int enetInt (struct eth_device *dev) |
1628 | { | |
1629 | int serviced; | |
1630 | int rc = -1; /* default to not us */ | |
d1631fe1 SR |
1631 | u32 mal_isr; |
1632 | u32 emac_isr = 0; | |
1633 | u32 mal_eob; | |
1634 | u32 uic_mal; | |
1635 | u32 uic_mal_err; | |
1636 | u32 uic_emac; | |
1637 | u32 uic_emac_b; | |
d6c61aab | 1638 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
1639 | |
1640 | /* | |
1641 | * Because the mal is generic, we need to get the current | |
1642 | * eth device | |
1643 | */ | |
d6c61aab SR |
1644 | #if defined(CONFIG_NET_MULTI) |
1645 | dev = eth_get_dev(); | |
1646 | #else | |
1647 | dev = emac0_dev; | |
1648 | #endif | |
ba56f625 WD |
1649 | |
1650 | hw_p = dev->priv; | |
1651 | ||
ba56f625 WD |
1652 | /* enter loop that stays in interrupt code until nothing to service */ |
1653 | do { | |
1654 | serviced = 0; | |
1655 | ||
d1631fe1 SR |
1656 | uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR); |
1657 | uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR); | |
1658 | uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR); | |
1659 | uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR); | |
887e2ec9 | 1660 | |
d1631fe1 SR |
1661 | if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB)) |
1662 | && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) | |
1663 | && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) { | |
ba56f625 WD |
1664 | /* not for us */ |
1665 | return (rc); | |
1666 | } | |
d1631fe1 | 1667 | |
ba56f625 | 1668 | /* get and clear controller status interrupts */ |
d1631fe1 SR |
1669 | /* look at MAL and EMAC error interrupts */ |
1670 | if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { | |
1671 | /* we have a MAL error interrupt */ | |
1672 | mal_isr = mfdcr(malesr); | |
1673 | mal_err(dev, mal_isr, uic_mal_err, | |
1674 | MAL_UIC_DEF, MAL_UIC_ERR); | |
ba56f625 | 1675 | |
d1631fe1 SR |
1676 | /* clear MAL error interrupt status bits */ |
1677 | mtdcr(UIC_BASE_MAL_ERR + UIC_SR, | |
1678 | UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE); | |
ba56f625 | 1679 | |
d1631fe1 | 1680 | return -1; |
ba56f625 WD |
1681 | } |
1682 | ||
d1631fe1 SR |
1683 | /* look for EMAC errors */ |
1684 | if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { | |
1685 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); | |
1686 | emac_err(dev, emac_isr); | |
6e7fb6ea | 1687 | |
d1631fe1 SR |
1688 | /* clear EMAC error interrupt status bits */ |
1689 | mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx); | |
1690 | mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB); | |
6e7fb6ea | 1691 | |
d1631fe1 | 1692 | return -1; |
ba56f625 | 1693 | } |
d6c61aab | 1694 | |
d1631fe1 SR |
1695 | /* handle MAX TX EOB interrupt from a tx */ |
1696 | if (uic_mal & UIC_MAL_TXEOB) { | |
1697 | /* clear MAL interrupt status bits */ | |
1698 | mal_eob = mfdcr(maltxeobisr); | |
1699 | mtdcr(maltxeobisr, mal_eob); | |
1700 | mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); | |
1701 | ||
1702 | /* indicate that we serviced an interrupt */ | |
1703 | serviced = 1; | |
1704 | rc = 0; | |
d6c61aab SR |
1705 | } |
1706 | ||
d1631fe1 SR |
1707 | /* handle MAL RX EOB interupt from a receive */ |
1708 | /* check for EOB on valid channels */ | |
1709 | if (uic_mal & UIC_MAL_RXEOB) { | |
1710 | mal_eob = mfdcr(malrxeobisr); | |
1711 | if (mal_eob & | |
1712 | (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { | |
1713 | /* push packet to upper layer */ | |
1714 | enet_rcv(dev, emac_isr); | |
d6c61aab | 1715 | |
d1631fe1 SR |
1716 | /* clear MAL interrupt status bits */ |
1717 | mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB); | |
d6c61aab | 1718 | |
d6c61aab SR |
1719 | /* indicate that we serviced an interrupt */ |
1720 | serviced = 1; | |
1721 | rc = 0; | |
1722 | } | |
1723 | } | |
d1631fe1 | 1724 | } while (serviced); |
d6c61aab SR |
1725 | |
1726 | return (rc); | |
1727 | } | |
1728 | ||
ba56f625 WD |
1729 | /*-----------------------------------------------------------------------------+ |
1730 | * MAL Error Routine | |
1731 | *-----------------------------------------------------------------------------*/ | |
1732 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1733 | unsigned long uic, unsigned long maldef, | |
1734 | unsigned long mal_errr) | |
1735 | { | |
d6c61aab | 1736 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1737 | |
1738 | mtdcr (malesr, isr); /* clear interrupt */ | |
1739 | ||
1740 | /* clear DE interrupt */ | |
1741 | mtdcr (maltxdeir, 0xC0000000); | |
1742 | mtdcr (malrxdeir, 0x80000000); | |
1743 | ||
d6c61aab | 1744 | #ifdef INFO_4XX_ENET |
265817c7 | 1745 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1746 | #endif |
1747 | ||
1748 | eth_init (hw_p->bis); /* start again... */ | |
1749 | } | |
1750 | ||
1751 | /*-----------------------------------------------------------------------------+ | |
1752 | * EMAC Error Routine | |
1753 | *-----------------------------------------------------------------------------*/ | |
1754 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1755 | { | |
d6c61aab | 1756 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1757 | |
1758 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
2d83476a | 1759 | out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); |
ba56f625 WD |
1760 | } |
1761 | ||
1762 | /*-----------------------------------------------------------------------------+ | |
1763 | * enet_rcv() handles the ethernet receive data | |
1764 | *-----------------------------------------------------------------------------*/ | |
1765 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1766 | { | |
1767 | struct enet_frame *ef_ptr; | |
1768 | unsigned long data_len; | |
1769 | unsigned long rx_eob_isr; | |
d6c61aab | 1770 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1771 | |
1772 | int handled = 0; | |
1773 | int i; | |
1774 | int loop_count = 0; | |
1775 | ||
1776 | rx_eob_isr = mfdcr (malrxeobisr); | |
8ac41e3e | 1777 | if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { |
ba56f625 WD |
1778 | /* clear EOB */ |
1779 | mtdcr (malrxeobisr, rx_eob_isr); | |
1780 | ||
1781 | /* EMAC RX done */ | |
1782 | while (1) { /* do all */ | |
1783 | i = hw_p->rx_slot; | |
1784 | ||
1785 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1786 | || (loop_count >= NUM_RX_BUFF)) | |
1787 | break; | |
a2e1c709 | 1788 | |
ba56f625 | 1789 | loop_count++; |
ba56f625 | 1790 | handled++; |
8ac41e3e | 1791 | data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ |
ba56f625 WD |
1792 | if (data_len) { |
1793 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1794 | data_len = 0; | |
1795 | else { | |
1796 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1797 | data_len = 0; | |
1798 | hw_p->stats.rx_err_log[hw_p-> | |
1799 | rx_err_index] | |
1800 | = hw_p->rx[i].ctrl; | |
1801 | hw_p->rx_err_index++; | |
1802 | if (hw_p->rx_err_index == | |
1803 | MAX_ERR_LOG) | |
1804 | hw_p->rx_err_index = | |
1805 | 0; | |
fc1cfcdb | 1806 | } /* emac_erros */ |
ba56f625 | 1807 | } /* data_len < max mtu */ |
fc1cfcdb | 1808 | } /* if data_len */ |
ba56f625 WD |
1809 | if (!data_len) { /* no data */ |
1810 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1811 | ||
1812 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1813 | } | |
1814 | ||
1815 | /* !data_len */ | |
1816 | /* AS.HARNOIS */ | |
1817 | /* Check if user has already eaten buffer */ | |
1818 | /* if not => ERROR */ | |
1819 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1820 | if (hw_p->is_receiving) | |
1821 | printf ("ERROR : Receive buffers are full!\n"); | |
1822 | break; | |
1823 | } else { | |
1824 | hw_p->stats.rx_frames++; | |
1825 | hw_p->stats.rx += data_len; | |
1826 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
1827 | data_ptr; | |
d6c61aab | 1828 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1829 | hw_p->stats.pkts_rx++; |
1830 | #endif | |
1831 | /* AS.HARNOIS | |
1832 | * use ring buffer | |
1833 | */ | |
1834 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1835 | hw_p->rx_i_index++; | |
1836 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1837 | hw_p->rx_i_index = 0; | |
1838 | ||
a2e1c709 SR |
1839 | hw_p->rx_slot++; |
1840 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1841 | hw_p->rx_slot = 0; | |
1842 | ||
ba56f625 WD |
1843 | /* AS.HARNOIS |
1844 | * free receive buffer only when | |
1845 | * buffer has been handled (eth_rx) | |
1846 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1847 | */ | |
1848 | } /* if data_len */ | |
1849 | } /* while */ | |
1850 | } /* if EMACK_RXCHL */ | |
1851 | } | |
1852 | ||
1853 | ||
d6c61aab | 1854 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1855 | { |
1856 | int length; | |
1857 | int user_index; | |
1858 | unsigned long msr; | |
d6c61aab | 1859 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1860 | |
265817c7 | 1861 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1862 | |
1863 | for (;;) { | |
1864 | /* AS.HARNOIS | |
1865 | * use ring buffer and | |
1866 | * get index from rx buffer desciptor queue | |
1867 | */ | |
1868 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1869 | if (user_index == -1) { | |
1870 | length = -1; | |
1871 | break; /* nothing received - leave for() loop */ | |
1872 | } | |
1873 | ||
1874 | msr = mfmsr (); | |
1875 | mtmsr (msr & ~(MSR_EE)); | |
1876 | ||
8ac41e3e | 1877 | length = hw_p->rx[user_index].data_len & 0x0fff; |
ba56f625 WD |
1878 | |
1879 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1880 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1881 | /* NetReceive(NetRxPackets[i], length); */ | |
ff768cb1 SR |
1882 | invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, |
1883 | (u32)hw_p->rx[user_index].data_ptr + | |
ba79fde5 | 1884 | length - 4); |
ba56f625 WD |
1885 | NetReceive (NetRxPackets[user_index], length - 4); |
1886 | /* Free Recv Buffer */ | |
1887 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1888 | /* Free rx buffer descriptor queue */ | |
1889 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1890 | hw_p->rx_u_index++; | |
1891 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1892 | hw_p->rx_u_index = 0; | |
1893 | ||
d6c61aab | 1894 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1895 | hw_p->stats.pkts_handled++; |
1896 | #endif | |
1897 | ||
1898 | mtmsr (msr); /* Enable IRQ's */ | |
1899 | } | |
1900 | ||
265817c7 | 1901 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1902 | |
1903 | return length; | |
1904 | } | |
1905 | ||
d6c61aab | 1906 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1907 | { |
1908 | static int virgin = 0; | |
ba56f625 WD |
1909 | struct eth_device *dev; |
1910 | int eth_num = 0; | |
d6c61aab | 1911 | EMAC_4XX_HW_PST hw = NULL; |
5fb692ca SR |
1912 | u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; |
1913 | u32 hw_addr[4]; | |
d1631fe1 | 1914 | u32 mal_ier; |
ba56f625 | 1915 | |
846b0dd2 | 1916 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1917 | unsigned long pfc1; |
1918 | ||
ba56f625 WD |
1919 | mfsdr (sdr_pfc1, pfc1); |
1920 | pfc1 &= ~(0x01e00000); | |
1921 | pfc1 |= 0x01200000; | |
1922 | mtsdr (sdr_pfc1, pfc1); | |
c157d8e2 | 1923 | #endif |
6c5879f3 | 1924 | |
5fb692ca SR |
1925 | /* first clear all mac-addresses */ |
1926 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) | |
1927 | memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); | |
a06752e3 | 1928 | |
1e25f957 | 1929 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
ba56f625 | 1930 | switch (eth_num) { |
e2ffd59b | 1931 | default: /* fall through */ |
ba56f625 | 1932 | case 0: |
5fb692ca SR |
1933 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1934 | bis->bi_enetaddr, 6); | |
1935 | hw_addr[eth_num] = 0x0; | |
ba56f625 | 1936 | break; |
e2ffd59b | 1937 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1938 | case 1: |
5fb692ca SR |
1939 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1940 | bis->bi_enet1addr, 6); | |
1941 | hw_addr[eth_num] = 0x100; | |
ba56f625 | 1942 | break; |
e2ffd59b WD |
1943 | #endif |
1944 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1945 | case 2: |
5fb692ca SR |
1946 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1947 | bis->bi_enet2addr, 6); | |
4c9e8557 SR |
1948 | #if defined(CONFIG_460GT) |
1949 | hw_addr[eth_num] = 0x300; | |
1950 | #else | |
5fb692ca | 1951 | hw_addr[eth_num] = 0x400; |
4c9e8557 | 1952 | #endif |
ba56f625 | 1953 | break; |
e2ffd59b WD |
1954 | #endif |
1955 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1956 | case 3: |
5fb692ca SR |
1957 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1958 | bis->bi_enet3addr, 6); | |
4c9e8557 SR |
1959 | #if defined(CONFIG_460GT) |
1960 | hw_addr[eth_num] = 0x400; | |
1961 | #else | |
5fb692ca | 1962 | hw_addr[eth_num] = 0x600; |
4c9e8557 | 1963 | #endif |
ba56f625 | 1964 | break; |
e2ffd59b | 1965 | #endif |
ba56f625 | 1966 | } |
5fb692ca SR |
1967 | } |
1968 | ||
1969 | /* set phy num and mode */ | |
1970 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
1971 | bis->bi_phymode[0] = 0; | |
1972 | ||
1973 | #if defined(CONFIG_PHY1_ADDR) | |
1974 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; | |
1975 | bis->bi_phymode[1] = 0; | |
1976 | #endif | |
1977 | #if defined(CONFIG_440GX) | |
1978 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; | |
1979 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
1980 | bis->bi_phymode[2] = 2; | |
1981 | bis->bi_phymode[3] = 2; | |
dbbd1257 | 1982 | #endif |
5fb692ca | 1983 | |
dbbd1257 SR |
1984 | #if defined(CONFIG_440GX) || \ |
1985 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
1986 | defined(CONFIG_405EX) | |
5fb692ca SR |
1987 | ppc_4xx_eth_setup_bridge(0, bis); |
1988 | #endif | |
1989 | ||
1990 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { | |
1991 | /* | |
1992 | * See if we can actually bring up the interface, | |
1993 | * otherwise, skip it | |
1994 | */ | |
1995 | if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { | |
1996 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
1997 | continue; | |
1998 | } | |
ba56f625 WD |
1999 | |
2000 | /* Allocate device structure */ | |
2001 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
2002 | if (dev == NULL) { | |
d6c61aab | 2003 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2004 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
2005 | return (-1); |
2006 | } | |
b2532eff | 2007 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
2008 | |
2009 | /* Allocate our private use data */ | |
d6c61aab | 2010 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 2011 | if (hw == NULL) { |
d6c61aab | 2012 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2013 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
2014 | eth_num); |
2015 | free (dev); | |
2016 | return (-1); | |
2017 | } | |
b2532eff | 2018 | memset(hw, 0, sizeof(*hw)); |
ba56f625 | 2019 | |
5fb692ca SR |
2020 | hw->hw_addr = hw_addr[eth_num]; |
2021 | memcpy (dev->enetaddr, ethaddr[eth_num], 6); | |
ba56f625 | 2022 | hw->devnum = eth_num; |
c157d8e2 | 2023 | hw->print_speed = 1; |
ba56f625 | 2024 | |
5fb692ca | 2025 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); |
ba56f625 | 2026 | dev->priv = (void *) hw; |
d6c61aab SR |
2027 | dev->init = ppc_4xx_eth_init; |
2028 | dev->halt = ppc_4xx_eth_halt; | |
2029 | dev->send = ppc_4xx_eth_send; | |
2030 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 WD |
2031 | |
2032 | if (0 == virgin) { | |
2033 | /* set the MAL IER ??? names may change with new spec ??? */ | |
dbbd1257 SR |
2034 | #if defined(CONFIG_440SPE) || \ |
2035 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
8ac41e3e | 2036 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 2037 | defined(CONFIG_405EX) |
6c5879f3 MB |
2038 | mal_ier = |
2039 | MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | | |
2040 | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; | |
2041 | #else | |
ba56f625 WD |
2042 | mal_ier = |
2043 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
2044 | MAL_IER_OPBE | MAL_IER_PLBE; | |
6c5879f3 | 2045 | #endif |
ba56f625 WD |
2046 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ |
2047 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
2048 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
2049 | mtdcr (malier, mal_ier); | |
2050 | ||
2051 | /* install MAL interrupt handler */ | |
d1631fe1 | 2052 | irq_install_handler (VECNUM_MAL_SERR, |
ba56f625 WD |
2053 | (interrupt_handler_t *) enetInt, |
2054 | dev); | |
d1631fe1 | 2055 | irq_install_handler (VECNUM_MAL_TXEOB, |
ba56f625 WD |
2056 | (interrupt_handler_t *) enetInt, |
2057 | dev); | |
d1631fe1 | 2058 | irq_install_handler (VECNUM_MAL_RXEOB, |
ba56f625 WD |
2059 | (interrupt_handler_t *) enetInt, |
2060 | dev); | |
d1631fe1 | 2061 | irq_install_handler (VECNUM_MAL_TXDE, |
ba56f625 WD |
2062 | (interrupt_handler_t *) enetInt, |
2063 | dev); | |
d1631fe1 | 2064 | irq_install_handler (VECNUM_MAL_RXDE, |
ba56f625 WD |
2065 | (interrupt_handler_t *) enetInt, |
2066 | dev); | |
2067 | virgin = 1; | |
2068 | } | |
2069 | ||
d6c61aab | 2070 | #if defined(CONFIG_NET_MULTI) |
ba56f625 | 2071 | eth_register (dev); |
d6c61aab SR |
2072 | #else |
2073 | emac0_dev = dev; | |
2074 | #endif | |
6c5879f3 MB |
2075 | |
2076 | #if defined(CONFIG_NET_MULTI) | |
3a1ed1e1 | 2077 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c | 2078 | miiphy_register (dev->name, |
6e7fb6ea | 2079 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c | 2080 | #endif |
6c5879f3 | 2081 | #endif |
ba56f625 | 2082 | } /* end for each supported device */ |
802b769b SR |
2083 | |
2084 | return 0; | |
ba56f625 | 2085 | } |
d6c61aab | 2086 | |
d6c61aab SR |
2087 | #if !defined(CONFIG_NET_MULTI) |
2088 | void eth_halt (void) { | |
2089 | if (emac0_dev) { | |
2090 | ppc_4xx_eth_halt(emac0_dev); | |
2091 | free(emac0_dev); | |
2092 | emac0_dev = NULL; | |
2093 | } | |
2094 | } | |
2095 | ||
2096 | int eth_init (bd_t *bis) | |
2097 | { | |
2098 | ppc_4xx_eth_initialize(bis); | |
4f92ac36 SR |
2099 | if (emac0_dev) { |
2100 | return ppc_4xx_eth_init(emac0_dev, bis); | |
2101 | } else { | |
2102 | printf("ERROR: ethaddr not set!\n"); | |
2103 | return -1; | |
2104 | } | |
d6c61aab SR |
2105 | } |
2106 | ||
2107 | int eth_send(volatile void *packet, int length) | |
2108 | { | |
d6c61aab SR |
2109 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); |
2110 | } | |
2111 | ||
2112 | int eth_rx(void) | |
2113 | { | |
2114 | return (ppc_4xx_eth_rx(emac0_dev)); | |
2115 | } | |
63ff004c MB |
2116 | |
2117 | int emac4xx_miiphy_initialize (bd_t * bis) | |
2118 | { | |
3a1ed1e1 | 2119 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c | 2120 | miiphy_register ("ppc_4xx_eth0", |
6e7fb6ea | 2121 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c MB |
2122 | #endif |
2123 | ||
2124 | return 0; | |
2125 | } | |
d6c61aab | 2126 | #endif /* !defined(CONFIG_NET_MULTI) */ |