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Commit | Line | Data |
---|---|---|
9751ee09 | 1 | /* |
26235093 | 2 | * sh_eth.c - Driver for Renesas ethernet controler. |
9751ee09 | 3 | * |
3bb4cc31 NI |
4 | * Copyright (C) 2008, 2011 Renesas Solutions Corp. |
5 | * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu | |
9751ee09 | 6 | * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> |
8707678c | 7 | * Copyright (C) 2013 Renesas Electronics Corporation |
9751ee09 | 8 | * |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
9751ee09 NI |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <malloc.h> | |
15 | #include <net.h> | |
bd3980cc | 16 | #include <netdev.h> |
bd1024b0 | 17 | #include <miiphy.h> |
9751ee09 NI |
18 | #include <asm/errno.h> |
19 | #include <asm/io.h> | |
20 | ||
21 | #include "sh_eth.h" | |
22 | ||
23 | #ifndef CONFIG_SH_ETHER_USE_PORT | |
24 | # error "Please define CONFIG_SH_ETHER_USE_PORT" | |
25 | #endif | |
26 | #ifndef CONFIG_SH_ETHER_PHY_ADDR | |
27 | # error "Please define CONFIG_SH_ETHER_PHY_ADDR" | |
28 | #endif | |
870cc23f | 29 | |
92f07134 NI |
30 | #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) |
31 | #define flush_cache_wback(addr, len) \ | |
32 | flush_dcache_range((u32)addr, (u32)(addr + len - 1)) | |
68260aab YS |
33 | #else |
34 | #define flush_cache_wback(...) | |
35 | #endif | |
9751ee09 | 36 | |
92f07134 NI |
37 | #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) |
38 | #define invalidate_cache(addr, len) \ | |
39 | { \ | |
40 | u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ | |
41 | u32 start, end; \ | |
42 | \ | |
43 | start = (u32)addr; \ | |
44 | end = start + len; \ | |
45 | start &= ~(line_size - 1); \ | |
46 | end = ((end + line_size - 1) & ~(line_size - 1)); \ | |
47 | \ | |
48 | invalidate_dcache_range(start, end); \ | |
49 | } | |
50 | #else | |
51 | #define invalidate_cache(...) | |
52 | #endif | |
53 | ||
4ba62c72 NI |
54 | #define TIMEOUT_CNT 1000 |
55 | ||
10cbe3b6 | 56 | int sh_eth_send(struct eth_device *dev, void *packet, int len) |
9751ee09 | 57 | { |
bd3980cc NI |
58 | struct sh_eth_dev *eth = dev->priv; |
59 | int port = eth->port, ret = 0, timeout; | |
60 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 NI |
61 | |
62 | if (!packet || len > 0xffff) { | |
bd3980cc NI |
63 | printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); |
64 | ret = -EINVAL; | |
65 | goto err; | |
9751ee09 NI |
66 | } |
67 | ||
68 | /* packet must be a 4 byte boundary */ | |
ee6ec5d4 | 69 | if ((int)packet & 3) { |
e2752db0 NI |
70 | printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n" |
71 | , __func__); | |
bd3980cc NI |
72 | ret = -EFAULT; |
73 | goto err; | |
9751ee09 NI |
74 | } |
75 | ||
76 | /* Update tx descriptor */ | |
68260aab | 77 | flush_cache_wback(packet, len); |
9751ee09 NI |
78 | port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); |
79 | port_info->tx_desc_cur->td1 = len << 16; | |
80 | /* Must preserve the end of descriptor list indication */ | |
81 | if (port_info->tx_desc_cur->td0 & TD_TDLE) | |
82 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; | |
83 | else | |
84 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; | |
85 | ||
86 | /* Restart the transmitter if disabled */ | |
49afb8ca YS |
87 | if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) |
88 | sh_eth_write(eth, EDTRR_TRNS, EDTRR); | |
9751ee09 NI |
89 | |
90 | /* Wait until packet is transmitted */ | |
4ba62c72 | 91 | timeout = TIMEOUT_CNT; |
92f07134 NI |
92 | do { |
93 | invalidate_cache(port_info->tx_desc_cur, | |
94 | sizeof(struct tx_desc_s)); | |
9751ee09 | 95 | udelay(100); |
92f07134 | 96 | } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); |
9751ee09 NI |
97 | |
98 | if (timeout < 0) { | |
bd3980cc NI |
99 | printf(SHETHER_NAME ": transmit timeout\n"); |
100 | ret = -ETIMEDOUT; | |
9751ee09 NI |
101 | goto err; |
102 | } | |
103 | ||
9751ee09 NI |
104 | port_info->tx_desc_cur++; |
105 | if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) | |
106 | port_info->tx_desc_cur = port_info->tx_desc_base; | |
107 | ||
bd3980cc NI |
108 | err: |
109 | return ret; | |
9751ee09 NI |
110 | } |
111 | ||
bd3980cc | 112 | int sh_eth_recv(struct eth_device *dev) |
9751ee09 | 113 | { |
bd3980cc NI |
114 | struct sh_eth_dev *eth = dev->priv; |
115 | int port = eth->port, len = 0; | |
116 | struct sh_eth_info *port_info = ð->port_info[port]; | |
10cbe3b6 | 117 | uchar *packet; |
9751ee09 NI |
118 | |
119 | /* Check if the rx descriptor is ready */ | |
92f07134 | 120 | invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); |
9751ee09 NI |
121 | if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { |
122 | /* Check for errors */ | |
123 | if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { | |
124 | len = port_info->rx_desc_cur->rd1 & 0xffff; | |
10cbe3b6 JH |
125 | packet = (uchar *) |
126 | ADDR_TO_P2(port_info->rx_desc_cur->rd2); | |
92f07134 | 127 | invalidate_cache(packet, len); |
9751ee09 NI |
128 | NetReceive(packet, len); |
129 | } | |
130 | ||
131 | /* Make current descriptor available again */ | |
132 | if (port_info->rx_desc_cur->rd0 & RD_RDLE) | |
133 | port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; | |
134 | else | |
135 | port_info->rx_desc_cur->rd0 = RD_RACT; | |
9751ee09 NI |
136 | /* Point to the next descriptor */ |
137 | port_info->rx_desc_cur++; | |
138 | if (port_info->rx_desc_cur >= | |
139 | port_info->rx_desc_base + NUM_RX_DESC) | |
140 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
141 | } | |
142 | ||
143 | /* Restart the receiver if disabled */ | |
49afb8ca YS |
144 | if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) |
145 | sh_eth_write(eth, EDRRR_R, EDRRR); | |
9751ee09 NI |
146 | |
147 | return len; | |
148 | } | |
149 | ||
bd3980cc | 150 | static int sh_eth_reset(struct sh_eth_dev *eth) |
9751ee09 | 151 | { |
62cbddc4 | 152 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
bd3980cc | 153 | int ret = 0, i; |
9751ee09 NI |
154 | |
155 | /* Start e-dmac transmitter and receiver */ | |
49afb8ca | 156 | sh_eth_write(eth, EDSR_ENALL, EDSR); |
9751ee09 NI |
157 | |
158 | /* Perform a software reset and wait for it to complete */ | |
49afb8ca | 159 | sh_eth_write(eth, EDMR_SRST, EDMR); |
e2752db0 | 160 | for (i = 0; i < TIMEOUT_CNT; i++) { |
49afb8ca | 161 | if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) |
9751ee09 NI |
162 | break; |
163 | udelay(1000); | |
164 | } | |
165 | ||
4ba62c72 | 166 | if (i == TIMEOUT_CNT) { |
bd3980cc NI |
167 | printf(SHETHER_NAME ": Software reset timeout\n"); |
168 | ret = -EIO; | |
9751ee09 | 169 | } |
bd3980cc NI |
170 | |
171 | return ret; | |
903de461 | 172 | #else |
49afb8ca | 173 | sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); |
903de461 | 174 | udelay(3000); |
49afb8ca | 175 | sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); |
903de461 YS |
176 | |
177 | return 0; | |
178 | #endif | |
9751ee09 NI |
179 | } |
180 | ||
bd3980cc | 181 | static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 182 | { |
bd3980cc | 183 | int port = eth->port, i, ret = 0; |
9751ee09 | 184 | u32 tmp_addr; |
bd3980cc | 185 | struct sh_eth_info *port_info = ð->port_info[port]; |
9751ee09 | 186 | struct tx_desc_s *cur_tx_desc; |
9751ee09 | 187 | |
bd3980cc NI |
188 | /* |
189 | * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned | |
190 | */ | |
191 | port_info->tx_desc_malloc = malloc(NUM_TX_DESC * | |
9751ee09 | 192 | sizeof(struct tx_desc_s) + |
bd3980cc NI |
193 | TX_DESC_SIZE - 1); |
194 | if (!port_info->tx_desc_malloc) { | |
195 | printf(SHETHER_NAME ": malloc failed\n"); | |
196 | ret = -ENOMEM; | |
197 | goto err; | |
9751ee09 | 198 | } |
bd3980cc | 199 | |
9751ee09 NI |
200 | tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & |
201 | ~(TX_DESC_SIZE - 1)); | |
68260aab | 202 | flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); |
9751ee09 NI |
203 | /* Make sure we use a P2 address (non-cacheable) */ |
204 | port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); | |
9751ee09 NI |
205 | port_info->tx_desc_cur = port_info->tx_desc_base; |
206 | ||
207 | /* Initialize all descriptors */ | |
208 | for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; | |
209 | cur_tx_desc++, i++) { | |
210 | cur_tx_desc->td0 = 0x00; | |
211 | cur_tx_desc->td1 = 0x00; | |
212 | cur_tx_desc->td2 = 0x00; | |
213 | } | |
214 | ||
215 | /* Mark the end of the descriptors */ | |
216 | cur_tx_desc--; | |
217 | cur_tx_desc->td0 |= TD_TDLE; | |
218 | ||
219 | /* Point the controller to the tx descriptor list. Must use physical | |
220 | addresses */ | |
49afb8ca | 221 | sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); |
62cbddc4 | 222 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
49afb8ca YS |
223 | sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); |
224 | sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); | |
225 | sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ | |
903de461 | 226 | #endif |
9751ee09 | 227 | |
bd3980cc NI |
228 | err: |
229 | return ret; | |
9751ee09 NI |
230 | } |
231 | ||
bd3980cc | 232 | static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 233 | { |
bd3980cc NI |
234 | int port = eth->port, i , ret = 0; |
235 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 | 236 | struct rx_desc_s *cur_rx_desc; |
bd3980cc | 237 | u32 tmp_addr; |
9751ee09 | 238 | u8 *rx_buf; |
9751ee09 | 239 | |
bd3980cc NI |
240 | /* |
241 | * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned | |
242 | */ | |
243 | port_info->rx_desc_malloc = malloc(NUM_RX_DESC * | |
9751ee09 | 244 | sizeof(struct rx_desc_s) + |
bd3980cc NI |
245 | RX_DESC_SIZE - 1); |
246 | if (!port_info->rx_desc_malloc) { | |
247 | printf(SHETHER_NAME ": malloc failed\n"); | |
248 | ret = -ENOMEM; | |
249 | goto err; | |
9751ee09 | 250 | } |
bd3980cc | 251 | |
9751ee09 NI |
252 | tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & |
253 | ~(RX_DESC_SIZE - 1)); | |
68260aab | 254 | flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); |
9751ee09 NI |
255 | /* Make sure we use a P2 address (non-cacheable) */ |
256 | port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); | |
257 | ||
258 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
259 | ||
bd3980cc NI |
260 | /* |
261 | * Allocate rx data buffers. They must be 32 bytes aligned and in | |
262 | * P2 area | |
263 | */ | |
f8b7507d NI |
264 | port_info->rx_buf_malloc = malloc( |
265 | NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1); | |
bd3980cc NI |
266 | if (!port_info->rx_buf_malloc) { |
267 | printf(SHETHER_NAME ": malloc failed\n"); | |
268 | ret = -ENOMEM; | |
269 | goto err_buf_malloc; | |
9751ee09 | 270 | } |
bd3980cc | 271 | |
f8b7507d NI |
272 | tmp_addr = (u32)(((int)port_info->rx_buf_malloc |
273 | + (RX_BUF_ALIGNE_SIZE - 1)) & | |
274 | ~(RX_BUF_ALIGNE_SIZE - 1)); | |
9751ee09 NI |
275 | port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); |
276 | ||
277 | /* Initialize all descriptors */ | |
278 | for (cur_rx_desc = port_info->rx_desc_base, | |
279 | rx_buf = port_info->rx_buf_base, i = 0; | |
280 | i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { | |
281 | cur_rx_desc->rd0 = RD_RACT; | |
282 | cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; | |
283 | cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); | |
284 | } | |
285 | ||
286 | /* Mark the end of the descriptors */ | |
287 | cur_rx_desc--; | |
288 | cur_rx_desc->rd0 |= RD_RDLE; | |
289 | ||
290 | /* Point the controller to the rx descriptor list */ | |
49afb8ca | 291 | sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); |
62cbddc4 | 292 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
49afb8ca YS |
293 | sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); |
294 | sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); | |
295 | sh_eth_write(eth, RDFFR_RDLF, RDFFR); | |
903de461 | 296 | #endif |
9751ee09 | 297 | |
bd3980cc NI |
298 | return ret; |
299 | ||
300 | err_buf_malloc: | |
301 | free(port_info->rx_desc_malloc); | |
302 | port_info->rx_desc_malloc = NULL; | |
303 | ||
304 | err: | |
305 | return ret; | |
9751ee09 NI |
306 | } |
307 | ||
bd3980cc | 308 | static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) |
9751ee09 | 309 | { |
bd3980cc NI |
310 | int port = eth->port; |
311 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 NI |
312 | |
313 | if (port_info->tx_desc_malloc) { | |
314 | free(port_info->tx_desc_malloc); | |
315 | port_info->tx_desc_malloc = NULL; | |
316 | } | |
bd3980cc NI |
317 | } |
318 | ||
319 | static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) | |
320 | { | |
321 | int port = eth->port; | |
322 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 NI |
323 | |
324 | if (port_info->rx_desc_malloc) { | |
325 | free(port_info->rx_desc_malloc); | |
326 | port_info->rx_desc_malloc = NULL; | |
327 | } | |
328 | ||
329 | if (port_info->rx_buf_malloc) { | |
330 | free(port_info->rx_buf_malloc); | |
331 | port_info->rx_buf_malloc = NULL; | |
332 | } | |
333 | } | |
334 | ||
bd3980cc | 335 | static int sh_eth_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 336 | { |
bd3980cc | 337 | int ret = 0; |
9751ee09 | 338 | |
bd3980cc NI |
339 | ret = sh_eth_tx_desc_init(eth); |
340 | if (ret) | |
341 | goto err_tx_init; | |
9751ee09 | 342 | |
bd3980cc NI |
343 | ret = sh_eth_rx_desc_init(eth); |
344 | if (ret) | |
345 | goto err_rx_init; | |
346 | ||
347 | return ret; | |
348 | err_rx_init: | |
349 | sh_eth_tx_desc_free(eth); | |
350 | ||
351 | err_tx_init: | |
352 | return ret; | |
9751ee09 NI |
353 | } |
354 | ||
bd3980cc | 355 | static int sh_eth_phy_config(struct sh_eth_dev *eth) |
9751ee09 | 356 | { |
bd1024b0 | 357 | int port = eth->port, ret = 0; |
bd3980cc | 358 | struct sh_eth_info *port_info = ð->port_info[port]; |
bd1024b0 YS |
359 | struct eth_device *dev = port_info->dev; |
360 | struct phy_device *phydev; | |
9751ee09 | 361 | |
ee6ec5d4 NI |
362 | phydev = phy_connect( |
363 | miiphy_get_dev_by_name(dev->name), | |
4398d559 | 364 | port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); |
bd1024b0 YS |
365 | port_info->phydev = phydev; |
366 | phy_config(phydev); | |
bd3980cc | 367 | |
bd3980cc | 368 | return ret; |
9751ee09 NI |
369 | } |
370 | ||
bd3980cc | 371 | static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) |
9751ee09 | 372 | { |
bd3980cc | 373 | int port = eth->port, ret = 0; |
bd1024b0 | 374 | u32 val; |
bd3980cc | 375 | struct sh_eth_info *port_info = ð->port_info[port]; |
c527ce92 | 376 | struct eth_device *dev = port_info->dev; |
bd1024b0 | 377 | struct phy_device *phy; |
9751ee09 NI |
378 | |
379 | /* Configure e-dmac registers */ | |
f8b7507d NI |
380 | sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | |
381 | (EMDR_DESC | EDMR_EL), EDMR); | |
382 | ||
49afb8ca YS |
383 | sh_eth_write(eth, 0, EESIPR); |
384 | sh_eth_write(eth, 0, TRSCER); | |
385 | sh_eth_write(eth, 0, TFTR); | |
386 | sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); | |
387 | sh_eth_write(eth, RMCR_RST, RMCR); | |
62cbddc4 | 388 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
49afb8ca | 389 | sh_eth_write(eth, 0, RPADIR); |
903de461 | 390 | #endif |
49afb8ca | 391 | sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); |
9751ee09 NI |
392 | |
393 | /* Configure e-mac registers */ | |
49afb8ca | 394 | sh_eth_write(eth, 0, ECSIPR); |
9751ee09 NI |
395 | |
396 | /* Set Mac address */ | |
c527ce92 MF |
397 | val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | |
398 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; | |
49afb8ca | 399 | sh_eth_write(eth, val, MAHR); |
9751ee09 | 400 | |
c527ce92 | 401 | val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; |
49afb8ca | 402 | sh_eth_write(eth, val, MALR); |
9751ee09 | 403 | |
49afb8ca | 404 | sh_eth_write(eth, RFLR_RFL_MIN, RFLR); |
26235093 | 405 | #if defined(SH_ETH_TYPE_GETHER) |
49afb8ca | 406 | sh_eth_write(eth, 0, PIPR); |
62cbddc4 NI |
407 | #endif |
408 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) | |
49afb8ca YS |
409 | sh_eth_write(eth, APR_AP, APR); |
410 | sh_eth_write(eth, MPR_MP, MPR); | |
411 | sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); | |
903de461 | 412 | #endif |
3bb4cc31 | 413 | |
dcd5a593 | 414 | #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) |
49afb8ca | 415 | sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); |
47ce8890 | 416 | #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) |
8707678c | 417 | sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); |
4398d559 | 418 | #endif |
9751ee09 | 419 | /* Configure phy */ |
bd3980cc NI |
420 | ret = sh_eth_phy_config(eth); |
421 | if (ret) { | |
88a4c2e7 | 422 | printf(SHETHER_NAME ": phy config timeout\n"); |
bd3980cc NI |
423 | goto err_phy_cfg; |
424 | } | |
bd1024b0 | 425 | phy = port_info->phydev; |
11af8d65 TT |
426 | ret = phy_startup(phy); |
427 | if (ret) { | |
428 | printf(SHETHER_NAME ": phy startup failure\n"); | |
429 | return ret; | |
430 | } | |
9751ee09 | 431 | |
3bb4cc31 NI |
432 | val = 0; |
433 | ||
9751ee09 | 434 | /* Set the transfer speed */ |
bd1024b0 | 435 | if (phy->speed == 100) { |
bd3980cc | 436 | printf(SHETHER_NAME ": 100Base/"); |
26235093 | 437 | #if defined(SH_ETH_TYPE_GETHER) |
49afb8ca | 438 | sh_eth_write(eth, GECMR_100B, GECMR); |
e3bb3254 | 439 | #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) |
49afb8ca | 440 | sh_eth_write(eth, 1, RTRATE); |
47ce8890 NI |
441 | #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ |
442 | defined(CONFIG_R8A7791) | |
3bb4cc31 NI |
443 | val = ECMR_RTM; |
444 | #endif | |
bd1024b0 | 445 | } else if (phy->speed == 10) { |
bd3980cc | 446 | printf(SHETHER_NAME ": 10Base/"); |
26235093 | 447 | #if defined(SH_ETH_TYPE_GETHER) |
49afb8ca | 448 | sh_eth_write(eth, GECMR_10B, GECMR); |
e3bb3254 | 449 | #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) |
49afb8ca | 450 | sh_eth_write(eth, 0, RTRATE); |
903de461 | 451 | #endif |
3bb4cc31 | 452 | } |
26235093 | 453 | #if defined(SH_ETH_TYPE_GETHER) |
4398d559 NI |
454 | else if (phy->speed == 1000) { |
455 | printf(SHETHER_NAME ": 1000Base/"); | |
49afb8ca | 456 | sh_eth_write(eth, GECMR_1000B, GECMR); |
4398d559 NI |
457 | } |
458 | #endif | |
9751ee09 NI |
459 | |
460 | /* Check if full duplex mode is supported by the phy */ | |
bd1024b0 | 461 | if (phy->duplex) { |
9751ee09 | 462 | printf("Full\n"); |
49afb8ca YS |
463 | sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), |
464 | ECMR); | |
9751ee09 NI |
465 | } else { |
466 | printf("Half\n"); | |
49afb8ca | 467 | sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); |
9751ee09 | 468 | } |
bd3980cc NI |
469 | |
470 | return ret; | |
471 | ||
472 | err_phy_cfg: | |
473 | return ret; | |
9751ee09 NI |
474 | } |
475 | ||
bd3980cc | 476 | static void sh_eth_start(struct sh_eth_dev *eth) |
9751ee09 NI |
477 | { |
478 | /* | |
479 | * Enable the e-dmac receiver only. The transmitter will be enabled when | |
480 | * we have something to transmit | |
481 | */ | |
49afb8ca | 482 | sh_eth_write(eth, EDRRR_R, EDRRR); |
bd3980cc | 483 | } |
9751ee09 | 484 | |
bd3980cc NI |
485 | static void sh_eth_stop(struct sh_eth_dev *eth) |
486 | { | |
49afb8ca | 487 | sh_eth_write(eth, ~EDRRR_R, EDRRR); |
9751ee09 NI |
488 | } |
489 | ||
bd3980cc | 490 | int sh_eth_init(struct eth_device *dev, bd_t *bd) |
9751ee09 | 491 | { |
bd3980cc NI |
492 | int ret = 0; |
493 | struct sh_eth_dev *eth = dev->priv; | |
9751ee09 | 494 | |
bd3980cc NI |
495 | ret = sh_eth_reset(eth); |
496 | if (ret) | |
497 | goto err; | |
9751ee09 | 498 | |
bd3980cc NI |
499 | ret = sh_eth_desc_init(eth); |
500 | if (ret) | |
501 | goto err; | |
9751ee09 | 502 | |
bd3980cc NI |
503 | ret = sh_eth_config(eth, bd); |
504 | if (ret) | |
505 | goto err_config; | |
506 | ||
507 | sh_eth_start(eth); | |
508 | ||
509 | return ret; | |
9751ee09 | 510 | |
bd3980cc NI |
511 | err_config: |
512 | sh_eth_tx_desc_free(eth); | |
513 | sh_eth_rx_desc_free(eth); | |
514 | ||
515 | err: | |
516 | return ret; | |
517 | } | |
518 | ||
519 | void sh_eth_halt(struct eth_device *dev) | |
520 | { | |
521 | struct sh_eth_dev *eth = dev->priv; | |
bd3980cc NI |
522 | sh_eth_stop(eth); |
523 | } | |
524 | ||
525 | int sh_eth_initialize(bd_t *bd) | |
526 | { | |
e2752db0 | 527 | int ret = 0; |
bd3980cc | 528 | struct sh_eth_dev *eth = NULL; |
e2752db0 | 529 | struct eth_device *dev = NULL; |
bd3980cc | 530 | |
e2752db0 | 531 | eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); |
bd3980cc NI |
532 | if (!eth) { |
533 | printf(SHETHER_NAME ": %s: malloc failed\n", __func__); | |
534 | ret = -ENOMEM; | |
9751ee09 | 535 | goto err; |
bd3980cc | 536 | } |
9751ee09 | 537 | |
e2752db0 | 538 | dev = (struct eth_device *)malloc(sizeof(struct eth_device)); |
bd3980cc NI |
539 | if (!dev) { |
540 | printf(SHETHER_NAME ": %s: malloc failed\n", __func__); | |
541 | ret = -ENOMEM; | |
542 | goto err; | |
543 | } | |
e2752db0 NI |
544 | memset(dev, 0, sizeof(struct eth_device)); |
545 | memset(eth, 0, sizeof(struct sh_eth_dev)); | |
9751ee09 | 546 | |
bd3980cc NI |
547 | eth->port = CONFIG_SH_ETHER_USE_PORT; |
548 | eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; | |
549 | ||
e2752db0 NI |
550 | dev->priv = (void *)eth; |
551 | dev->iobase = 0; | |
552 | dev->init = sh_eth_init; | |
553 | dev->halt = sh_eth_halt; | |
554 | dev->send = sh_eth_send; | |
555 | dev->recv = sh_eth_recv; | |
556 | eth->port_info[eth->port].dev = dev; | |
bd3980cc NI |
557 | |
558 | sprintf(dev->name, SHETHER_NAME); | |
559 | ||
e2752db0 NI |
560 | /* Register Device to EtherNet subsystem */ |
561 | eth_register(dev); | |
bd3980cc | 562 | |
bd1024b0 YS |
563 | bb_miiphy_buses[0].priv = eth; |
564 | miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); | |
565 | ||
c527ce92 MF |
566 | if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) |
567 | puts("Please set MAC address\n"); | |
bd3980cc NI |
568 | |
569 | return ret; | |
9751ee09 | 570 | |
9751ee09 | 571 | err: |
bd3980cc NI |
572 | if (dev) |
573 | free(dev); | |
574 | ||
575 | if (eth) | |
576 | free(eth); | |
577 | ||
578 | printf(SHETHER_NAME ": Failed\n"); | |
579 | return ret; | |
9751ee09 | 580 | } |
bd1024b0 YS |
581 | |
582 | /******* for bb_miiphy *******/ | |
583 | static int sh_eth_bb_init(struct bb_miiphy_bus *bus) | |
584 | { | |
585 | return 0; | |
586 | } | |
587 | ||
588 | static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) | |
589 | { | |
590 | struct sh_eth_dev *eth = bus->priv; | |
bd1024b0 | 591 | |
49afb8ca | 592 | sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); |
bd1024b0 YS |
593 | |
594 | return 0; | |
595 | } | |
596 | ||
597 | static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) | |
598 | { | |
599 | struct sh_eth_dev *eth = bus->priv; | |
bd1024b0 | 600 | |
49afb8ca | 601 | sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); |
bd1024b0 YS |
602 | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) | |
607 | { | |
608 | struct sh_eth_dev *eth = bus->priv; | |
bd1024b0 YS |
609 | |
610 | if (v) | |
49afb8ca | 611 | sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); |
bd1024b0 | 612 | else |
49afb8ca | 613 | sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); |
bd1024b0 YS |
614 | |
615 | return 0; | |
616 | } | |
617 | ||
618 | static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) | |
619 | { | |
620 | struct sh_eth_dev *eth = bus->priv; | |
bd1024b0 | 621 | |
49afb8ca | 622 | *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; |
bd1024b0 YS |
623 | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) | |
628 | { | |
629 | struct sh_eth_dev *eth = bus->priv; | |
bd1024b0 YS |
630 | |
631 | if (v) | |
49afb8ca | 632 | sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); |
bd1024b0 | 633 | else |
49afb8ca | 634 | sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); |
bd1024b0 YS |
635 | |
636 | return 0; | |
637 | } | |
638 | ||
639 | static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) | |
640 | { | |
641 | udelay(10); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | struct bb_miiphy_bus bb_miiphy_buses[] = { | |
647 | { | |
648 | .name = "sh_eth", | |
649 | .init = sh_eth_bb_init, | |
650 | .mdio_active = sh_eth_bb_mdio_active, | |
651 | .mdio_tristate = sh_eth_bb_mdio_tristate, | |
652 | .set_mdio = sh_eth_bb_set_mdio, | |
653 | .get_mdio = sh_eth_bb_get_mdio, | |
654 | .set_mdc = sh_eth_bb_set_mdc, | |
655 | .delay = sh_eth_bb_delay, | |
656 | } | |
657 | }; | |
658 | int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); |