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Commit | Line | Data |
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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
1a459660 | 20 | * SPDX-License-Identifier: GPL-2.0+ |
3e326ece MK |
21 | */ |
22 | /* | |
23 | * IMPORTANT NOTES | |
fc43be47 | 24 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 25 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 26 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 27 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
28 | * to activate workaround for bug #41 or this driver will NOT work! |
29 | */ | |
30 | ||
31 | #include <common.h> | |
fc43be47 MK |
32 | #include <asm/byteorder.h> |
33 | ||
34 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 35 | # include <pci.h> |
477434c6 SP |
36 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
37 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
38 | #endif | |
ddf83a2f | 39 | #endif |
3e326ece MK |
40 | |
41 | #include <malloc.h> | |
42 | #include <usb.h> | |
2731b9a8 JCPV |
43 | |
44 | #include "ohci.h" | |
3e326ece | 45 | |
e8da58f2 WD |
46 | #ifdef CONFIG_AT91RM9200 |
47 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
48 | #endif | |
49 | ||
ddf83a2f | 50 | #if defined(CONFIG_ARM920T) || \ |
ac67804f | 51 | defined(CONFIG_S3C24X0) || \ |
ae3b770e | 52 | defined(CONFIG_440EP) || \ |
4dae14ce | 53 | defined(CONFIG_PCI_OHCI) || \ |
2596f5b9 | 54 | defined(CONFIG_MPC5200) || \ |
6d0f6bcf | 55 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
56 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
57 | #endif | |
58 | ||
3e326ece | 59 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
60 | #undef DEBUG |
61 | #undef SHOW_INFO | |
62 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
63 | |
64 | /* For initializing controller (mask in an HCFS mode too) */ | |
65 | #define OHCI_CONTROL_INIT \ | |
66 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
67 | ||
6f5794a6 RB |
68 | #define min_t(type, x, y) \ |
69 | ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) | |
3e326ece | 70 | |
4dae14ce ZW |
71 | #ifdef CONFIG_PCI_OHCI |
72 | static struct pci_device_id ohci_pci_ids[] = { | |
73 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 74 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 75 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
76 | /* Please add supported PCI OHCI controller ids here */ |
77 | {0, 0} | |
78 | }; | |
79 | #endif | |
80 | ||
e90fb6af YT |
81 | #ifdef CONFIG_PCI_EHCI_DEVNO |
82 | static struct pci_device_id ehci_pci_ids[] = { | |
83 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
84 | /* Please add supported PCI EHCI controller ids here */ | |
85 | {0, 0} | |
86 | }; | |
87 | #endif | |
88 | ||
3e326ece MK |
89 | #ifdef DEBUG |
90 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
91 | #else | |
6f5794a6 | 92 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
93 | #endif /* DEBUG */ |
94 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
95 | #ifdef SHOW_INFO |
96 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
97 | #else | |
6f5794a6 | 98 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
99 | #endif |
100 | ||
6d0f6bcf | 101 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
102 | # define m16_swap(x) cpu_to_be16(x) |
103 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 104 | #else |
fc43be47 MK |
105 | # define m16_swap(x) cpu_to_le16(x) |
106 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 107 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece MK |
108 | |
109 | /* global ohci_t */ | |
110 | static ohci_t gohci; | |
111 | /* this must be aligned to a 256 byte boundary */ | |
112 | struct ohci_hcca ghcca[1]; | |
113 | /* a pointer to the aligned storage */ | |
114 | struct ohci_hcca *phcca; | |
115 | /* this allocates EDs for all possible endpoints */ | |
116 | struct ohci_device ohci_dev; | |
3e326ece MK |
117 | /* device which was disconnected */ |
118 | struct usb_device *devgone; | |
119 | ||
6f5794a6 | 120 | static inline u32 roothub_a(struct ohci *hc) |
a5496a18 | 121 | { return ohci_readl(&hc->regs->roothub.a); } |
6f5794a6 | 122 | static inline u32 roothub_b(struct ohci *hc) |
a5496a18 | 123 | { return ohci_readl(&hc->regs->roothub.b); } |
6f5794a6 | 124 | static inline u32 roothub_status(struct ohci *hc) |
a5496a18 | 125 | { return ohci_readl(&hc->regs->roothub.status); } |
6f5794a6 | 126 | static inline u32 roothub_portstatus(struct ohci *hc, int i) |
a5496a18 | 127 | { return ohci_readl(&hc->regs->roothub.portstatus[i]); } |
3e326ece | 128 | |
3e326ece | 129 | /* forward declaration */ |
6f5794a6 RB |
130 | static int hc_interrupt(void); |
131 | static void td_submit_job(struct usb_device *dev, unsigned long pipe, | |
132 | void *buffer, int transfer_len, | |
133 | struct devrequest *setup, urb_priv_t *urb, | |
134 | int interval); | |
3e326ece MK |
135 | |
136 | /*-------------------------------------------------------------------------* | |
137 | * URB support functions | |
138 | *-------------------------------------------------------------------------*/ | |
139 | ||
140 | /* free HCD-private data associated with this URB */ | |
141 | ||
6f5794a6 | 142 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
143 | { |
144 | int i; | |
145 | int last; | |
6f5794a6 | 146 | struct td *td; |
3e326ece MK |
147 | |
148 | last = urb->length - 1; | |
149 | if (last >= 0) { | |
150 | for (i = 0; i <= last; i++) { | |
151 | td = urb->td[i]; | |
152 | if (td) { | |
153 | td->usb_dev = NULL; | |
154 | urb->td[i] = NULL; | |
155 | } | |
156 | } | |
157 | } | |
4dae14ce | 158 | free(urb); |
3e326ece MK |
159 | } |
160 | ||
161 | /*-------------------------------------------------------------------------*/ | |
162 | ||
163 | #ifdef DEBUG | |
6f5794a6 | 164 | static int sohci_get_current_frame_number(struct usb_device *dev); |
3e326ece MK |
165 | |
166 | /* debug| print the main components of an URB | |
167 | * small: 0) header + data packets 1) just header */ | |
168 | ||
6f5794a6 RB |
169 | static void pkt_print(urb_priv_t *purb, struct usb_device *dev, |
170 | unsigned long pipe, void *buffer, int transfer_len, | |
171 | struct devrequest *setup, char *str, int small) | |
3e326ece | 172 | { |
6f5794a6 | 173 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 174 | str, |
6f5794a6 RB |
175 | sohci_get_current_frame_number(dev), |
176 | usb_pipedevice(pipe), | |
177 | usb_pipeendpoint(pipe), | |
178 | usb_pipeout(pipe)? 'O': 'I', | |
179 | usb_pipetype(pipe) < 2 ? \ | |
180 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
181 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 182 | (purb ? purb->actual_length : 0), |
3e326ece MK |
183 | transfer_len, dev->status); |
184 | #ifdef OHCI_VERBOSE_DEBUG | |
185 | if (!small) { | |
186 | int i, len; | |
187 | ||
6f5794a6 RB |
188 | if (usb_pipecontrol(pipe)) { |
189 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 190 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
191 | printf(" %02x", ((__u8 *) setup) [i]); |
192 | printf("\n"); | |
3e326ece MK |
193 | } |
194 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 195 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 196 | (purb ? purb->actual_length : 0), |
3e326ece | 197 | transfer_len); |
6f5794a6 | 198 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 199 | (purb ? purb->actual_length : 0); |
3e326ece | 200 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
201 | printf(" %02x", ((__u8 *) buffer) [i]); |
202 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
203 | } |
204 | } | |
205 | #endif | |
206 | } | |
207 | ||
6f5794a6 RB |
208 | /* just for debugging; prints non-empty branches of the int ed tree |
209 | * inclusive iso eds */ | |
210 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
211 | { | |
3e326ece | 212 | int i, j; |
6f5794a6 RB |
213 | __u32 *ed_p; |
214 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
215 | j = 5; |
216 | ed_p = &(ohci->hcca->int_table [i]); | |
217 | if (*ed_p == 0) | |
218 | continue; | |
6f5794a6 | 219 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
220 | while (*ed_p != 0 && j--) { |
221 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
6f5794a6 | 222 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
223 | ed_p = &ed->hwNextED; |
224 | } | |
6f5794a6 | 225 | printf("\n"); |
3e326ece MK |
226 | } |
227 | } | |
228 | ||
6f5794a6 | 229 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 230 | { |
6f5794a6 | 231 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
232 | label, |
233 | mask, | |
234 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
235 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
236 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
237 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
238 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
239 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
240 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
241 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
242 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
243 | ); | |
244 | } | |
245 | ||
6f5794a6 | 246 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
247 | { |
248 | ed_t *edp = (ed_t *)value; | |
249 | ||
250 | if (value) { | |
6f5794a6 RB |
251 | dbg("%s %08x", label, value); |
252 | dbg("%08x", edp->hwINFO); | |
253 | dbg("%08x", edp->hwTailP); | |
254 | dbg("%08x", edp->hwHeadP); | |
255 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
256 | } |
257 | } | |
258 | ||
6f5794a6 | 259 | static char *hcfs2string(int state) |
3e326ece MK |
260 | { |
261 | switch (state) { | |
6f5794a6 RB |
262 | case OHCI_USB_RESET: return "reset"; |
263 | case OHCI_USB_RESUME: return "resume"; | |
264 | case OHCI_USB_OPER: return "operational"; | |
265 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
266 | } |
267 | return "?"; | |
268 | } | |
269 | ||
270 | /* dump control and status registers */ | |
6f5794a6 | 271 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
272 | { |
273 | struct ohci_regs *regs = controller->regs; | |
274 | __u32 temp; | |
275 | ||
a5496a18 | 276 | temp = ohci_readl(®s->revision) & 0xff; |
3e326ece | 277 | if (temp != 0x10) |
6f5794a6 | 278 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 279 | |
a5496a18 | 280 | temp = ohci_readl(®s->control); |
6f5794a6 | 281 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, |
3e326ece MK |
282 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
283 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
284 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 285 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
286 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
287 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
288 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
289 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
290 | temp & OHCI_CTRL_CBSR | |
291 | ); | |
292 | ||
a5496a18 | 293 | temp = ohci_readl(®s->cmdstatus); |
6f5794a6 | 294 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, |
3e326ece MK |
295 | (temp & OHCI_SOC) >> 16, |
296 | (temp & OHCI_OCR) ? " OCR" : "", | |
297 | (temp & OHCI_BLF) ? " BLF" : "", | |
298 | (temp & OHCI_CLF) ? " CLF" : "", | |
299 | (temp & OHCI_HCR) ? " HCR" : "" | |
300 | ); | |
301 | ||
a5496a18 BB |
302 | ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); |
303 | ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); | |
3e326ece | 304 | |
a5496a18 BB |
305 | maybe_print_eds("ed_periodcurrent", |
306 | ohci_readl(®s->ed_periodcurrent)); | |
3e326ece | 307 | |
a5496a18 BB |
308 | maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); |
309 | maybe_print_eds("ed_controlcurrent", | |
310 | ohci_readl(®s->ed_controlcurrent)); | |
3e326ece | 311 | |
a5496a18 BB |
312 | maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); |
313 | maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); | |
3e326ece | 314 | |
a5496a18 | 315 | maybe_print_eds("donehead", ohci_readl(®s->donehead)); |
3e326ece MK |
316 | } |
317 | ||
6f5794a6 | 318 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
319 | { |
320 | __u32 temp, ndp, i; | |
321 | ||
6f5794a6 | 322 | temp = roothub_a(controller); |
3e326ece MK |
323 | ndp = (temp & RH_A_NDP); |
324 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
325 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
326 | #endif |
327 | if (verbose) { | |
6f5794a6 | 328 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
329 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
330 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
331 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
332 | (temp & RH_A_DT) ? " DT" : "", | |
333 | (temp & RH_A_NPS) ? " NPS" : "", | |
334 | (temp & RH_A_PSM) ? " PSM" : "", | |
335 | ndp | |
336 | ); | |
6f5794a6 RB |
337 | temp = roothub_b(controller); |
338 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
339 | temp, |
340 | (temp & RH_B_PPCM) >> 16, | |
341 | (temp & RH_B_DR) | |
342 | ); | |
6f5794a6 RB |
343 | temp = roothub_status(controller); |
344 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
345 | temp, |
346 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
347 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
348 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
349 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
350 | (temp & RH_HS_OCI) ? " OCI" : "", | |
351 | (temp & RH_HS_LPS) ? " LPS" : "" | |
352 | ); | |
353 | } | |
354 | ||
355 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
356 | temp = roothub_portstatus(controller, i); |
357 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
358 | i, |
359 | temp, | |
360 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
361 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
362 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
363 | (temp & RH_PS_PESC) ? " PESC" : "", | |
364 | (temp & RH_PS_CSC) ? " CSC" : "", | |
365 | ||
366 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
367 | (temp & RH_PS_PPS) ? " PPS" : "", | |
368 | (temp & RH_PS_PRS) ? " PRS" : "", | |
369 | (temp & RH_PS_POCI) ? " POCI" : "", | |
370 | (temp & RH_PS_PSS) ? " PSS" : "", | |
371 | ||
372 | (temp & RH_PS_PES) ? " PES" : "", | |
373 | (temp & RH_PS_CCS) ? " CCS" : "" | |
374 | ); | |
375 | } | |
376 | } | |
377 | ||
6f5794a6 | 378 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 379 | { |
6f5794a6 | 380 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
381 | |
382 | /* dumps some of the state we know about */ | |
6f5794a6 | 383 | ohci_dump_status(controller); |
3e326ece | 384 | if (verbose) |
6f5794a6 RB |
385 | ep_print_int_eds(controller, "hcca"); |
386 | dbg("hcca frame #%04x", controller->hcca->frame_no); | |
387 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 388 | } |
3e326ece MK |
389 | #endif /* DEBUG */ |
390 | ||
391 | /*-------------------------------------------------------------------------* | |
392 | * Interface functions (URB) | |
393 | *-------------------------------------------------------------------------*/ | |
394 | ||
395 | /* get a transfer request */ | |
396 | ||
4dae14ce | 397 | int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) |
3e326ece MK |
398 | { |
399 | ohci_t *ohci; | |
6f5794a6 | 400 | ed_t *ed; |
4dae14ce | 401 | urb_priv_t *purb_priv = urb; |
3e326ece | 402 | int i, size = 0; |
4dae14ce ZW |
403 | struct usb_device *dev = urb->dev; |
404 | unsigned long pipe = urb->pipe; | |
405 | void *buffer = urb->transfer_buffer; | |
406 | int transfer_len = urb->transfer_buffer_length; | |
407 | int interval = urb->interval; | |
3e326ece MK |
408 | |
409 | ohci = &gohci; | |
410 | ||
411 | /* when controller's hung, permit only roothub cleanup attempts | |
412 | * such as powering down ports */ | |
413 | if (ohci->disabled) { | |
414 | err("sohci_submit_job: EPIPE"); | |
415 | return -1; | |
416 | } | |
ae79f606 | 417 | |
6f5794a6 RB |
418 | /* we're about to begin a new transaction here so mark the |
419 | * URB unfinished */ | |
4dae14ce | 420 | urb->finished = 0; |
3e326ece MK |
421 | |
422 | /* every endpoint has a ed, locate and fill it */ | |
6f5794a6 RB |
423 | ed = ep_add_ed(dev, pipe, interval, 1); |
424 | if (!ed) { | |
3e326ece MK |
425 | err("sohci_submit_job: ENOMEM"); |
426 | return -1; | |
427 | } | |
428 | ||
429 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
430 | switch (usb_pipetype(pipe)) { |
431 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
432 | size = (transfer_len - 1) / 4096 + 1; | |
433 | break; | |
434 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
435 | size = (transfer_len == 0)? 2: | |
436 | (transfer_len - 1) / 4096 + 3; | |
437 | break; | |
438 | case PIPE_INTERRUPT: /* 1 TD */ | |
439 | size = 1; | |
440 | break; | |
3e326ece MK |
441 | } |
442 | ||
4dae14ce ZW |
443 | ed->purb = urb; |
444 | ||
3e326ece MK |
445 | if (size >= (N_URB_TD - 1)) { |
446 | err("need %d TDs, only have %d", size, N_URB_TD); | |
447 | return -1; | |
448 | } | |
3e326ece MK |
449 | purb_priv->pipe = pipe; |
450 | ||
451 | /* fill the private part of the URB */ | |
452 | purb_priv->length = size; | |
453 | purb_priv->ed = ed; | |
454 | purb_priv->actual_length = 0; | |
455 | ||
456 | /* allocate the TDs */ | |
457 | /* note that td[0] was allocated in ep_add_ed */ | |
458 | for (i = 0; i < size; i++) { | |
6f5794a6 | 459 | purb_priv->td[i] = td_alloc(dev); |
3e326ece MK |
460 | if (!purb_priv->td[i]) { |
461 | purb_priv->length = i; | |
6f5794a6 | 462 | urb_free_priv(purb_priv); |
3e326ece MK |
463 | err("sohci_submit_job: ENOMEM"); |
464 | return -1; | |
465 | } | |
466 | } | |
467 | ||
468 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 469 | urb_free_priv(purb_priv); |
3e326ece MK |
470 | err("sohci_submit_job: EINVAL"); |
471 | return -1; | |
472 | } | |
473 | ||
474 | /* link the ed into a chain if is not already */ | |
475 | if (ed->state != ED_OPER) | |
6f5794a6 | 476 | ep_link(ohci, ed); |
3e326ece MK |
477 | |
478 | /* fill the TDs and link it to the ed */ | |
6f5794a6 RB |
479 | td_submit_job(dev, pipe, buffer, transfer_len, |
480 | setup, purb_priv, interval); | |
3e326ece MK |
481 | |
482 | return 0; | |
483 | } | |
484 | ||
4dae14ce ZW |
485 | static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) |
486 | { | |
487 | struct ohci_regs *regs = hc->regs; | |
488 | ||
6f5794a6 | 489 | switch (usb_pipetype(urb->pipe)) { |
4dae14ce ZW |
490 | case PIPE_INTERRUPT: |
491 | /* implicitly requeued */ | |
492 | if (urb->dev->irq_handle && | |
493 | (urb->dev->irq_act_len = urb->actual_length)) { | |
a5496a18 BB |
494 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
495 | ohci_readl(®s->intrenable); /* PCI posting flush */ | |
4dae14ce | 496 | urb->dev->irq_handle(urb->dev); |
a5496a18 BB |
497 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
498 | ohci_readl(®s->intrdisable); /* PCI posting flush */ | |
4dae14ce ZW |
499 | } |
500 | urb->actual_length = 0; | |
6f5794a6 | 501 | td_submit_job( |
4dae14ce ZW |
502 | urb->dev, |
503 | urb->pipe, | |
504 | urb->transfer_buffer, | |
505 | urb->transfer_buffer_length, | |
506 | NULL, | |
507 | urb, | |
508 | urb->interval); | |
509 | break; | |
510 | case PIPE_CONTROL: | |
511 | case PIPE_BULK: | |
512 | break; | |
513 | default: | |
514 | return 0; | |
515 | } | |
516 | return 1; | |
517 | } | |
518 | ||
3e326ece MK |
519 | /*-------------------------------------------------------------------------*/ |
520 | ||
521 | #ifdef DEBUG | |
522 | /* tell us the current USB frame number */ | |
523 | ||
6f5794a6 | 524 | static int sohci_get_current_frame_number(struct usb_device *usb_dev) |
3e326ece MK |
525 | { |
526 | ohci_t *ohci = &gohci; | |
527 | ||
6f5794a6 | 528 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
529 | } |
530 | #endif | |
531 | ||
4dae14ce ZW |
532 | /*-------------------------------------------------------------------------* |
533 | * ED handling functions | |
534 | *-------------------------------------------------------------------------*/ | |
535 | ||
536 | /* search for the right branch to insert an interrupt ed into the int tree | |
537 | * do some load ballancing; | |
538 | * returns the branch and | |
539 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
540 | ||
6f5794a6 | 541 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
542 | { |
543 | int i, branch = 0; | |
544 | ||
545 | /* search for the least loaded interrupt endpoint | |
546 | * branch of all 32 branches | |
547 | */ | |
548 | for (i = 0; i < 32; i++) | |
549 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
550 | branch = i; | |
551 | ||
552 | branch = branch % interval; | |
553 | for (i = branch; i < 32; i += interval) | |
554 | ohci->ohci_int_load [i] += load; | |
555 | ||
556 | return branch; | |
557 | } | |
558 | ||
559 | /*-------------------------------------------------------------------------*/ | |
560 | ||
561 | /* 2^int( ld (inter)) */ | |
562 | ||
6f5794a6 | 563 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
564 | { |
565 | int i; | |
6f5794a6 | 566 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
567 | return 1 << i; |
568 | } | |
569 | ||
570 | /*-------------------------------------------------------------------------*/ | |
571 | ||
572 | /* the int tree is a binary tree | |
6f5794a6 RB |
573 | * in order to process it sequentially the indexes of the branches have to |
574 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
575 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
576 | { |
577 | int i, wout = 0; | |
578 | ||
579 | for (i = 0; i < num_bits; i++) | |
580 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
581 | return wout; | |
582 | } | |
583 | ||
3e326ece MK |
584 | /*-------------------------------------------------------------------------* |
585 | * ED handling functions | |
586 | *-------------------------------------------------------------------------*/ | |
587 | ||
588 | /* link an ed into one of the HC chains */ | |
589 | ||
6f5794a6 | 590 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
591 | { |
592 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
593 | int int_branch; |
594 | int i; | |
595 | int inter; | |
596 | int interval; | |
597 | int load; | |
6f5794a6 | 598 | __u32 *ed_p; |
3e326ece MK |
599 | |
600 | ed->state = ED_OPER; | |
4dae14ce | 601 | ed->int_interval = 0; |
3e326ece MK |
602 | |
603 | switch (ed->type) { | |
604 | case PIPE_CONTROL: | |
605 | ed->hwNextED = 0; | |
6f5794a6 | 606 | if (ohci->ed_controltail == NULL) |
a5496a18 | 607 | ohci_writel(ed, &ohci->regs->ed_controlhead); |
6f5794a6 RB |
608 | else |
609 | ohci->ed_controltail->hwNextED = | |
610 | m32_swap((unsigned long)ed); | |
611 | ||
3e326ece MK |
612 | ed->ed_prev = ohci->ed_controltail; |
613 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
614 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
615 | ohci->hc_control |= OHCI_CTRL_CLE; | |
a5496a18 | 616 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
617 | } |
618 | ohci->ed_controltail = edi; | |
619 | break; | |
620 | ||
621 | case PIPE_BULK: | |
622 | ed->hwNextED = 0; | |
6f5794a6 | 623 | if (ohci->ed_bulktail == NULL) |
a5496a18 | 624 | ohci_writel(ed, &ohci->regs->ed_bulkhead); |
6f5794a6 RB |
625 | else |
626 | ohci->ed_bulktail->hwNextED = | |
627 | m32_swap((unsigned long)ed); | |
628 | ||
3e326ece MK |
629 | ed->ed_prev = ohci->ed_bulktail; |
630 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
631 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
632 | ohci->hc_control |= OHCI_CTRL_BLE; | |
a5496a18 | 633 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
634 | } |
635 | ohci->ed_bulktail = edi; | |
636 | break; | |
4dae14ce ZW |
637 | |
638 | case PIPE_INTERRUPT: | |
639 | load = ed->int_load; | |
6f5794a6 | 640 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 641 | ed->int_interval = interval; |
6f5794a6 | 642 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
643 | ed->int_branch = int_branch; |
644 | ||
6f5794a6 | 645 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 646 | inter = 1; |
6f5794a6 RB |
647 | for (ed_p = &(ohci->hcca->int_table[\ |
648 | ep_rev(5, i) + int_branch]); | |
649 | (*ed_p != 0) && | |
650 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 651 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
652 | inter = ep_rev(6, |
653 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 654 | ed->hwNextED = *ed_p; |
4a8527ef | 655 | *ed_p = m32_swap((unsigned long)ed); |
4dae14ce ZW |
656 | } |
657 | break; | |
3e326ece MK |
658 | } |
659 | return 0; | |
660 | } | |
661 | ||
662 | /*-------------------------------------------------------------------------*/ | |
663 | ||
4dae14ce | 664 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
665 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
666 | unsigned index, unsigned period) | |
4dae14ce ZW |
667 | { |
668 | for (; index < NUM_INTS; index += period) { | |
669 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
670 | ||
671 | /* ED might have been unlinked through another path */ | |
672 | while (*ed_p != 0) { | |
6f5794a6 RB |
673 | if (((struct ed *) |
674 | m32_swap((unsigned long)ed_p)) == ed) { | |
4dae14ce ZW |
675 | *ed_p = ed->hwNextED; |
676 | break; | |
677 | } | |
6f5794a6 RB |
678 | ed_p = &(((struct ed *) |
679 | m32_swap((unsigned long)ed_p))->hwNextED); | |
4dae14ce ZW |
680 | } |
681 | } | |
682 | } | |
683 | ||
3e326ece MK |
684 | /* unlink an ed from one of the HC chains. |
685 | * just the link to the ed is unlinked. | |
686 | * the link from the ed still points to another operational ed or 0 | |
687 | * so the HC can eventually finish the processing of the unlinked ed */ | |
688 | ||
6f5794a6 | 689 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 690 | { |
53e336e9 | 691 | volatile ed_t *ed = edi; |
4dae14ce | 692 | int i; |
53e336e9 | 693 | |
6f5794a6 | 694 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
3e326ece MK |
695 | |
696 | switch (ed->type) { | |
697 | case PIPE_CONTROL: | |
698 | if (ed->ed_prev == NULL) { | |
699 | if (!ed->hwNextED) { | |
700 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
a5496a18 BB |
701 | ohci_writel(ohci->hc_control, |
702 | &ohci->regs->control); | |
3e326ece | 703 | } |
a5496a18 | 704 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 705 | &ohci->regs->ed_controlhead); |
3e326ece MK |
706 | } else { |
707 | ed->ed_prev->hwNextED = ed->hwNextED; | |
708 | } | |
709 | if (ohci->ed_controltail == ed) { | |
710 | ohci->ed_controltail = ed->ed_prev; | |
711 | } else { | |
6f5794a6 RB |
712 | ((ed_t *)m32_swap( |
713 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
714 | } |
715 | break; | |
716 | ||
717 | case PIPE_BULK: | |
718 | if (ed->ed_prev == NULL) { | |
719 | if (!ed->hwNextED) { | |
720 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
a5496a18 BB |
721 | ohci_writel(ohci->hc_control, |
722 | &ohci->regs->control); | |
3e326ece | 723 | } |
a5496a18 | 724 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 725 | &ohci->regs->ed_bulkhead); |
3e326ece MK |
726 | } else { |
727 | ed->ed_prev->hwNextED = ed->hwNextED; | |
728 | } | |
729 | if (ohci->ed_bulktail == ed) { | |
730 | ohci->ed_bulktail = ed->ed_prev; | |
731 | } else { | |
6f5794a6 RB |
732 | ((ed_t *)m32_swap( |
733 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
734 | } |
735 | break; | |
4dae14ce ZW |
736 | |
737 | case PIPE_INTERRUPT: | |
6f5794a6 | 738 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
739 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
740 | ohci->ohci_int_load[i] -= ed->int_load; | |
741 | break; | |
3e326ece MK |
742 | } |
743 | ed->state = ED_UNLINK; | |
744 | return 0; | |
745 | } | |
746 | ||
3e326ece MK |
747 | /*-------------------------------------------------------------------------*/ |
748 | ||
ddf83a2f MK |
749 | /* add/reinit an endpoint; this should be done once at the |
750 | * usb_set_configuration command, but the USB stack is a little bit | |
751 | * stateless so we do it at every transaction if the state of the ed | |
752 | * is ED_NEW then a dummy td is added and the state is changed to | |
753 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
754 | * info fields are setted anyway even though most of them should not | |
755 | * change | |
756 | */ | |
6f5794a6 RB |
757 | static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, |
758 | int interval, int load) | |
3e326ece MK |
759 | { |
760 | td_t *td; | |
761 | ed_t *ed_ret; | |
762 | volatile ed_t *ed; | |
763 | ||
6f5794a6 RB |
764 | ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | |
765 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; | |
3e326ece MK |
766 | |
767 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
768 | err("ep_add_ed: pending delete"); | |
769 | /* pending delete request */ | |
770 | return NULL; | |
771 | } | |
772 | ||
773 | if (ed->state == ED_NEW) { | |
3e326ece | 774 | /* dummy td; end of td list for ed */ |
6f5794a6 RB |
775 | td = td_alloc(usb_dev); |
776 | ed->hwTailP = m32_swap((unsigned long)td); | |
3e326ece MK |
777 | ed->hwHeadP = ed->hwTailP; |
778 | ed->state = ED_UNLINK; | |
6f5794a6 | 779 | ed->type = usb_pipetype(pipe); |
3e326ece MK |
780 | ohci_dev.ed_cnt++; |
781 | } | |
782 | ||
6f5794a6 RB |
783 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
784 | | usb_pipeendpoint(pipe) << 7 | |
785 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
786 | | (usb_pipecontrol(pipe)? 0: \ | |
787 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
c60795f4 | 788 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
6f5794a6 | 789 | | usb_maxpacket(usb_dev, pipe) << 16); |
3e326ece | 790 | |
4dae14ce ZW |
791 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
792 | ed->int_period = interval; | |
793 | ed->int_load = load; | |
794 | } | |
795 | ||
3e326ece MK |
796 | return ed_ret; |
797 | } | |
798 | ||
799 | /*-------------------------------------------------------------------------* | |
800 | * TD handling functions | |
801 | *-------------------------------------------------------------------------*/ | |
802 | ||
803 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
804 | ||
6f5794a6 | 805 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
806 | void *data, int len, |
807 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
808 | { | |
809 | volatile td_t *td, *td_pt; | |
810 | #ifdef OHCI_FILL_TRACE | |
811 | int i; | |
812 | #endif | |
813 | ||
814 | if (index > urb_priv->length) { | |
815 | err("index > length"); | |
816 | return; | |
817 | } | |
818 | /* use this td as the next dummy */ | |
819 | td_pt = urb_priv->td [index]; | |
820 | td_pt->hwNextTD = 0; | |
821 | ||
822 | /* fill the old dummy TD */ | |
6f5794a6 RB |
823 | td = urb_priv->td [index] = |
824 | (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
825 | |
826 | td->ed = urb_priv->ed; | |
827 | td->next_dl_td = NULL; | |
828 | td->index = index; | |
829 | td->data = (__u32)data; | |
830 | #ifdef OHCI_FILL_TRACE | |
48867208 | 831 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 832 | for (i = 0; i < len; i++) |
6f5794a6 | 833 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
834 | printf("\n"); |
835 | } | |
836 | #endif | |
837 | if (!len) | |
838 | data = 0; | |
839 | ||
6f5794a6 RB |
840 | td->hwINFO = m32_swap(info); |
841 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 842 | if (data) |
6f5794a6 | 843 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
844 | else |
845 | td->hwBE = 0; | |
6f5794a6 RB |
846 | |
847 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
3e326ece MK |
848 | |
849 | /* append to queue */ | |
850 | td->ed->hwTailP = td->hwNextTD; | |
851 | } | |
852 | ||
853 | /*-------------------------------------------------------------------------*/ | |
854 | ||
855 | /* prepare all TDs of a transfer */ | |
856 | ||
6f5794a6 RB |
857 | static void td_submit_job(struct usb_device *dev, unsigned long pipe, |
858 | void *buffer, int transfer_len, | |
859 | struct devrequest *setup, urb_priv_t *urb, | |
860 | int interval) | |
3e326ece MK |
861 | { |
862 | ohci_t *ohci = &gohci; | |
863 | int data_len = transfer_len; | |
864 | void *data; | |
865 | int cnt = 0; | |
866 | __u32 info = 0; | |
867 | unsigned int toggle = 0; | |
868 | ||
6f5794a6 RB |
869 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
870 | * bits for reseting */ | |
871 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
3e326ece MK |
872 | toggle = TD_T_TOGGLE; |
873 | } else { | |
874 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
875 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
876 | usb_pipeout(pipe), 1); | |
3e326ece MK |
877 | } |
878 | urb->td_cnt = 0; | |
879 | if (data_len) | |
880 | data = buffer; | |
881 | else | |
882 | data = 0; | |
883 | ||
6f5794a6 | 884 | switch (usb_pipetype(pipe)) { |
3e326ece | 885 | case PIPE_BULK: |
6f5794a6 | 886 | info = usb_pipeout(pipe)? |
3e326ece | 887 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
888 | while (data_len > 4096) { |
889 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
890 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
891 | data += 4096; data_len -= 4096; cnt++; |
892 | } | |
6f5794a6 | 893 | info = usb_pipeout(pipe)? |
3e326ece | 894 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
895 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
896 | data_len, dev, cnt, urb); | |
3e326ece MK |
897 | cnt++; |
898 | ||
6f5794a6 RB |
899 | if (!ohci->sleeping) { |
900 | /* start bulk list */ | |
a5496a18 | 901 | ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); |
6f5794a6 | 902 | } |
3e326ece MK |
903 | break; |
904 | ||
905 | case PIPE_CONTROL: | |
6f5794a6 | 906 | /* Setup phase */ |
3e326ece | 907 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
6f5794a6 RB |
908 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
909 | ||
910 | /* Optional Data phase */ | |
3e326ece | 911 | if (data_len > 0) { |
6f5794a6 RB |
912 | info = usb_pipeout(pipe)? |
913 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
914 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 915 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
916 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
917 | } | |
918 | ||
919 | /* Status phase */ | |
920 | info = usb_pipeout(pipe)? | |
921 | TD_CC | TD_DP_IN | TD_T_DATA1: | |
922 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
923 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
924 | ||
925 | if (!ohci->sleeping) { | |
926 | /* start Control list */ | |
a5496a18 | 927 | ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); |
3e326ece | 928 | } |
3e326ece | 929 | break; |
4dae14ce ZW |
930 | |
931 | case PIPE_INTERRUPT: | |
6f5794a6 | 932 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
933 | TD_CC | TD_DP_OUT | toggle: |
934 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 935 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 936 | break; |
3e326ece MK |
937 | } |
938 | if (urb->length != cnt) | |
939 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
940 | } | |
941 | ||
942 | /*-------------------------------------------------------------------------* | |
943 | * Done List handling functions | |
944 | *-------------------------------------------------------------------------*/ | |
945 | ||
3e326ece MK |
946 | /* calculate the transfer length and update the urb */ |
947 | ||
6f5794a6 | 948 | static void dl_transfer_length(td_t *td) |
3e326ece | 949 | { |
6bc52ef3 | 950 | __u32 tdBE, tdCBP; |
4dae14ce | 951 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 952 | |
6f5794a6 RB |
953 | tdBE = m32_swap(td->hwBE); |
954 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 955 | |
48867208 | 956 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
957 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
958 | if (tdBE != 0) { | |
959 | if (td->hwCBP == 0) | |
960 | lurb_priv->actual_length += tdBE - td->data + 1; | |
961 | else | |
962 | lurb_priv->actual_length += tdCBP - td->data; | |
963 | } | |
964 | } | |
965 | } | |
966 | ||
967 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
968 | static void check_status(td_t *td_list) |
969 | { | |
970 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
971 | int urb_len = lurb_priv->length; | |
972 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
973 | int cc; | |
974 | ||
975 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
976 | if (cc) { | |
977 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
978 | ||
979 | if (*phwHeadP & m32_swap(0x1)) { | |
980 | if (lurb_priv && | |
981 | ((td_list->index + 1) < urb_len)) { | |
982 | *phwHeadP = | |
983 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
984 | m32_swap(0xfffffff0)) | | |
985 | (*phwHeadP & m32_swap(0x2)); | |
986 | ||
987 | lurb_priv->td_cnt += urb_len - | |
988 | td_list->index - 1; | |
989 | } else | |
990 | *phwHeadP &= m32_swap(0xfffffff2); | |
991 | } | |
992 | #ifdef CONFIG_MPC5200 | |
993 | td_list->hwNextTD = 0; | |
994 | #endif | |
995 | } | |
996 | } | |
3e326ece MK |
997 | |
998 | /* replies to the request have to be on a FIFO basis so | |
999 | * we reverse the reversed done-list */ | |
6f5794a6 | 1000 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece MK |
1001 | { |
1002 | __u32 td_list_hc; | |
1003 | td_t *td_rev = NULL; | |
1004 | td_t *td_list = NULL; | |
3e326ece | 1005 | |
6f5794a6 | 1006 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece MK |
1007 | ohci->hcca->done_head = 0; |
1008 | ||
1009 | while (td_list_hc) { | |
1010 | td_list = (td_t *)td_list_hc; | |
6f5794a6 | 1011 | check_status(td_list); |
3e326ece MK |
1012 | td_list->next_dl_td = td_rev; |
1013 | td_rev = td_list; | |
6f5794a6 | 1014 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1015 | } |
1016 | return td_list; | |
1017 | } | |
1018 | ||
6f5794a6 | 1019 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1020 | /*-------------------------------------------------------------------------*/ |
1021 | ||
6f5794a6 RB |
1022 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1023 | { | |
1024 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
1025 | urb->finished = sohci_return_job(ohci, urb); | |
1026 | else | |
1027 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1028 | } | |
1029 | ||
1030 | /* | |
1031 | * Used to take back a TD from the host controller. This would normally be | |
1032 | * called from within dl_done_list, however it may be called directly if the | |
1033 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1034 | * two frames). This bug has been observed on ZF Micro systems. | |
1035 | */ | |
1036 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1037 | { |
3e326ece | 1038 | ed_t *ed; |
6f5794a6 | 1039 | int cc; |
3e326ece MK |
1040 | int stat = 0; |
1041 | /* urb_t *urb; */ | |
1042 | urb_priv_t *lurb_priv; | |
1043 | __u32 tdINFO, edHeadP, edTailP; | |
1044 | ||
6f5794a6 | 1045 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1046 | |
6f5794a6 RB |
1047 | ed = td_list->ed; |
1048 | lurb_priv = ed->purb; | |
3e326ece | 1049 | |
6f5794a6 | 1050 | dl_transfer_length(td_list); |
3e326ece | 1051 | |
6f5794a6 | 1052 | lurb_priv->td_cnt++; |
3e326ece | 1053 | |
6f5794a6 RB |
1054 | /* error code of transfer */ |
1055 | cc = TD_CC_GET(tdINFO); | |
1056 | if (cc) { | |
1057 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1058 | stat = cc_to_error[cc]; | |
1059 | } | |
ae79f606 | 1060 | |
6f5794a6 RB |
1061 | /* see if this done list makes for all TD's of current URB, |
1062 | * and mark the URB finished if so */ | |
1063 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1064 | finish_urb(ohci, lurb_priv, ed->state); | |
1065 | ||
1066 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1067 | lurb_priv->td_cnt, lurb_priv->length); | |
1068 | ||
48867208 | 1069 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
6f5794a6 RB |
1070 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1071 | edTailP = m32_swap(ed->hwTailP); | |
1072 | ||
1073 | /* unlink eds if they are not busy */ | |
1074 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1075 | ep_unlink(ohci, ed); | |
1076 | } | |
1077 | return stat; | |
1078 | } | |
3e326ece | 1079 | |
6f5794a6 RB |
1080 | static int dl_done_list(ohci_t *ohci) |
1081 | { | |
1082 | int stat = 0; | |
1083 | td_t *td_list = dl_reverse_done_list(ohci); | |
1084 | ||
1085 | while (td_list) { | |
1086 | td_t *td_next = td_list->next_dl_td; | |
1087 | stat = takeback_td(ohci, td_list); | |
1088 | td_list = td_next; | |
3e326ece MK |
1089 | } |
1090 | return stat; | |
1091 | } | |
1092 | ||
1093 | /*-------------------------------------------------------------------------* | |
1094 | * Virtual Root Hub | |
1095 | *-------------------------------------------------------------------------*/ | |
1096 | ||
eb838e7d | 1097 | #include <usbroothubdes.h> |
3e326ece MK |
1098 | |
1099 | /* Hub class-specific descriptor is constructed dynamically */ | |
1100 | ||
3e326ece MK |
1101 | /*-------------------------------------------------------------------------*/ |
1102 | ||
1103 | #define OK(x) len = (x); break | |
1104 | #ifdef DEBUG | |
a5496a18 | 1105 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ |
6f5794a6 RB |
1106 | &gohci.regs->roothub.status); } |
1107 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ | |
a5496a18 | 1108 | (x)); ohci_writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); } |
3e326ece | 1109 | #else |
a5496a18 BB |
1110 | #define WR_RH_STAT(x) ohci_writel((x), &gohci.regs->roothub.status) |
1111 | #define WR_RH_PORTSTAT(x) ohci_writel((x), \ | |
6f5794a6 | 1112 | &gohci.regs->roothub.portstatus[wIndex-1]) |
3e326ece MK |
1113 | #endif |
1114 | #define RD_RH_STAT roothub_status(&gohci) | |
6f5794a6 | 1115 | #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) |
3e326ece MK |
1116 | |
1117 | /* request to virtual root hub */ | |
1118 | ||
1119 | int rh_check_port_status(ohci_t *controller) | |
1120 | { | |
1121 | __u32 temp, ndp, i; | |
1122 | int res; | |
1123 | ||
1124 | res = -1; | |
6f5794a6 | 1125 | temp = roothub_a(controller); |
3e326ece MK |
1126 | ndp = (temp & RH_A_NDP); |
1127 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1128 | ndp = (ndp == 2) ? 1:0; | |
1129 | #endif | |
1130 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1131 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1132 | /* check for a device disconnect */ |
1133 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1134 | (RH_PS_PESC | RH_PS_CSC)) && | |
1135 | ((temp & RH_PS_CCS) == 0)) { | |
1136 | res = i; | |
1137 | break; | |
1138 | } | |
1139 | } | |
1140 | return res; | |
1141 | } | |
1142 | ||
1143 | static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, | |
1144 | void *buffer, int transfer_len, struct devrequest *cmd) | |
1145 | { | |
6f5794a6 | 1146 | void *data = buffer; |
3e326ece MK |
1147 | int leni = transfer_len; |
1148 | int len = 0; | |
1149 | int stat = 0; | |
3e326ece MK |
1150 | __u16 bmRType_bReq; |
1151 | __u16 wValue; | |
1152 | __u16 wIndex; | |
1153 | __u16 wLength; | |
f1273f11 | 1154 | ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); |
5f6aa03f | 1155 | |
3e326ece | 1156 | #ifdef DEBUG |
6f5794a6 RB |
1157 | pkt_print(NULL, dev, pipe, buffer, transfer_len, |
1158 | cmd, "SUB(rh)", usb_pipein(pipe)); | |
3e326ece | 1159 | #else |
5b84dd67 | 1160 | mdelay(1); |
3e326ece | 1161 | #endif |
48867208 | 1162 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1163 | info("Root-Hub submit IRQ: NOT implemented"); |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1168 | wValue = le16_to_cpu(cmd->value); |
1169 | wIndex = le16_to_cpu(cmd->index); | |
1170 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1171 | |
1172 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1173 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1174 | ||
1175 | switch (bmRType_bReq) { | |
1176 | /* Request Destination: | |
1177 | without flags: Device, | |
1178 | RH_INTERFACE: interface, | |
1179 | RH_ENDPOINT: endpoint, | |
1180 | RH_CLASS means HUB here, | |
1181 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1182 | */ | |
1183 | ||
1184 | case RH_GET_STATUS: | |
f1273f11 | 1185 | *(u16 *)databuf = cpu_to_le16(1); |
6f5794a6 | 1186 | OK(2); |
3e326ece | 1187 | case RH_GET_STATUS | RH_INTERFACE: |
f1273f11 | 1188 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1189 | OK(2); |
3e326ece | 1190 | case RH_GET_STATUS | RH_ENDPOINT: |
f1273f11 | 1191 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1192 | OK(2); |
3e326ece | 1193 | case RH_GET_STATUS | RH_CLASS: |
f1273f11 | 1194 | *(u32 *)databuf = cpu_to_le32( |
3e326ece | 1195 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1196 | OK(4); |
3e326ece | 1197 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
f1273f11 | 1198 | *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); |
6f5794a6 | 1199 | OK(4); |
3e326ece MK |
1200 | |
1201 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1202 | switch (wValue) { | |
6f5794a6 RB |
1203 | case (RH_ENDPOINT_STALL): |
1204 | OK(0); | |
3e326ece MK |
1205 | } |
1206 | break; | |
1207 | ||
1208 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1209 | switch (wValue) { | |
6f5794a6 RB |
1210 | case RH_C_HUB_LOCAL_POWER: |
1211 | OK(0); | |
1212 | case (RH_C_HUB_OVER_CURRENT): | |
1213 | WR_RH_STAT(RH_HS_OCIC); | |
1214 | OK(0); | |
3e326ece MK |
1215 | } |
1216 | break; | |
1217 | ||
1218 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1219 | switch (wValue) { | |
6f5794a6 RB |
1220 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1221 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1222 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1223 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1224 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1225 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1226 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1227 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1228 | } |
1229 | break; | |
1230 | ||
1231 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1232 | switch (wValue) { | |
6f5794a6 RB |
1233 | case (RH_PORT_SUSPEND): |
1234 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1235 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1236 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1237 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1238 | OK(0); | |
1239 | case (RH_PORT_POWER): | |
1240 | WR_RH_PORTSTAT(RH_PS_PPS); | |
5b84dd67 | 1241 | mdelay(100); |
6f5794a6 RB |
1242 | OK(0); |
1243 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1244 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1245 | WR_RH_PORTSTAT(RH_PS_PES); | |
1246 | OK(0); | |
3e326ece MK |
1247 | } |
1248 | break; | |
1249 | ||
6f5794a6 RB |
1250 | case RH_SET_ADDRESS: |
1251 | gohci.rh.devnum = wValue; | |
1252 | OK(0); | |
3e326ece MK |
1253 | |
1254 | case RH_GET_DESCRIPTOR: | |
1255 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1256 | case (0x01): /* device descriptor */ |
1257 | len = min_t(unsigned int, | |
1258 | leni, | |
1259 | min_t(unsigned int, | |
1260 | sizeof(root_hub_dev_des), | |
1261 | wLength)); | |
f1273f11 | 1262 | databuf = root_hub_dev_des; OK(len); |
6f5794a6 RB |
1263 | case (0x02): /* configuration descriptor */ |
1264 | len = min_t(unsigned int, | |
1265 | leni, | |
1266 | min_t(unsigned int, | |
1267 | sizeof(root_hub_config_des), | |
1268 | wLength)); | |
f1273f11 | 1269 | databuf = root_hub_config_des; OK(len); |
6f5794a6 RB |
1270 | case (0x03): /* string descriptors */ |
1271 | if (wValue == 0x0300) { | |
3e326ece | 1272 | len = min_t(unsigned int, |
6f5794a6 RB |
1273 | leni, |
1274 | min_t(unsigned int, | |
1275 | sizeof(root_hub_str_index0), | |
1276 | wLength)); | |
f1273f11 | 1277 | databuf = root_hub_str_index0; |
6f5794a6 | 1278 | OK(len); |
3e326ece | 1279 | } |
6f5794a6 RB |
1280 | if (wValue == 0x0301) { |
1281 | len = min_t(unsigned int, | |
1282 | leni, | |
1283 | min_t(unsigned int, | |
1284 | sizeof(root_hub_str_index1), | |
1285 | wLength)); | |
f1273f11 | 1286 | databuf = root_hub_str_index1; |
6f5794a6 RB |
1287 | OK(len); |
1288 | } | |
1289 | default: | |
1290 | stat = USB_ST_STALLED; | |
3e326ece MK |
1291 | } |
1292 | break; | |
1293 | ||
1294 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1295 | { | |
6f5794a6 | 1296 | __u32 temp = roothub_a(&gohci); |
3e326ece | 1297 | |
f1273f11 TK |
1298 | databuf[0] = 9; /* min length; */ |
1299 | databuf[1] = 0x29; | |
1300 | databuf[2] = temp & RH_A_NDP; | |
3e326ece | 1301 | #ifdef CONFIG_AT91C_PQFP_UHPBUG |
f1273f11 | 1302 | databuf[2] = (databuf[2] == 2) ? 1 : 0; |
3e326ece | 1303 | #endif |
f1273f11 | 1304 | databuf[3] = 0; |
3e326ece | 1305 | if (temp & RH_A_PSM) /* per-port power switching? */ |
f1273f11 | 1306 | databuf[3] |= 0x1; |
3e326ece | 1307 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ |
f1273f11 | 1308 | databuf[3] |= 0x10; |
6f5794a6 | 1309 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
f1273f11 | 1310 | databuf[3] |= 0x8; |
3e326ece | 1311 | |
f1273f11 TK |
1312 | databuf[4] = 0; |
1313 | databuf[5] = (temp & RH_A_POTPGT) >> 24; | |
1314 | databuf[6] = 0; | |
6f5794a6 | 1315 | temp = roothub_b(&gohci); |
f1273f11 TK |
1316 | databuf[7] = temp & RH_B_DR; |
1317 | if (databuf[2] < 7) { | |
1318 | databuf[8] = 0xff; | |
3e326ece | 1319 | } else { |
f1273f11 TK |
1320 | databuf[0] += 2; |
1321 | databuf[8] = (temp & RH_B_DR) >> 8; | |
1322 | databuf[10] = databuf[9] = 0xff; | |
3e326ece MK |
1323 | } |
1324 | ||
1325 | len = min_t(unsigned int, leni, | |
f1273f11 | 1326 | min_t(unsigned int, databuf[0], wLength)); |
6f5794a6 | 1327 | OK(len); |
3e326ece MK |
1328 | } |
1329 | ||
5f6aa03f | 1330 | case RH_GET_CONFIGURATION: |
f1273f11 | 1331 | databuf[0] = 0x01; |
5f6aa03f | 1332 | OK(1); |
3e326ece | 1333 | |
5f6aa03f MV |
1334 | case RH_SET_CONFIGURATION: |
1335 | WR_RH_STAT(0x10000); | |
1336 | OK(0); | |
3e326ece MK |
1337 | |
1338 | default: | |
6f5794a6 | 1339 | dbg("unsupported root hub command"); |
3e326ece MK |
1340 | stat = USB_ST_STALLED; |
1341 | } | |
1342 | ||
1343 | #ifdef DEBUG | |
6f5794a6 | 1344 | ohci_dump_roothub(&gohci, 1); |
3e326ece | 1345 | #else |
5b84dd67 | 1346 | mdelay(1); |
3e326ece MK |
1347 | #endif |
1348 | ||
1349 | len = min_t(int, len, leni); | |
f1273f11 TK |
1350 | if (data != databuf) |
1351 | memcpy(data, databuf, len); | |
3e326ece MK |
1352 | dev->act_len = len; |
1353 | dev->status = stat; | |
1354 | ||
1355 | #ifdef DEBUG | |
6f5794a6 RB |
1356 | pkt_print(NULL, dev, pipe, buffer, |
1357 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); | |
3e326ece | 1358 | #else |
5b84dd67 | 1359 | mdelay(1); |
3e326ece MK |
1360 | #endif |
1361 | ||
1362 | return stat; | |
1363 | } | |
1364 | ||
1365 | /*-------------------------------------------------------------------------*/ | |
1366 | ||
1367 | /* common code for handling submit messages - used for all but root hub */ | |
1368 | /* accesses. */ | |
1369 | int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1370 | int transfer_len, struct devrequest *setup, int interval) | |
1371 | { | |
1372 | int stat = 0; | |
1373 | int maxsize = usb_maxpacket(dev, pipe); | |
1374 | int timeout; | |
4dae14ce ZW |
1375 | urb_priv_t *urb; |
1376 | ||
1377 | urb = malloc(sizeof(urb_priv_t)); | |
1378 | memset(urb, 0, sizeof(urb_priv_t)); | |
1379 | ||
1380 | urb->dev = dev; | |
1381 | urb->pipe = pipe; | |
1382 | urb->transfer_buffer = buffer; | |
1383 | urb->transfer_buffer_length = transfer_len; | |
1384 | urb->interval = interval; | |
3e326ece MK |
1385 | |
1386 | /* device pulled? Shortcut the action. */ | |
1387 | if (devgone == dev) { | |
1388 | dev->status = USB_ST_CRC_ERR; | |
1389 | return 0; | |
1390 | } | |
1391 | ||
1392 | #ifdef DEBUG | |
4dae14ce | 1393 | urb->actual_length = 0; |
6f5794a6 RB |
1394 | pkt_print(urb, dev, pipe, buffer, transfer_len, |
1395 | setup, "SUB", usb_pipein(pipe)); | |
3e326ece | 1396 | #else |
5b84dd67 | 1397 | mdelay(1); |
3e326ece MK |
1398 | #endif |
1399 | if (!maxsize) { | |
1400 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1401 | pipe); | |
1402 | return -1; | |
1403 | } | |
1404 | ||
4dae14ce | 1405 | if (sohci_submit_job(urb, setup) < 0) { |
3e326ece MK |
1406 | err("sohci_submit_job failed"); |
1407 | return -1; | |
1408 | } | |
1409 | ||
ae3b770e | 1410 | #if 0 |
5b84dd67 | 1411 | mdelay(10); |
3e326ece | 1412 | /* ohci_dump_status(&gohci); */ |
ae3b770e | 1413 | #endif |
3e326ece | 1414 | |
96820a35 | 1415 | timeout = USB_TIMEOUT_MS(pipe); |
3e326ece MK |
1416 | |
1417 | /* wait for it to complete */ | |
1418 | for (;;) { | |
1419 | /* check whether the controller is done */ | |
1420 | stat = hc_interrupt(); | |
1421 | if (stat < 0) { | |
1422 | stat = USB_ST_CRC_ERR; | |
1423 | break; | |
1424 | } | |
ddf83a2f | 1425 | |
ddf83a2f MK |
1426 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1427 | * handle only one URB at a time, we cannot assume the | |
1428 | * transaction finished on the first successful return from | |
1429 | * hc_interrupt().. unless the flag for current URB is set, | |
1430 | * meaning that all TD's to/from device got actually | |
1431 | * transferred and processed. If the current URB is not | |
1432 | * finished we need to re-iterate this loop so as | |
1433 | * hc_interrupt() gets called again as there needs to be some | |
1434 | * more TD's to process still */ | |
4dae14ce | 1435 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1436 | /* 0xff is returned for an SF-interrupt */ |
1437 | break; | |
1438 | } | |
ddf83a2f | 1439 | |
3e326ece | 1440 | if (--timeout) { |
5b84dd67 | 1441 | mdelay(1); |
4dae14ce | 1442 | if (!urb->finished) |
6f5794a6 | 1443 | dbg("*"); |
4dae14ce | 1444 | |
3e326ece MK |
1445 | } else { |
1446 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1447 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1448 | urb->finished = 1; |
3e326ece MK |
1449 | stat = USB_ST_CRC_ERR; |
1450 | break; | |
1451 | } | |
1452 | } | |
3e326ece MK |
1453 | |
1454 | dev->status = stat; | |
522c9564 | 1455 | dev->act_len = urb->actual_length; |
3e326ece MK |
1456 | |
1457 | #ifdef DEBUG | |
6f5794a6 RB |
1458 | pkt_print(urb, dev, pipe, buffer, transfer_len, |
1459 | setup, "RET(ctlr)", usb_pipein(pipe)); | |
3e326ece | 1460 | #else |
5b84dd67 | 1461 | mdelay(1); |
3e326ece MK |
1462 | #endif |
1463 | ||
1464 | /* free TDs in urb_priv */ | |
48867208 | 1465 | if (!usb_pipeint(pipe)) |
6f5794a6 | 1466 | urb_free_priv(urb); |
3e326ece MK |
1467 | return 0; |
1468 | } | |
1469 | ||
1470 | /* submit routines called from usb.c */ | |
1471 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1472 | int transfer_len) | |
1473 | { | |
1474 | info("submit_bulk_msg"); | |
1475 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); | |
1476 | } | |
1477 | ||
1478 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1479 | int transfer_len, struct devrequest *setup) | |
1480 | { | |
1481 | int maxsize = usb_maxpacket(dev, pipe); | |
1482 | ||
1483 | info("submit_control_msg"); | |
1484 | #ifdef DEBUG | |
6f5794a6 RB |
1485 | pkt_print(NULL, dev, pipe, buffer, transfer_len, |
1486 | setup, "SUB", usb_pipein(pipe)); | |
3e326ece | 1487 | #else |
5b84dd67 | 1488 | mdelay(1); |
3e326ece MK |
1489 | #endif |
1490 | if (!maxsize) { | |
1491 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1492 | pipe); | |
1493 | return -1; | |
1494 | } | |
1495 | if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { | |
1496 | gohci.rh.dev = dev; | |
1497 | /* root hub - redirect */ | |
1498 | return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, | |
1499 | setup); | |
1500 | } | |
1501 | ||
1502 | return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); | |
1503 | } | |
1504 | ||
1505 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1506 | int transfer_len, int interval) | |
1507 | { | |
1508 | info("submit_int_msg"); | |
4dae14ce ZW |
1509 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, |
1510 | interval); | |
3e326ece MK |
1511 | } |
1512 | ||
1513 | /*-------------------------------------------------------------------------* | |
1514 | * HC functions | |
1515 | *-------------------------------------------------------------------------*/ | |
1516 | ||
1517 | /* reset the HC and BUS */ | |
1518 | ||
6f5794a6 | 1519 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1520 | { |
e90fb6af YT |
1521 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1522 | pci_dev_t pdev; | |
1523 | #endif | |
3e326ece MK |
1524 | int timeout = 30; |
1525 | int smm_timeout = 50; /* 0,5 sec */ | |
1526 | ||
1527 | dbg("%s\n", __FUNCTION__); | |
1528 | ||
e90fb6af YT |
1529 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1530 | /* | |
1531 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1532 | * resetting via EHCI registers only. | |
1533 | */ | |
1534 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1535 | if (pdev != -1) { | |
1536 | u32 base; | |
1537 | int timeout = 1000; | |
1538 | ||
1539 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
a5496a18 BB |
1540 | base += EHCI_USBCMD_OFF; |
1541 | ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); | |
e90fb6af | 1542 | |
a5496a18 | 1543 | while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { |
e90fb6af YT |
1544 | if (timeout-- <= 0) { |
1545 | printf("USB RootHub reset timed out!"); | |
1546 | break; | |
1547 | } | |
1548 | udelay(1); | |
1549 | } | |
1550 | } else | |
1551 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1552 | #endif | |
a5496a18 BB |
1553 | if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1554 | /* SMM owns the HC, request ownership */ | |
1555 | ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); | |
3e326ece | 1556 | info("USB HC TakeOver from SMM"); |
a5496a18 | 1557 | while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1558 | mdelay(10); |
3e326ece MK |
1559 | if (--smm_timeout == 0) { |
1560 | err("USB HC TakeOver failed!"); | |
1561 | return -1; | |
1562 | } | |
1563 | } | |
1564 | } | |
1565 | ||
1566 | /* Disable HC interrupts */ | |
a5496a18 | 1567 | ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1568 | |
1569 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1570 | ohci->slot_name, | |
a5496a18 | 1571 | ohci_readl(&ohci->regs->control)); |
3e326ece MK |
1572 | |
1573 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1574 | ohci->hc_control = 0; |
a5496a18 | 1575 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1576 | |
1577 | /* HC Reset requires max 10 us delay */ | |
a5496a18 BB |
1578 | ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1579 | while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1580 | if (--timeout == 0) { |
1581 | err("USB HC reset timed out!"); | |
1582 | return -1; | |
1583 | } | |
6f5794a6 | 1584 | udelay(1); |
3e326ece MK |
1585 | } |
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | /*-------------------------------------------------------------------------*/ | |
1590 | ||
1591 | /* Start an OHCI controller, set the BUS operational | |
1592 | * enable interrupts | |
1593 | * connect the virtual root hub */ | |
1594 | ||
6f5794a6 | 1595 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1596 | { |
1597 | __u32 mask; | |
1598 | unsigned int fminterval; | |
1599 | ||
1600 | ohci->disabled = 1; | |
1601 | ||
1602 | /* Tell the controller where the control and bulk lists are | |
1603 | * The lists are empty now. */ | |
1604 | ||
a5496a18 BB |
1605 | ohci_writel(0, &ohci->regs->ed_controlhead); |
1606 | ohci_writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1607 | |
a5496a18 BB |
1608 | ohci_writel((__u32)ohci->hcca, |
1609 | &ohci->regs->hcca); /* reset clears this */ | |
3e326ece MK |
1610 | |
1611 | fminterval = 0x2edf; | |
a5496a18 | 1612 | ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1613 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
a5496a18 BB |
1614 | ohci_writel(fminterval, &ohci->regs->fminterval); |
1615 | ohci_writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1616 | |
1617 | /* start controller operations */ | |
1618 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1619 | ohci->disabled = 0; | |
a5496a18 | 1620 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1621 | |
1622 | /* disable all interrupts */ | |
1623 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1624 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1625 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
a5496a18 | 1626 | ohci_writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1627 | /* clear all interrupts */ |
1628 | mask &= ~OHCI_INTR_MIE; | |
a5496a18 | 1629 | ohci_writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1630 | /* Choose the interrupts we care about now - but w/o MIE */ |
1631 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
a5496a18 | 1632 | ohci_writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1633 | |
1634 | #ifdef OHCI_USE_NPS | |
1635 | /* required for AMD-756 and some Mac platforms */ | |
a5496a18 | 1636 | ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1637 | &ohci->regs->roothub.a); |
a5496a18 | 1638 | ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1639 | #endif /* OHCI_USE_NPS */ |
1640 | ||
3e326ece | 1641 | /* POTPGT delay is bits 24-31, in 2 ms units. */ |
6f5794a6 | 1642 | mdelay((roothub_a(ohci) >> 23) & 0x1fe); |
3e326ece MK |
1643 | |
1644 | /* connect the virtual root hub */ | |
1645 | ohci->rh.devnum = 0; | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
1650 | /*-------------------------------------------------------------------------*/ | |
1651 | ||
1652 | /* an interrupt happens */ | |
1653 | ||
6f5794a6 | 1654 | static int hc_interrupt(void) |
3e326ece MK |
1655 | { |
1656 | ohci_t *ohci = &gohci; | |
1657 | struct ohci_regs *regs = ohci->regs; | |
1658 | int ints; | |
1659 | int stat = -1; | |
1660 | ||
ddf83a2f | 1661 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1662 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1663 | ints = OHCI_INTR_WDH; |
6f5794a6 | 1664 | } else { |
a5496a18 | 1665 | ints = ohci_readl(®s->intrstatus); |
6f5794a6 RB |
1666 | if (ints == ~(u32)0) { |
1667 | ohci->disabled++; | |
1668 | err("%s device removed!", ohci->slot_name); | |
1669 | return -1; | |
1670 | } else { | |
a5496a18 | 1671 | ints &= ohci_readl(®s->intrenable); |
6f5794a6 RB |
1672 | if (ints == 0) { |
1673 | dbg("hc_interrupt: returning..\n"); | |
1674 | return 0xff; | |
1675 | } | |
1676 | } | |
ddf83a2f | 1677 | } |
ae79f606 | 1678 | |
6f5794a6 RB |
1679 | /* dbg("Interrupt: %x frame: %x", ints, |
1680 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1681 | |
6f5794a6 | 1682 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1683 | stat = 0xff; |
3e326ece MK |
1684 | |
1685 | if (ints & OHCI_INTR_UE) { | |
1686 | ohci->disabled++; | |
6f5794a6 | 1687 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1688 | ohci->slot_name); |
1689 | /* e.g. due to PCI Master/Target Abort */ | |
1690 | ||
1691 | #ifdef DEBUG | |
6f5794a6 | 1692 | ohci_dump(ohci, 1); |
3e326ece | 1693 | #else |
5b84dd67 | 1694 | mdelay(1); |
3e326ece MK |
1695 | #endif |
1696 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1697 | /* Make some non-interrupt context restart the controller. */ | |
1698 | /* Count and limit the retries though; either hardware or */ | |
1699 | /* software errors can go forever... */ | |
6f5794a6 | 1700 | hc_reset(ohci); |
3e326ece MK |
1701 | return -1; |
1702 | } | |
1703 | ||
1704 | if (ints & OHCI_INTR_WDH) { | |
5b84dd67 | 1705 | mdelay(1); |
a5496a18 BB |
1706 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
1707 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
6f5794a6 | 1708 | stat = dl_done_list(&gohci); |
a5496a18 BB |
1709 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
1710 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1711 | } |
1712 | ||
1713 | if (ints & OHCI_INTR_SO) { | |
1714 | dbg("USB Schedule overrun\n"); | |
a5496a18 | 1715 | ohci_writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1716 | stat = -1; |
1717 | } | |
1718 | ||
1719 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1720 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1721 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
5b84dd67 | 1722 | mdelay(1); |
a5496a18 | 1723 | ohci_writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1724 | if (ohci->ed_rm_list[frame] != NULL) |
a5496a18 | 1725 | ohci_writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1726 | stat = 0xff; |
1727 | } | |
1728 | ||
a5496a18 | 1729 | ohci_writel(ints, ®s->intrstatus); |
3e326ece MK |
1730 | return stat; |
1731 | } | |
1732 | ||
1733 | /*-------------------------------------------------------------------------*/ | |
1734 | ||
1735 | /*-------------------------------------------------------------------------*/ | |
1736 | ||
1737 | /* De-allocate all resources.. */ | |
1738 | ||
6f5794a6 | 1739 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1740 | { |
6f5794a6 | 1741 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1742 | |
1743 | if (!ohci->disabled) | |
6f5794a6 | 1744 | hc_reset(ohci); |
3e326ece MK |
1745 | } |
1746 | ||
1747 | /*-------------------------------------------------------------------------*/ | |
1748 | ||
1749 | /* | |
1750 | * low level initalisation routine, called from usb.c | |
1751 | */ | |
1752 | static char ohci_inited = 0; | |
1753 | ||
06d513ec | 1754 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
3e326ece | 1755 | { |
4dae14ce ZW |
1756 | #ifdef CONFIG_PCI_OHCI |
1757 | pci_dev_t pdev; | |
1758 | #endif | |
24e37645 | 1759 | |
6d0f6bcf | 1760 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1761 | /* cpu dependant init */ |
6f5794a6 | 1762 | if (usb_cpu_init()) |
3e326ece | 1763 | return -1; |
24e37645 | 1764 | #endif |
3e326ece | 1765 | |
6d0f6bcf | 1766 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1767 | /* board dependant init */ |
16297cfb | 1768 | if (board_usb_init(index, USB_INIT_HOST)) |
24e37645 MK |
1769 | return -1; |
1770 | #endif | |
6f5794a6 | 1771 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
1772 | |
1773 | /* align the storage */ | |
1774 | if ((__u32)&ghcca[0] & 0xff) { | |
1775 | err("HCCA not aligned!!"); | |
1776 | return -1; | |
1777 | } | |
1778 | phcca = &ghcca[0]; | |
1779 | info("aligned ghcca %p", phcca); | |
1780 | memset(&ohci_dev, 0, sizeof(struct ohci_device)); | |
1781 | if ((__u32)&ohci_dev.ed[0] & 0x7) { | |
1782 | err("EDs not aligned!!"); | |
1783 | return -1; | |
1784 | } | |
1785 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); | |
1786 | if ((__u32)gtd & 0x7) { | |
1787 | err("TDs not aligned!!"); | |
1788 | return -1; | |
1789 | } | |
1790 | ptd = gtd; | |
1791 | gohci.hcca = phcca; | |
6f5794a6 | 1792 | memset(phcca, 0, sizeof(struct ohci_hcca)); |
3e326ece MK |
1793 | |
1794 | gohci.disabled = 1; | |
1795 | gohci.sleeping = 0; | |
1796 | gohci.irq = -1; | |
4dae14ce | 1797 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 1798 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
1799 | |
1800 | if (pdev != -1) { | |
1801 | u16 vid, did; | |
1802 | u32 base; | |
1803 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1804 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1805 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1806 | vid, did, (pdev >> 16) & 0xff, | |
1807 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1808 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1809 | printf("OHCI regs address 0x%08x\n", base); | |
1810 | gohci.regs = (struct ohci_regs *)base; | |
1811 | } else | |
1812 | return -1; | |
1813 | #else | |
6d0f6bcf | 1814 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 1815 | #endif |
3e326ece MK |
1816 | |
1817 | gohci.flags = 0; | |
6d0f6bcf | 1818 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1819 | |
1820 | if (hc_reset (&gohci) < 0) { | |
1821 | hc_release_ohci (&gohci); | |
1822 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 1823 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1824 | /* board dependant cleanup */ |
16297cfb | 1825 | board_usb_cleanup(index, USB_INIT_HOST); |
24e37645 MK |
1826 | #endif |
1827 | ||
6d0f6bcf | 1828 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1829 | /* cpu dependant cleanup */ |
ddf83a2f | 1830 | usb_cpu_init_fail(); |
24e37645 | 1831 | #endif |
3e326ece MK |
1832 | return -1; |
1833 | } | |
1834 | ||
6f5794a6 RB |
1835 | if (hc_start(&gohci) < 0) { |
1836 | err("can't start usb-%s", gohci.slot_name); | |
1837 | hc_release_ohci(&gohci); | |
3e326ece | 1838 | /* Initialization failed */ |
6d0f6bcf | 1839 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
1840 | /* board dependant cleanup */ |
1841 | usb_board_stop(); | |
1842 | #endif | |
1843 | ||
6d0f6bcf | 1844 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
1845 | /* cpu dependant cleanup */ |
1846 | usb_cpu_stop(); | |
1847 | #endif | |
3e326ece MK |
1848 | return -1; |
1849 | } | |
1850 | ||
1851 | #ifdef DEBUG | |
6f5794a6 | 1852 | ohci_dump(&gohci, 1); |
3e326ece | 1853 | #else |
5b84dd67 | 1854 | mdelay(1); |
3e326ece MK |
1855 | #endif |
1856 | ohci_inited = 1; | |
1857 | return 0; | |
1858 | } | |
1859 | ||
c7e3b2b5 | 1860 | int usb_lowlevel_stop(int index) |
3e326ece MK |
1861 | { |
1862 | /* this gets called really early - before the controller has */ | |
1863 | /* even been initialized! */ | |
1864 | if (!ohci_inited) | |
1865 | return 0; | |
1866 | /* TODO release any interrupts, etc. */ | |
1867 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 1868 | hc_reset(&gohci); |
3e326ece | 1869 | |
6d0f6bcf | 1870 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 1871 | /* board dependant cleanup */ |
6f5794a6 | 1872 | if (usb_board_stop()) |
3e326ece | 1873 | return -1; |
24e37645 MK |
1874 | #endif |
1875 | ||
6d0f6bcf | 1876 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1877 | /* cpu dependant cleanup */ |
6f5794a6 | 1878 | if (usb_cpu_stop()) |
24e37645 MK |
1879 | return -1; |
1880 | #endif | |
eba1f2fc RB |
1881 | /* This driver is no longer initialised. It needs a new low-level |
1882 | * init (board/cpu) before it can be used again. */ | |
1883 | ohci_inited = 0; | |
3e326ece MK |
1884 | return 0; |
1885 | } |