[people/ms/u-boot.git] / include / configs / CPCI4052.h

/*
 * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#undef  CONFIG_HAS_ETH1

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM

#define CONFIG_SUPPORT_VFAT

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */

#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

#define CONFIG_PRAM		0	/* use pram variable to overwrite */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */
#endif

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
#define CONFIG_SYS_LED_ADDR		0xF0000380

/* Memory Bank 3 (CompactFlash IDE) initialization				*/
#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM/RTC) initialization					*/
/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 5 (optional Quart) initialization				*/
#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 6 (FPGA internal) initialization					*/
#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_MODE		0x00
#define CONFIG_SYS_FPGA_STATUS		0x02
#define CONFIG_SYS_FPGA_TS		0x04
#define CONFIG_SYS_FPGA_TS_LOW		0x06
#define CONFIG_SYS_FPGA_TS_CAP0	0x10
#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
#define CONFIG_SYS_FPGA_TS_CAP1	0x14
#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
#define CONFIG_SYS_FPGA_TS_CAP2	0x18
#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e

/* FPGA Mode Reg */
#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000

/* FPGA Status Reg */
#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000

#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
a20b27a3	2	* (C) Copyright 2001-2004
c609719b WD	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
c609719b WD	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c609719b	21	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c837dcb1	22	#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
6f35c531	23	#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
c609719b	24
2ae18241 WD	25	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	26
3a8f28d0	27	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
c609719b	28
a20b27a3	29	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
c609719b WD	30
c609719b WD	31	#define CONFIG_BAUDRATE 9600
c609719b	32
c609719b	33	#undef CONFIG_BOOTARGS
a20b27a3 SR	34	#undef CONFIG_BOOTCOMMAND
	35
	36	#define CONFIG_PREBOOT /* enable preboot variable */
c609719b WD	37
c609719b WD	38	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	39	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	40
96e21f86	41	#define CONFIG_PPC4xx_EMAC
c609719b	42	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	43	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	44	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
6f35c531 MF	45	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
6f35c531 MF	46
6f35c531	47	#undef CONFIG_HAS_ETH1
c609719b WD	48
	49	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	50
5d2ebe1b JL	51	/*
	52	* BOOTP options
	53	*/
	54	#define CONFIG_BOOTP_SUBNETMASK
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
	57	#define CONFIG_BOOTP_BOOTPATH
	58	#define CONFIG_BOOTP_DNS
	59	#define CONFIG_BOOTP_DNS2
	60	#define CONFIG_BOOTP_SEND_HOSTNAME
	61
49cf7e8e JL	62	/*
	63	* Command line configuration.
	64	*/
49cf7e8e JL	65	#define CONFIG_CMD_PCI
	66	#define CONFIG_CMD_IRQ
	67	#define CONFIG_CMD_IDE
49cf7e8e	68	#define CONFIG_CMD_DATE
49cf7e8e JL	69	#define CONFIG_CMD_BSP
	70	#define CONFIG_CMD_EEPROM
	71
a20b27a3 SR	72	#define CONFIG_SUPPORT_VFAT
a20b27a3 SR	73
c837dcb1	74	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	75
c837dcb1	76	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	77
	78	/*
	79	* Miscellaneous configurable options
	80	*/
c6265f7f	81	#undef CONFIG_SYS_LONGHELP /* undef to save memory */
c609719b	82
49cf7e8e	83	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	84	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	85	#else
6d0f6bcf	86	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	87	#endif
6d0f6bcf JCPV	88	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	89	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	90	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	91
6d0f6bcf	92	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b	93
6d0f6bcf	94	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	97	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	98
550650dd	99	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
550650dd SR	100	#define CONFIG_SYS_NS16550_SERIAL
	101	#define CONFIG_SYS_NS16550_REG_SIZE 1
	102	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	103
6d0f6bcf	104	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	105	#define CONFIG_SYS_BASE_BAUD 691200
c609719b	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	108	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	109
ac53ee83 MF	110	#define CONFIG_CMDLINE_EDITING /* add command line history */
ac53ee83 MF	111
6d0f6bcf	112	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435	113
c609719b WD	114	/*-----------------------------------------------------------------------
	115	* PCI stuff
	116	*-----------------------------------------------------------------------
	117	*/
a20b27a3 SR	118	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	119	#define PCI_HOST_FORCE 1 /* configure as pci host */
	120	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	121
842033e6	122	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
a20b27a3	123	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
a20b27a3 SR	124	/* resource configuration */
	125
	126	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	127
	128	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	129
	130	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	133	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	134	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	135	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	136	#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
	137	#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
	138	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	139	#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
	140	#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
468ebf19	141	#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
c609719b	142
82379b55 MF	143	#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
82379b55 MF	144
c609719b WD	145	/*-----------------------------------------------------------------------
	146	* IDE/ATA stuff
	147	*-----------------------------------------------------------------------
	148	*/
c837dcb1 WD	149	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
c837dcb1 WD	150	#undef CONFIG_IDE_LED /* no led for ide supported */
c609719b WD	151	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
c609719b WD	152
6d0f6bcf JCPV	153	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	154	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
c609719b	155
6d0f6bcf JCPV	156	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
6d0f6bcf JCPV	157	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
c609719b	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	160	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	161	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
c609719b WD	162
	163	/*-----------------------------------------------------------------------
	164	* Start addresses for the final memory configuration
	165	* (Set up by the startup code)
6d0f6bcf	166	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	169	#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
	170	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	171	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	172	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b	173
3ba605d4 MF	174	#define CONFIG_PRAM 0 /* use pram variable to overwrite */
3ba605d4 MF	175
c609719b WD	176	/*
	177	* For booting Linux, the board info and command line data
	178	* have to be in the first 8 MB of memory, since this is
	179	* the maximum mapped by the Linux kernel during initialization.
	180	*/
6d0f6bcf	181	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ac53ee83	182
c609719b WD	183	/*-----------------------------------------------------------------------
	184	* FLASH organization
	185	*/
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	187	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	193	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	194	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	195	/*
	196	* The following defines are added for buggy IOP480 byte interface.
	197	* All other boards should use the standard values (CPCI405 etc.)
	198	*/
6d0f6bcf JCPV	199	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	200	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	201	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	202
6d0f6bcf	203	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b	204
c609719b WD	205	#if 0 /* Use NVRAM for environment variables */
	206	/*-----------------------------------------------------------------------
	207	* NVRAM organization
	208	*/
9314cee6	209	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
0e8d1586 JCPV	210	#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
0e8d1586 JCPV	211	#define CONFIG_ENV_ADDR \
6d0f6bcf	212	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
c609719b WD	213
	214	#else /* Use EEPROM for environment variables */
	215
bb1f8b4f	216	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	217	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	218	#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
8bde7f77	219	/* total size of a CAT24WC16 is 2048 bytes */
c609719b WD	220	#endif
c609719b WD	221
6d0f6bcf JCPV	222	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	223	#define CONFIG_SYS_NVRAM_SIZE (321024) / NVRAM size */
	224	#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
c609719b WD	225
	226	/*-----------------------------------------------------------------------
	227	* I2C EEPROM (CAT24WC16) for environment
	228	*/
880540de DE	229	#define CONFIG_SYS_I2C
	230	#define CONFIG_SYS_I2C_PPC4XX
	231	#define CONFIG_SYS_I2C_PPC4XX_CH0
	232	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	233	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b	234
6d0f6bcf JCPV	235	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	236	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	237	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	238	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	239	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b	240	/* 16 byte page write mode using*/
c837dcb1	241	/* last 4 bits of the address */
6d0f6bcf	242	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	243
c609719b WD	244	/*
	245	* Init Memory Controller:
	246	*
	247	* BR0/1 and OR0/1 (FLASH)
	248	*/
	249
	250	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	251	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	252
	253	/*-----------------------------------------------------------------------
	254	* External Bus Controller (EBC) Setup
	255	*/
	256
c837dcb1	257	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	258	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	259	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	260
c837dcb1	261	/* Memory Bank 1 (Flash Bank 1) initialization */
6d0f6bcf JCPV	262	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	263	#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	264
c837dcb1	265	/* Memory Bank 2 (CAN0, 1) initialization */
6d0f6bcf JCPV	266	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	267	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	268	#define CONFIG_SYS_LED_ADDR 0xF0000380
c609719b	269
c837dcb1	270	/* Memory Bank 3 (CompactFlash IDE) initialization */
6d0f6bcf JCPV	271	#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	272	#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b	273
c837dcb1	274	/* Memory Bank 4 (NVRAM/RTC) initialization */
6d0f6bcf JCPV	275	/#define CONFIG_SYS_EBC_PB4AP 0x01805280 / TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
	276	#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
	277	#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b	278
c837dcb1	279	/* Memory Bank 5 (optional Quart) initialization */
6d0f6bcf JCPV	280	#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
6d0f6bcf JCPV	281	#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b	282
c837dcb1	283	/* Memory Bank 6 (FPGA internal) initialization */
6d0f6bcf JCPV	284	#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	285	#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	286	#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
c609719b WD	287
	288	/*-----------------------------------------------------------------------
	289	* FPGA stuff
	290	*/
	291	/* FPGA internal regs */
6d0f6bcf JCPV	292	#define CONFIG_SYS_FPGA_MODE 0x00
	293	#define CONFIG_SYS_FPGA_STATUS 0x02
	294	#define CONFIG_SYS_FPGA_TS 0x04
	295	#define CONFIG_SYS_FPGA_TS_LOW 0x06
	296	#define CONFIG_SYS_FPGA_TS_CAP0 0x10
	297	#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
	298	#define CONFIG_SYS_FPGA_TS_CAP1 0x14
	299	#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
	300	#define CONFIG_SYS_FPGA_TS_CAP2 0x18
	301	#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
	302	#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
	303	#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
c609719b WD	304
c609719b WD	305	/* FPGA Mode Reg */
6d0f6bcf JCPV	306	#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
	307	#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
	308	#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
	309	#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
	310	#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
	311	#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
c609719b WD	312
c609719b WD	313	/* FPGA Status Reg */
6d0f6bcf JCPV	314	#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
	315	#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
	316	#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
	317	#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
	318	#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
c609719b	319
6d0f6bcf JCPV	320	#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
6d0f6bcf JCPV	321	#define CONFIG_SYS_FPGA_MAX_SIZE 321024 / 32kByte is enough for XC2S15 */
c609719b WD	322
c609719b WD	323	/* FPGA program pin configuration */
6d0f6bcf JCPV	324	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	325	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	326	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	327	#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	328	#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
c609719b WD	329
	330	/*-----------------------------------------------------------------------
	331	* Definitions for initial stack pointer and data area (in data cache)
	332	*/
6d0f6bcf	333	#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
c609719b	334
6d0f6bcf	335	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
553f0982	336	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb	337	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	338	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	339
c609719b	340	#endif /* __CONFIG_H */