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Commit | Line | Data |
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c609719b | 1 | /* |
a20b27a3 | 2 | * (C) Copyright 2001-2004 |
c609719b WD |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c609719b | 21 | #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ |
c837dcb1 | 22 | #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ |
6f35c531 | 23 | #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ |
c609719b | 24 | |
2ae18241 WD |
25 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
26 | ||
3a8f28d0 | 27 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
c609719b | 28 | |
a20b27a3 | 29 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
c609719b | 30 | |
c609719b | 31 | #undef CONFIG_BOOTARGS |
a20b27a3 SR |
32 | #undef CONFIG_BOOTCOMMAND |
33 | ||
34 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
c609719b WD |
35 | |
36 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 37 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 38 | |
96e21f86 | 39 | #define CONFIG_PPC4xx_EMAC |
c609719b | 40 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 41 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 42 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
6f35c531 MF |
43 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
44 | ||
6f35c531 | 45 | #undef CONFIG_HAS_ETH1 |
c609719b WD |
46 | |
47 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
48 | ||
5d2ebe1b JL |
49 | /* |
50 | * BOOTP options | |
51 | */ | |
52 | #define CONFIG_BOOTP_SUBNETMASK | |
53 | #define CONFIG_BOOTP_GATEWAY | |
54 | #define CONFIG_BOOTP_HOSTNAME | |
55 | #define CONFIG_BOOTP_BOOTPATH | |
56 | #define CONFIG_BOOTP_DNS | |
57 | #define CONFIG_BOOTP_DNS2 | |
58 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
59 | ||
49cf7e8e JL |
60 | /* |
61 | * Command line configuration. | |
62 | */ | |
49cf7e8e JL |
63 | #define CONFIG_CMD_PCI |
64 | #define CONFIG_CMD_IRQ | |
65 | #define CONFIG_CMD_IDE | |
49cf7e8e JL |
66 | #define CONFIG_CMD_EEPROM |
67 | ||
a20b27a3 SR |
68 | #define CONFIG_SUPPORT_VFAT |
69 | ||
c837dcb1 | 70 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
c609719b | 71 | |
c837dcb1 | 72 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
c609719b WD |
73 | |
74 | /* | |
75 | * Miscellaneous configurable options | |
76 | */ | |
c6265f7f | 77 | #undef CONFIG_SYS_LONGHELP /* undef to save memory */ |
c609719b | 78 | |
49cf7e8e | 79 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 80 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 81 | #else |
6d0f6bcf | 82 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 83 | #endif |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
85 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
86 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
c609719b | 89 | |
6d0f6bcf | 90 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
c609719b | 91 | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
93 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 94 | |
550650dd | 95 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
96 | #define CONFIG_SYS_NS16550_SERIAL |
97 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
98 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
99 | ||
6d0f6bcf | 100 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 101 | #define CONFIG_SYS_BASE_BAUD 691200 |
c609719b | 102 | |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
104 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 105 | |
ac53ee83 MF |
106 | #define CONFIG_CMDLINE_EDITING /* add command line history */ |
107 | ||
6d0f6bcf | 108 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
53cf9435 | 109 | |
c609719b WD |
110 | /*----------------------------------------------------------------------- |
111 | * PCI stuff | |
112 | *----------------------------------------------------------------------- | |
113 | */ | |
a20b27a3 SR |
114 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
115 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
116 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
117 | ||
842033e6 | 118 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
a20b27a3 | 119 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
a20b27a3 SR |
120 | /* resource configuration */ |
121 | ||
122 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
123 | ||
124 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
125 | ||
126 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ | |
127 | ||
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
129 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
130 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ | |
131 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
132 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ | |
133 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ | |
134 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
135 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
136 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
468ebf19 | 137 | #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ |
c609719b | 138 | |
82379b55 MF |
139 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
140 | ||
c609719b WD |
141 | /*----------------------------------------------------------------------- |
142 | * IDE/ATA stuff | |
143 | *----------------------------------------------------------------------- | |
144 | */ | |
c837dcb1 WD |
145 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
146 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
c609719b WD |
147 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
148 | ||
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
150 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
c609719b | 151 | |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
153 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
c609719b | 154 | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
156 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
157 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
c609719b WD |
158 | |
159 | /*----------------------------------------------------------------------- | |
160 | * Start addresses for the final memory configuration | |
161 | * (Set up by the startup code) | |
6d0f6bcf | 162 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 163 | */ |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
165 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
166 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
167 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
168 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
c609719b | 169 | |
3ba605d4 MF |
170 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ |
171 | ||
c609719b WD |
172 | /* |
173 | * For booting Linux, the board info and command line data | |
174 | * have to be in the first 8 MB of memory, since this is | |
175 | * the maximum mapped by the Linux kernel during initialization. | |
176 | */ | |
6d0f6bcf | 177 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ac53ee83 | 178 | |
c609719b WD |
179 | /*----------------------------------------------------------------------- |
180 | * FLASH organization | |
181 | */ | |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
183 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
c609719b | 184 | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
186 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
189 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
190 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
c609719b WD |
191 | /* |
192 | * The following defines are added for buggy IOP480 byte interface. | |
193 | * All other boards should use the standard values (CPCI405 etc.) | |
194 | */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
196 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
197 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
c609719b | 198 | |
6d0f6bcf | 199 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
c609719b | 200 | |
c609719b WD |
201 | #if 0 /* Use NVRAM for environment variables */ |
202 | /*----------------------------------------------------------------------- | |
203 | * NVRAM organization | |
204 | */ | |
9314cee6 | 205 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
0e8d1586 JCPV |
206 | #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ |
207 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 208 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ |
c609719b WD |
209 | |
210 | #else /* Use EEPROM for environment variables */ | |
211 | ||
bb1f8b4f | 212 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
213 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
214 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ | |
8bde7f77 | 215 | /* total size of a CAT24WC16 is 2048 bytes */ |
c609719b WD |
216 | #endif |
217 | ||
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
219 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
220 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ | |
c609719b WD |
221 | |
222 | /*----------------------------------------------------------------------- | |
223 | * I2C EEPROM (CAT24WC16) for environment | |
224 | */ | |
880540de DE |
225 | #define CONFIG_SYS_I2C |
226 | #define CONFIG_SYS_I2C_PPC4XX | |
227 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
228 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
229 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
c609719b | 230 | |
6d0f6bcf JCPV |
231 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
232 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 233 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
235 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
c609719b | 236 | /* 16 byte page write mode using*/ |
c837dcb1 | 237 | /* last 4 bits of the address */ |
6d0f6bcf | 238 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 239 | |
c609719b WD |
240 | /* |
241 | * Init Memory Controller: | |
242 | * | |
243 | * BR0/1 and OR0/1 (FLASH) | |
244 | */ | |
245 | ||
246 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
247 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
248 | ||
249 | /*----------------------------------------------------------------------- | |
250 | * External Bus Controller (EBC) Setup | |
251 | */ | |
252 | ||
c837dcb1 | 253 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
254 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
255 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 256 | |
c837dcb1 | 257 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
259 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 260 | |
c837dcb1 | 261 | /* Memory Bank 2 (CAN0, 1) initialization */ |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
263 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
264 | #define CONFIG_SYS_LED_ADDR 0xF0000380 | |
c609719b | 265 | |
c837dcb1 | 266 | /* Memory Bank 3 (CompactFlash IDE) initialization */ |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
268 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
c609719b | 269 | |
c837dcb1 | 270 | /* Memory Bank 4 (NVRAM/RTC) initialization */ |
6d0f6bcf JCPV |
271 | /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ |
272 | #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ | |
273 | #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 274 | |
c837dcb1 | 275 | /* Memory Bank 5 (optional Quart) initialization */ |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
277 | #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 278 | |
c837dcb1 | 279 | /* Memory Bank 6 (FPGA internal) initialization */ |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
281 | #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
282 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 | |
c609719b WD |
283 | |
284 | /*----------------------------------------------------------------------- | |
285 | * FPGA stuff | |
286 | */ | |
287 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_FPGA_MODE 0x00 |
289 | #define CONFIG_SYS_FPGA_STATUS 0x02 | |
290 | #define CONFIG_SYS_FPGA_TS 0x04 | |
291 | #define CONFIG_SYS_FPGA_TS_LOW 0x06 | |
292 | #define CONFIG_SYS_FPGA_TS_CAP0 0x10 | |
293 | #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 | |
294 | #define CONFIG_SYS_FPGA_TS_CAP1 0x14 | |
295 | #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 | |
296 | #define CONFIG_SYS_FPGA_TS_CAP2 0x18 | |
297 | #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a | |
298 | #define CONFIG_SYS_FPGA_TS_CAP3 0x1c | |
299 | #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e | |
c609719b WD |
300 | |
301 | /* FPGA Mode Reg */ | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 |
303 | #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 | |
304 | #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ | |
305 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 | |
306 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 | |
307 | #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 | |
c609719b WD |
308 | |
309 | /* FPGA Status Reg */ | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 |
311 | #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 | |
312 | #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 | |
313 | #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 | |
314 | #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 | |
c609719b | 315 | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
317 | #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ | |
c609719b WD |
318 | |
319 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
321 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
322 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
323 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
324 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
c609719b WD |
325 | |
326 | /*----------------------------------------------------------------------- | |
327 | * Definitions for initial stack pointer and data area (in data cache) | |
328 | */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
c609719b | 330 | |
6d0f6bcf | 331 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
553f0982 | 332 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 333 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 334 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 335 | |
c609719b | 336 | #endif /* __CONFIG_H */ |