[people/ms/u-boot.git] / include / configs / M5282EVB.h

/*
 * Configuation settings for the Motorola MC5282EVB board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _CONFIG_M5282EVB_H
#define _CONFIG_M5282EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define	CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5282		/* define processor type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_IS_IN_FLASH	1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII

#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_BOOTDELAY	5
#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5282EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_PROMPT		"-> "
#define	CONFIG_SYS_LONGHELP		/* undef to save memory         */

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		0x20000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define CONFIG_SYS_HZ			1000
#define	CONFIG_SYS_CLK			64000000

/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define	CONFIG_SYS_MBAR		0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE	0x21

/* If M5282 port is fully implemented the monitor base will be behind
 * the vector table. */
#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
					 CF_CACR_CEIB | CF_CACR_DBWE | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
#define CONFIG_SYS_PADDR		0x0000000
#define CONFIG_SYS_PADAT		0x0000000

#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
#define CONFIG_SYS_PBDDR		0x0000000
#define CONFIG_SYS_PBDAT		0x0000000

#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PEHLPAR		0xC0
#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
#define CONFIG_SYS_DDRUA		0x05
#define CONFIG_SYS_PJPAR		0xFF

#endif				/* _CONFIG_M5282EVB_H */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Configuation settings for the Motorola MC5282EVB board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
bf9e3b38 WD	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
4e5ca3eb WD	13	#ifndef _CONFIG_M5282EVB_H
	14	#define _CONFIG_M5282EVB_H
	15
bf9e3b38 WD	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
f28e1bd9 TL	20	#define CONFIG_MCF52x2 /* define processor family */
f28e1bd9 TL	21	#define CONFIG_M5282 /* define processor type */
bf9e3b38	22
f28e1bd9	23	#define CONFIG_MCFTMR
bf9e3b38	24
f28e1bd9	25	#define CONFIG_MCFUART
6d0f6bcf	26	#define CONFIG_SYS_UART_PORT (0)
79e0799c	27	#define CONFIG_BAUDRATE 115200
4e5ca3eb	28
f28e1bd9	29	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
bf9e3b38 WD	30
	31	/* Configuration for environment
	32	* Environment is embedded in u-boot in the second sector of the flash
	33	*/
0e8d1586 JCPV	34	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	35	#define CONFIG_ENV_SIZE 0x2000
5a1aceb0	36	#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38	37
659e2f67 JL	38	/*
	39	* BOOTP options
	40	*/
	41	#define CONFIG_BOOTP_BOOTFILESIZE
	42	#define CONFIG_BOOTP_BOOTPATH
	43	#define CONFIG_BOOTP_GATEWAY
	44	#define CONFIG_BOOTP_HOSTNAME
	45
8353e139 JL	46	/*
	47	* Command line configuration.
	48	*/
	49	#include <config_cmd_default.h>
dd9f054e	50	#define CONFIG_CMD_CACHE
f28e1bd9 TL	51	#define CONFIG_CMD_NET
	52	#define CONFIG_CMD_PING
	53	#define CONFIG_CMD_MII
8353e139 JL	54
	55	#undef CONFIG_CMD_LOADS
	56	#undef CONFIG_CMD_LOADB
	57
f28e1bd9 TL	58	#define CONFIG_MCFFEC
f28e1bd9 TL	59	#ifdef CONFIG_MCFFEC
f28e1bd9	60	# define CONFIG_MII 1
0f3ba7e9	61	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	62	# define CONFIG_SYS_DISCOVER_PHY
	63	# define CONFIG_SYS_RX_ETH_BUFFER 8
	64	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	65
6d0f6bcf JCPV	66	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	67	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	68	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	69	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	70	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	71	# define FECDUPLEX FULL
	72	# define FECSPEED _100BASET
	73	# else
6d0f6bcf JCPV	74	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	75	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	76	# endif
6d0f6bcf	77	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9	78	#endif
bf9e3b38	79
bf9e3b38	80	#define CONFIG_BOOTDELAY 5
f28e1bd9 TL	81	#ifdef CONFIG_MCFFEC
	82	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	83	# define CONFIG_IPADDR 192.162.1.2
	84	# define CONFIG_NETMASK 255.255.255.0
	85	# define CONFIG_SERVERIP 192.162.1.1
	86	# define CONFIG_GATEWAYIP 192.162.1.1
	87	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	88	#endif /* CONFIG_MCFFEC */
	89
4cb4e654	90	#define CONFIG_HOSTNAME M5282EVB
f28e1bd9 TL	91	#define CONFIG_EXTRA_ENV_SETTINGS \
	92	"netdev=eth0\0" \
	93	"loadaddr=10000\0" \
	94	"u-boot=u-boot.bin\0" \
	95	"load=tftp ${loadaddr) ${u-boot}\0" \
	96	"upd=run load; run prog\0" \
	97	"prog=prot off ffe00000 ffe3ffff;" \
	98	"era ffe00000 ffe3ffff;" \
	99	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	100	"save\0" \
	101	""
bf9e3b38	102
6d0f6bcf JCPV	103	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	104	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38	105
8353e139	106	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	107	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38	108	#else
6d0f6bcf	109	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38	110	#endif
6d0f6bcf JCPV	111	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	112	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	113	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
bf9e3b38	114
6d0f6bcf	115	#define CONFIG_SYS_LOAD_ADDR 0x20000
bf9e3b38	116
6d0f6bcf JCPV	117	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	118	#define CONFIG_SYS_MEMTEST_END 0x380000
bf9e3b38	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_HZ 1000
6d0f6bcf JCPV	121	#define CONFIG_SYS_CLK 64000000
bf9e3b38	122
f28e1bd9 TL	123	/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
f28e1bd9 TL	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
6d0f6bcf JCPV	126	#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
bf9e3b38 WD	127
	128	/*
	129	* Low Level Configuration Settings
	130	* (address mappings, register initial values, etc.)
	131	* You should know what you are doing if you make changes here.
	132	*/
6d0f6bcf	133	#define CONFIG_SYS_MBAR 0x40000000
bf9e3b38	134
bf9e3b38 WD	135	/*-----------------------------------------------------------------------
	136	* Definitions for initial stack pointer and data area (in DPRAM)
	137	*/
6d0f6bcf	138	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	139	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	140	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	141	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
bf9e3b38 WD	142
	143	/*-----------------------------------------------------------------------
	144	* Start addresses for the final memory configuration
	145	* (Set up by the startup code)
6d0f6bcf	146	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38	147	*/
6d0f6bcf JCPV	148	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	149	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	150	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	151	#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
6d0f6bcf JCPV	152	#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
bf9e3b38 WD	153
	154	/* If M5282 port is fully implemented the monitor base will be behind
	155	* the vector table. */
14d0a02a	156	#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
6d0f6bcf	157	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
f28e1bd9	158	#else
14d0a02a	159	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
f28e1bd9	160	#endif
bf9e3b38	161
6d0f6bcf JCPV	162	#define CONFIG_SYS_MONITOR_LEN 0x20000
	163	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	164	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
bf9e3b38	165
bf9e3b38 WD	166	/*
	167	* For booting Linux, the board info and command line data
	168	* have to be in the first 8 MB of memory, since this is
	169	* the maximum mapped by the Linux kernel during initialization ??
	170	*/
6d0f6bcf	171	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38 WD	172
	173	/*-----------------------------------------------------------------------
	174	* FLASH organization
	175	*/
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	177	#ifdef CONFIG_SYS_FLASH_CFI
f28e1bd9	178
00b1883a	179	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	180	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	181	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	182	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	183	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	184	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	185	# define CONFIG_SYS_FLASH_CHECKSUM
	186	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f28e1bd9	187	#endif
bf9e3b38 WD	188
	189	/*-----------------------------------------------------------------------
	190	* Cache Configuration
	191	*/
6d0f6bcf	192	#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38	193
dd9f054e	194	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	195	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	196	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	197	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	198	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
	199	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	200	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	201	CF_ACR_EN \| CF_ACR_SM_ALL)
	202	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_DISD \| \
	203	CF_CACR_CEIB \| CF_CACR_DBWE \| \
	204	CF_CACR_EUSP)
	205
bf9e3b38 WD	206	/*-----------------------------------------------------------------------
	207	* Memory bank definitions
	208	*/
012522fe TL	209	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	210	#define CONFIG_SYS_CS0_CTRL 0x00001980
	211	#define CONFIG_SYS_CS0_MASK 0x001F0001
	212
bf9e3b38 WD	213	/*-----------------------------------------------------------------------
	214	* Port configuration
	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
	217	#define CONFIG_SYS_PADDR 0x0000000
	218	#define CONFIG_SYS_PADAT 0x0000000
	219
	220	#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
	221	#define CONFIG_SYS_PBDDR 0x0000000
	222	#define CONFIG_SYS_PBDAT 0x0000000
	223
	224	#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
	225	#define CONFIG_SYS_PCDDR 0x0000000
	226	#define CONFIG_SYS_PCDAT 0x0000000
	227
	228	#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
	229	#define CONFIG_SYS_PCDDR 0x0000000
	230	#define CONFIG_SYS_PCDAT 0x0000000
	231
	232	#define CONFIG_SYS_PEHLPAR 0xC0
	233	#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
	234	#define CONFIG_SYS_DDRUA 0x05
	235	#define CONFIG_SYS_PJPAR 0xFF
4e5ca3eb	236
f28e1bd9	237	#endif /* _CONFIG_M5282EVB_H */