[people/ms/u-boot.git] / include / configs / M5282EVB.h

/*
 * Configuation settings for the Motorola MC5282EVB board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _CONFIG_M5282EVB_H
#define _CONFIG_M5282EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SIZE		0x2000

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5282EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define	CONFIG_SYS_LONGHELP		/* undef to save memory         */

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		0x20000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define	CONFIG_SYS_CLK			64000000

/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define	CONFIG_SYS_MBAR		0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE	0x21

/* If M5282 port is fully implemented the monitor base will be behind
 * the vector table. */
#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
					 CF_CACR_CEIB | CF_CACR_DBWE | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
#define CONFIG_SYS_PADDR		0x0000000
#define CONFIG_SYS_PADAT		0x0000000

#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
#define CONFIG_SYS_PBDDR		0x0000000
#define CONFIG_SYS_PBDAT		0x0000000

#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PEHLPAR		0xC0
#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
#define CONFIG_SYS_DDRUA		0x05
#define CONFIG_SYS_PJPAR		0xFF

#endif				/* _CONFIG_M5282EVB_H */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Configuation settings for the Motorola MC5282EVB board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
bf9e3b38 WD	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
4e5ca3eb WD	13	#ifndef _CONFIG_M5282EVB_H
	14	#define _CONFIG_M5282EVB_H
	15
bf9e3b38 WD	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
f28e1bd9	20	#define CONFIG_MCFTMR
bf9e3b38	21
f28e1bd9	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
4e5ca3eb	24
f28e1bd9	25	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
bf9e3b38 WD	26
	27	/* Configuration for environment
	28	* Environment is embedded in u-boot in the second sector of the flash
	29	*/
0e8d1586 JCPV	30	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	31	#define CONFIG_ENV_SIZE 0x2000
bf9e3b38	32
5296cb1d	33	#define LDS_BOARD_TEXT \
	34	. = DEFINED(env_offset) ? env_offset : .; \
	35	common/env_embedded.o (.text*);
	36
659e2f67 JL	37	/*
	38	* BOOTP options
	39	*/
	40	#define CONFIG_BOOTP_BOOTFILESIZE
	41	#define CONFIG_BOOTP_BOOTPATH
	42	#define CONFIG_BOOTP_GATEWAY
	43	#define CONFIG_BOOTP_HOSTNAME
	44
8353e139 JL	45	/*
	46	* Command line configuration.
	47	*/
8353e139	48
f28e1bd9 TL	49	#define CONFIG_MCFFEC
f28e1bd9 TL	50	#ifdef CONFIG_MCFFEC
f28e1bd9	51	# define CONFIG_MII 1
0f3ba7e9	52	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	53	# define CONFIG_SYS_DISCOVER_PHY
	54	# define CONFIG_SYS_RX_ETH_BUFFER 8
	55	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	56
6d0f6bcf JCPV	57	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	58	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	59	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	60	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	61	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	62	# define FECDUPLEX FULL
	63	# define FECSPEED _100BASET
	64	# else
6d0f6bcf JCPV	65	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	66	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	67	# endif
6d0f6bcf	68	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9	69	#endif
bf9e3b38	70
f28e1bd9	71	#ifdef CONFIG_MCFFEC
f28e1bd9 TL	72	# define CONFIG_IPADDR 192.162.1.2
	73	# define CONFIG_NETMASK 255.255.255.0
	74	# define CONFIG_SERVERIP 192.162.1.1
	75	# define CONFIG_GATEWAYIP 192.162.1.1
f28e1bd9 TL	76	#endif /* CONFIG_MCFFEC */
f28e1bd9 TL	77
4cb4e654	78	#define CONFIG_HOSTNAME M5282EVB
f28e1bd9 TL	79	#define CONFIG_EXTRA_ENV_SETTINGS \
	80	"netdev=eth0\0" \
	81	"loadaddr=10000\0" \
	82	"u-boot=u-boot.bin\0" \
	83	"load=tftp ${loadaddr) ${u-boot}\0" \
	84	"upd=run load; run prog\0" \
	85	"prog=prot off ffe00000 ffe3ffff;" \
	86	"era ffe00000 ffe3ffff;" \
	87	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	88	"save\0" \
	89	""
bf9e3b38	90
6d0f6bcf	91	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38	92
8353e139	93	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	94	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38	95	#else
6d0f6bcf	96	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38	97	#endif
6d0f6bcf JCPV	98	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	99	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	100	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
bf9e3b38	101
6d0f6bcf	102	#define CONFIG_SYS_LOAD_ADDR 0x20000
bf9e3b38	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	105	#define CONFIG_SYS_MEMTEST_END 0x380000
bf9e3b38	106
6d0f6bcf	107	#define CONFIG_SYS_CLK 64000000
bf9e3b38	108
f28e1bd9 TL	109	/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
f28e1bd9 TL	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
6d0f6bcf JCPV	112	#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
bf9e3b38 WD	113
	114	/*
	115	* Low Level Configuration Settings
	116	* (address mappings, register initial values, etc.)
	117	* You should know what you are doing if you make changes here.
	118	*/
6d0f6bcf	119	#define CONFIG_SYS_MBAR 0x40000000
bf9e3b38	120
bf9e3b38 WD	121	/*-----------------------------------------------------------------------
	122	* Definitions for initial stack pointer and data area (in DPRAM)
	123	*/
6d0f6bcf	124	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	125	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	126	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	127	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
bf9e3b38 WD	128
	129	/*-----------------------------------------------------------------------
	130	* Start addresses for the final memory configuration
	131	* (Set up by the startup code)
6d0f6bcf	132	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38	133	*/
6d0f6bcf JCPV	134	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	135	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	136	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	137	#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
6d0f6bcf JCPV	138	#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
bf9e3b38 WD	139
	140	/* If M5282 port is fully implemented the monitor base will be behind
	141	* the vector table. */
14d0a02a	142	#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
6d0f6bcf	143	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
f28e1bd9	144	#else
14d0a02a	145	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
f28e1bd9	146	#endif
bf9e3b38	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_MONITOR_LEN 0x20000
	149	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	150	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
bf9e3b38	151
bf9e3b38 WD	152	/*
	153	* For booting Linux, the board info and command line data
	154	* have to be in the first 8 MB of memory, since this is
	155	* the maximum mapped by the Linux kernel during initialization ??
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38 WD	158
	159	/*-----------------------------------------------------------------------
	160	* FLASH organization
	161	*/
6d0f6bcf JCPV	162	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	163	#ifdef CONFIG_SYS_FLASH_CFI
f28e1bd9	164
00b1883a	165	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	166	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	167	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	168	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	169	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	170	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	171	# define CONFIG_SYS_FLASH_CHECKSUM
	172	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f28e1bd9	173	#endif
bf9e3b38 WD	174
	175	/*-----------------------------------------------------------------------
	176	* Cache Configuration
	177	*/
6d0f6bcf	178	#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38	179
dd9f054e	180	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	181	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	182	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	183	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	184	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
	185	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	186	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	187	CF_ACR_EN \| CF_ACR_SM_ALL)
	188	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_DISD \| \
	189	CF_CACR_CEIB \| CF_CACR_DBWE \| \
	190	CF_CACR_EUSP)
	191
bf9e3b38 WD	192	/*-----------------------------------------------------------------------
	193	* Memory bank definitions
	194	*/
012522fe TL	195	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	196	#define CONFIG_SYS_CS0_CTRL 0x00001980
	197	#define CONFIG_SYS_CS0_MASK 0x001F0001
	198
bf9e3b38 WD	199	/*-----------------------------------------------------------------------
	200	* Port configuration
	201	*/
6d0f6bcf JCPV	202	#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
	203	#define CONFIG_SYS_PADDR 0x0000000
	204	#define CONFIG_SYS_PADAT 0x0000000
	205
	206	#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
	207	#define CONFIG_SYS_PBDDR 0x0000000
	208	#define CONFIG_SYS_PBDAT 0x0000000
	209
	210	#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
	211	#define CONFIG_SYS_PCDDR 0x0000000
	212	#define CONFIG_SYS_PCDAT 0x0000000
	213
	214	#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
	215	#define CONFIG_SYS_PCDDR 0x0000000
	216	#define CONFIG_SYS_PCDAT 0x0000000
	217
	218	#define CONFIG_SYS_PEHLPAR 0xC0
	219	#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
	220	#define CONFIG_SYS_DDRUA 0x05
	221	#define CONFIG_SYS_PJPAR 0xFF
4e5ca3eb	222
f28e1bd9	223	#endif /* _CONFIG_M5282EVB_H */