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1/*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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20
21#define CONFIG_SYS_TEXT_BASE 0xFFF80000
22
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23/***********************************************************
24 * Note that it may also be a MIP405T board which is a subset of the
25 * MIP405
26 ***********************************************************/
27/***********************************************************
28 * WARNING:
29 * CONFIG_BOOT_PCI is only used for first boot-up and should
30 * NOT be enabled for production bootloader
31 ***********************************************************/
8bde7f77 32/*#define CONFIG_BOOT_PCI 1*/
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33/***********************************************************
34 * Clock
35 ***********************************************************/
36#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
37
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38/*
39 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
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46/*
47 * Command line configuration.
48 */
8353e139 49#define CONFIG_CMD_DATE
8353e139 50#define CONFIG_CMD_EEPROM
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51#define CONFIG_CMD_IDE
52#define CONFIG_CMD_IRQ
53#define CONFIG_CMD_JFFS2
8353e139 54#define CONFIG_CMD_PCI
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55#define CONFIG_CMD_REGINFO
56#define CONFIG_CMD_SAVES
57#define CONFIG_CMD_BSP
f3e0de60 58
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59/**************************************************************
60 * I2C Stuff:
61 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
62 * 0x53.
63 * The Atmel EEPROM uses 16Bit addressing.
64 ***************************************************************/
65
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66#define CONFIG_SYS_I2C
67#define CONFIG_SYS_I2C_PPC4XX
68#define CONFIG_SYS_I2C_PPC4XX_CH0
69#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
70#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
7d393aed 71
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72#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
73#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
7d393aed 74/* mask of address bits that overflow into the "EEPROM chip address" */
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75#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
76#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
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77 /* 64 byte page write mode using*/
78 /* last 6 bits of the address */
6d0f6bcf 79#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
7d393aed 80
bb1f8b4f 81#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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82#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
83#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
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84
85/***************************************************************
86 * Definitions for Serial Presence Detect EEPROM address
87 * (to get SDRAM settings)
88 ***************************************************************/
f3e0de60 89/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
53677ef1 90#define SDRAM_EEPROM_READ_ADDRESS 0xA1
f3e0de60 91*/
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92/**************************************************************
93 * Environment definitions
94 **************************************************************/
95#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
7d393aed 96/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2afbe4ed 97/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
7d393aed 98
3e38691e 99#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
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100#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
101
102#define CONFIG_IPADDR 10.0.0.100
103#define CONFIG_SERVERIP 10.0.0.1
104#define CONFIG_PREBOOT
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105/***************************************************************
106 * defines if an overwrite_console function exists
107 *************************************************************/
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108/***************************************************************
109 * defines if the overwrite_console should be stored in the
110 * environment
111 **************************************************************/
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112
113/**************************************************************
114 * loads config
115 *************************************************************/
116#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 117#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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118
119#define CONFIG_MISC_INIT_R
120/***********************************************************
121 * Miscellaneous configurable options
122 **********************************************************/
6d0f6bcf 123#define CONFIG_SYS_LONGHELP /* undef to save memory */
8353e139 124#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 125#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7d393aed 126#else
6d0f6bcf 127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7d393aed 128#endif
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129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7d393aed 132
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133#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
7d393aed 135
550650dd 136#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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137#define CONFIG_SYS_NS16550_SERIAL
138#define CONFIG_SYS_NS16550_REG_SIZE 1
139#define CONFIG_SYS_NS16550_CLK get_serial_clock()
140
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141#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
142#define CONFIG_SYS_BASE_BAUD 916667
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143
144/* The following table includes the supported baudrates */
6d0f6bcf 145#define CONFIG_SYS_BAUDRATE_TABLE \
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146 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
147 57600, 115200, 230400, 460800, 921600 }
148
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149#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
150#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
7d393aed 151
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152/*-----------------------------------------------------------------------
153 * PCI stuff
154 *-----------------------------------------------------------------------
155 */
156#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
157#define PCI_HOST_FORCE 1 /* configure as pci host */
158#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
159
160#define CONFIG_PCI /* include pci support */
842033e6 161#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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162#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
163#define CONFIG_PCI_PNP /* pci plug-and-play */
164 /* resource configuration */
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165#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
166#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
167#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
168#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
169#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
170#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
171#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
172#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
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173
174/*-----------------------------------------------------------------------
175 * Start addresses for the final memory configuration
176 * (Set up by the startup code)
6d0f6bcf 177 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
7d393aed 178 */
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179#define CONFIG_SYS_SDRAM_BASE 0x00000000
180#define CONFIG_SYS_FLASH_BASE 0xFFF80000
181#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
182#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
183#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
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184
185/*
186 * For booting Linux, the board info and command line data
187 * have to be in the first 8 MB of memory, since this is
188 * the maximum mapped by the Linux kernel during initialization.
189 */
6d0f6bcf 190#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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191/*-----------------------------------------------------------------------
192 * FLASH organization
193 */
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194#define CONFIG_SYS_UPDATE_FLASH_SIZE
195#define CONFIG_SYS_FLASH_PROTECTION
196#define CONFIG_SYS_FLASH_EMPTY_INFO
7d393aed 197
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198#define CONFIG_SYS_FLASH_CFI
199#define CONFIG_FLASH_CFI_DRIVER
200
201#define CONFIG_FLASH_SHOW_PROGRESS 45
202
203#define CONFIG_SYS_MAX_FLASH_BANKS 1
204#define CONFIG_SYS_MAX_FLASH_SECT 256
7d393aed 205
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206/*
207 * JFFS2 partitions
208 *
209 */
210/* No command line, one static partition, whole device */
68d7d651 211#undef CONFIG_CMD_MTDPARTS
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212#define CONFIG_JFFS2_DEV "nor0"
213#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
214#define CONFIG_JFFS2_PART_OFFSET 0x00000000
215
216/* mtdparts command line support */
217/* Note: fake mtd_id used, no linux mtd map file */
218/*
68d7d651 219#define CONFIG_CMD_MTDPARTS
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220#define MTDIDS_DEFAULT "nor0=mip405-0"
221#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
222*/
7d393aed 223
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224/*-----------------------------------------------------------------------
225 * Logbuffer Configuration
226 */
53677ef1 227#undef CONFIG_LOGBUFFER /* supported but not enabled */
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228/*-----------------------------------------------------------------------
229 * Bootcountlimit Configuration
230 */
231#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
232
233/*-----------------------------------------------------------------------
234 * POST Configuration
235 */
236#if 0 /* enable this if POST is desired (is supported but not enabled) */
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237#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
238 CONFIG_SYS_POST_CPU | \
239 CONFIG_SYS_POST_RTC | \
240 CONFIG_SYS_POST_I2C)
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241
242#endif
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243/*
244 * Init Memory Controller:
245 */
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246#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
247#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
248/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
249#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
7d393aed 250
c837dcb1 251#define CONFIG_BOARD_EARLY_INIT_F 1
39441b35 252#define CONFIG_BOARD_EARLY_INIT_R
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253
254/* Peripheral Bus Mapping */
255#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
256#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
257#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
258
259#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
53677ef1 260#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
7d393aed 261
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262/*-----------------------------------------------------------------------
263 * Definitions for initial stack pointer and data area (in On Chip SRAM)
264 */
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265#define CONFIG_SYS_TEMP_STACK_OCM 1
266#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
267#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
268#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
553f0982 269#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
25ddd1fb 270#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
63e73c9a 271/* reserve some memory for POST and BOOT limit info */
6d0f6bcf 272#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
63e73c9a 273
63e73c9a 274#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
6d0f6bcf 275#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
63e73c9a 276#endif
7d393aed 277
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278/***********************************************************************
279 * External peripheral base address
280 ***********************************************************************/
6d0f6bcf 281#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
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282
283/***********************************************************************
284 * Last Stage Init
285 ***********************************************************************/
286#define CONFIG_LAST_STAGE_INIT
287/************************************************************
288 * Ethernet Stuff
289 ***********************************************************/
96e21f86 290#define CONFIG_PPC4xx_EMAC
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291#define CONFIG_MII 1 /* MII PHY management */
292#define CONFIG_PHY_ADDR 1 /* PHY address */
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293#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
294#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
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295/************************************************************
296 * RTC
297 ***********************************************************/
298#define CONFIG_RTC_MC146818
299#undef CONFIG_WATCHDOG /* watchdog disabled */
300
301/************************************************************
302 * IDE/ATA stuff
303 ************************************************************/
adf32adb 304#if defined(CONFIG_TARGET_MIP405T)
6d0f6bcf 305#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
f3e0de60 306#else
6d0f6bcf 307#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
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308#endif
309
6d0f6bcf 310#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
7d393aed 311
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312#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
313#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
314#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
315#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
316#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
317#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
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318
319#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
320#undef CONFIG_IDE_LED /* no led for ide supported */
321#define CONFIG_IDE_RESET /* reset for ide supported... */
322#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
7205e407 323#define CONFIG_SUPPORT_VFAT
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324/************************************************************
325 * ATAPI support (experimental)
326 ************************************************************/
327#define CONFIG_ATAPI /* enable ATAPI Support */
328
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329/************************************************************
330 * DISK Partition support
331 ************************************************************/
332#define CONFIG_DOS_PARTITION
333#define CONFIG_MAC_PARTITION
334#define CONFIG_ISO_PARTITION /* Experimental */
335
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336/************************************************************
337 * Video support
338 ************************************************************/
7d393aed 339#define CONFIG_VIDEO_LOGO
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340#undef CONFIG_VIDEO_ONBOARD
341/************************************************************
342 * USB support EXPERIMENTAL
343 ************************************************************/
adf32adb 344#if !defined(CONFIG_TARGET_MIP405T)
7d393aed 345#define CONFIG_USB_UHCI
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346
347/* Enable needed helper functions */
52cb4d4f 348#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
f3e0de60 349#endif
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350/************************************************************
351 * Debug support
352 ************************************************************/
8353e139 353#if defined(CONFIG_CMD_KGDB)
7d393aed 354#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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355#endif
356
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357/************************************************************
358 * support BZIP2 compression
359 ************************************************************/
360#define CONFIG_BZIP2 1
361
7d393aed 362#endif /* __CONFIG_H */