[people/ms/u-boot.git] / include / configs / MIP405.h

/*
 * (C) Copyright 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************
 * High Level Configuration Options
 * (easy to change)
 ***********************************************************/
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

/***********************************************************
 * Note that it may also be a MIP405T board which is a subset of the
 * MIP405
 ***********************************************************/
/***********************************************************
 * WARNING:
 * CONFIG_BOOT_PCI is only used for first boot-up and should
 * NOT be enabled for production bootloader
 ***********************************************************/
/*#define        CONFIG_BOOT_PCI         1*/
/***********************************************************
 * Clock
 ***********************************************************/
#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP

/**************************************************************
 * I2C Stuff:
 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
 * 0x53.
 * The Atmel EEPROM uses 16Bit addressing.
 ***************************************************************/

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
					/* 64 byte page write mode using*/
					/* last	6 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */

/***************************************************************
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 ***************************************************************/
/*#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
#define SDRAM_EEPROM_READ_ADDRESS	0xA1
*/
/**************************************************************
 * Environment definitions
 **************************************************************/
#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */

#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */

#define CONFIG_IPADDR		10.0.0.100
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
 * defines if an overwrite_console function exists
 *************************************************************/
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/***************************************************************
 * defines if the overwrite_console should be stored in the
 * environment
 **************************************************************/
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE

/**************************************************************
 * loads config
 *************************************************************/
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MISC_INIT_R
/***********************************************************
 * Miscellaneous configurable options
 **********************************************************/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD       916667

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x400000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
					/* resource configuration	*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFF80000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_UPDATE_FLASH_SIZE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_FLASH_SHOW_PROGRESS	45

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=mip405-0"
#define MTDPARTS_DEFAULT	"mtdparts=mip405-0:-(jffs2)"
*/

/*-----------------------------------------------------------------------
 * Logbuffer Configuration
 */
#undef CONFIG_LOGBUFFER		/* supported but not enabled */
/*-----------------------------------------------------------------------
 * Bootcountlimit Configuration
 */
#undef CONFIG_BOOTCOUNT_LIMIT	/* supported but not enabled */

/*-----------------------------------------------------------------------
 * POST Configuration
 */
#if 0 /* enable this if POST is desired (is supported but not enabled) */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY	| \
				 CONFIG_SYS_POST_CPU		| \
				 CONFIG_SYS_POST_RTC		| \
				 CONFIG_SYS_POST_I2C)

#endif
/*
 * Init Memory Controller:
 */
#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/

#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_BOARD_EARLY_INIT_R

/* Peripheral Bus Mapping */
#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/
#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/

#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
#define CONFIG_PORT_ADDR	PER_PLD_ADDR + 5

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in On Chip SRAM)
 */
#define CONFIG_SYS_TEMP_STACK_OCM      1
#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* reserve some memory for POST and BOOT limit info */
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)

#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
#endif

/***********************************************************************
 * External peripheral base address
 ***********************************************************************/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000

/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT
/************************************************************
 * Ethernet Stuff
 ***********************************************************/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/
#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
#define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
/************************************************************
 * RTC
 ***********************************************************/
#define CONFIG_RTC_MC146818
#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/************************************************************
 * IDE/ATA stuff
 ************************************************************/
#if defined(CONFIG_TARGET_MIP405T)
#define CONFIG_SYS_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
#else
#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#endif

#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
#undef	CONFIG_IDE_LED	       /* no led for ide supported     */
#define CONFIG_IDE_RESET       /* reset for ide supported...	*/
#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
#define CONFIG_SUPPORT_VFAT
/************************************************************
 * ATAPI support (experimental)
 ************************************************************/
#define CONFIG_ATAPI			/* enable ATAPI Support */

/************************************************************
 * DISK Partition support
 ************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */

/************************************************************
 * Video support
 ************************************************************/
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#undef CONFIG_VIDEO_ONBOARD
/************************************************************
 * USB support EXPERIMENTAL
 ************************************************************/
#if !defined(CONFIG_TARGET_MIP405T)
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD

/* Enable needed helper functions */
#define CONFIG_SYS_STDIO_DEREGISTER		/* needs stdio_deregister */
#endif
/************************************************************
 * Debug support
 ************************************************************/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/************************************************************
 * support BZIP2 compression
 ************************************************************/
#define CONFIG_BZIP2		1

#endif	/* __CONFIG_H */
Commit	Line	Data
7d393aed WD	1	/*
	2	* (C) Copyright 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
7d393aed WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/***********************************************************
	16	* High Level Configuration Options
	17	* (easy to change)
	18	***********************************************************/
	19	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
2ae18241 WD	20
	21	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	22
f3e0de60 WD	23	/***********************************************************
	24	* Note that it may also be a MIP405T board which is a subset of the
	25	* MIP405
	26	***********************************************************/
	27	/***********************************************************
	28	* WARNING:
	29	* CONFIG_BOOT_PCI is only used for first boot-up and should
	30	* NOT be enabled for production bootloader
	31	***********************************************************/
8bde7f77	32	/#define CONFIG_BOOT_PCI 1/
7d393aed WD	33	/***********************************************************
	34	* Clock
	35	***********************************************************/
	36	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	37
659e2f67 JL	38	/*
	39	* BOOTP options
	40	*/
	41	#define CONFIG_BOOTP_BOOTFILESIZE
	42	#define CONFIG_BOOTP_BOOTPATH
	43	#define CONFIG_BOOTP_GATEWAY
	44	#define CONFIG_BOOTP_HOSTNAME
	45
8353e139 JL	46	/*
	47	* Command line configuration.
	48	*/
8353e139	49	#define CONFIG_CMD_DATE
8353e139	50	#define CONFIG_CMD_EEPROM
8353e139 JL	51	#define CONFIG_CMD_IDE
	52	#define CONFIG_CMD_IRQ
	53	#define CONFIG_CMD_JFFS2
8353e139	54	#define CONFIG_CMD_PCI
8353e139 JL	55	#define CONFIG_CMD_REGINFO
	56	#define CONFIG_CMD_SAVES
	57	#define CONFIG_CMD_BSP
f3e0de60	58
7d393aed WD	59	/**************************************************************
	60	* I2C Stuff:
	61	* the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
	62	* 0x53.
	63	* The Atmel EEPROM uses 16Bit addressing.
	64	***************************************************************/
	65
880540de DE	66	#define CONFIG_SYS_I2C
	67	#define CONFIG_SYS_I2C_PPC4XX
	68	#define CONFIG_SYS_I2C_PPC4XX_CH0
	69	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
	70	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
7d393aed	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
6d0f6bcf JCPV	73	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
7d393aed	74	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	75	#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
6d0f6bcf JCPV	76	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
7d393aed WD	77	/* 64 byte page write mode using*/
7d393aed WD	78	/* last 6 bits of the address */
6d0f6bcf	79	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
7d393aed	80
bb1f8b4f	81	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	82	#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	83	#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
7d393aed WD	84
	85	/***************************************************************
	86	* Definitions for Serial Presence Detect EEPROM address
	87	* (to get SDRAM settings)
	88	***************************************************************/
f3e0de60	89	/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
53677ef1	90	#define SDRAM_EEPROM_READ_ADDRESS 0xA1
f3e0de60	91	*/
7d393aed WD	92	/**************************************************************
	93	* Environment definitions
	94	**************************************************************/
	95	#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
7d393aed	96	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2afbe4ed	97	/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
7d393aed	98
3e38691e	99	#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
7d393aed WD	100	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
	101
	102	#define CONFIG_IPADDR 10.0.0.100
	103	#define CONFIG_SERVERIP 10.0.0.1
	104	#define CONFIG_PREBOOT
7d393aed WD	105	/***************************************************************
	106	* defines if an overwrite_console function exists
	107	*************************************************************/
6d0f6bcf JCPV	108	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
6d0f6bcf JCPV	109	#define CONFIG_SYS_CONSOLE_INFO_QUIET
7d393aed WD	110	/***************************************************************
	111	* defines if the overwrite_console should be stored in the
	112	* environment
	113	**************************************************************/
6d0f6bcf	114	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
7d393aed WD	115
	116	/**************************************************************
	117	* loads config
	118	*************************************************************/
	119	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	120	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
7d393aed WD	121
	122	#define CONFIG_MISC_INIT_R
	123	/***********************************************************
	124	* Miscellaneous configurable options
	125	**********************************************************/
6d0f6bcf	126	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8353e139	127	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	128	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7d393aed	129	#else
6d0f6bcf	130	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7d393aed	131	#endif
6d0f6bcf JCPV	132	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	133	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	134	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7d393aed	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
6d0f6bcf JCPV	137	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
7d393aed	138
550650dd	139	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
550650dd SR	140	#define CONFIG_SYS_NS16550_SERIAL
	141	#define CONFIG_SYS_NS16550_REG_SIZE 1
	142	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	143
6d0f6bcf JCPV	144	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf JCPV	145	#define CONFIG_SYS_BASE_BAUD 916667
7d393aed WD	146
7d393aed WD	147	/* The following table includes the supported baudrates */
6d0f6bcf	148	#define CONFIG_SYS_BAUDRATE_TABLE \
7d393aed WD	149	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	150	57600, 115200, 230400, 460800, 921600 }
	151
6d0f6bcf JCPV	152	#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
6d0f6bcf JCPV	153	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
7d393aed	154
7d393aed WD	155	/*-----------------------------------------------------------------------
	156	* PCI stuff
	157	*-----------------------------------------------------------------------
	158	*/
	159	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	160	#define PCI_HOST_FORCE 1 /* configure as pci host */
	161	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	162
	163	#define CONFIG_PCI /* include pci support */
842033e6	164	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
7d393aed WD	165	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
	166	#define CONFIG_PCI_PNP /* pci plug-and-play */
	167	/* resource configuration */
6d0f6bcf JCPV	168	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	169	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	170	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	171	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	172	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	173	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	174	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	175	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
7d393aed WD	176
	177	/*-----------------------------------------------------------------------
	178	* Start addresses for the final memory configuration
	179	* (Set up by the startup code)
6d0f6bcf	180	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
7d393aed	181	*/
6d0f6bcf JCPV	182	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	183	#define CONFIG_SYS_FLASH_BASE 0xFFF80000
	184	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	185	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
	186	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
7d393aed WD	187
	188	/*
	189	* For booting Linux, the board info and command line data
	190	* have to be in the first 8 MB of memory, since this is
	191	* the maximum mapped by the Linux kernel during initialization.
	192	*/
6d0f6bcf	193	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7d393aed WD	194	/*-----------------------------------------------------------------------
	195	* FLASH organization
	196	*/
39441b35 DM	197	#define CONFIG_SYS_UPDATE_FLASH_SIZE
	198	#define CONFIG_SYS_FLASH_PROTECTION
	199	#define CONFIG_SYS_FLASH_EMPTY_INFO
7d393aed	200
39441b35 DM	201	#define CONFIG_SYS_FLASH_CFI
	202	#define CONFIG_FLASH_CFI_DRIVER
	203
	204	#define CONFIG_FLASH_SHOW_PROGRESS 45
	205
	206	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	207	#define CONFIG_SYS_MAX_FLASH_SECT 256
7d393aed	208
700a0c64 WD	209	/*
	210	* JFFS2 partitions
	211	*
	212	*/
	213	/* No command line, one static partition, whole device */
68d7d651	214	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	215	#define CONFIG_JFFS2_DEV "nor0"
	216	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	217	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	218
	219	/* mtdparts command line support */
	220	/* Note: fake mtd_id used, no linux mtd map file */
	221	/*
68d7d651	222	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	223	#define MTDIDS_DEFAULT "nor0=mip405-0"
	224	#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
	225	*/
7d393aed	226
63e73c9a WD	227	/*-----------------------------------------------------------------------
	228	* Logbuffer Configuration
	229	*/
53677ef1	230	#undef CONFIG_LOGBUFFER /* supported but not enabled */
63e73c9a WD	231	/*-----------------------------------------------------------------------
	232	* Bootcountlimit Configuration
	233	*/
	234	#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
	235
	236	/*-----------------------------------------------------------------------
	237	* POST Configuration
	238	*/
	239	#if 0 /* enable this if POST is desired (is supported but not enabled) */
6d0f6bcf JCPV	240	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	241	CONFIG_SYS_POST_CPU \| \
	242	CONFIG_SYS_POST_RTC \| \
	243	CONFIG_SYS_POST_I2C)
63e73c9a WD	244
63e73c9a WD	245	#endif
7d393aed WD	246	/*
	247	* Init Memory Controller:
	248	*/
7205e407 WD	249	#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
	250	#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
	251	/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
	252	#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
7d393aed	253
c837dcb1	254	#define CONFIG_BOARD_EARLY_INIT_F 1
39441b35	255	#define CONFIG_BOARD_EARLY_INIT_R
7d393aed WD	256
	257	/* Peripheral Bus Mapping */
	258	#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
	259	#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
	260	#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
	261
	262	#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
53677ef1	263	#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
7d393aed	264
7d393aed WD	265	/*-----------------------------------------------------------------------
	266	* Definitions for initial stack pointer and data area (in On Chip SRAM)
	267	*/
6d0f6bcf JCPV	268	#define CONFIG_SYS_TEMP_STACK_OCM 1
	269	#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
	270	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	271	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
553f0982	272	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
25ddd1fb	273	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
63e73c9a	274	/* reserve some memory for POST and BOOT limit info */
6d0f6bcf	275	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
63e73c9a	276
63e73c9a	277	#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
6d0f6bcf	278	#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
63e73c9a	279	#endif
7d393aed	280
7d393aed WD	281	/***********************************************************************
	282	* External peripheral base address
	283	***********************************************************************/
6d0f6bcf	284	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
7d393aed WD	285
	286	/***********************************************************************
	287	* Last Stage Init
	288	***********************************************************************/
	289	#define CONFIG_LAST_STAGE_INIT
	290	/************************************************************
	291	* Ethernet Stuff
	292	***********************************************************/
96e21f86	293	#define CONFIG_PPC4xx_EMAC
7d393aed WD	294	#define CONFIG_MII 1 /* MII PHY management */
7d393aed WD	295	#define CONFIG_PHY_ADDR 1 /* PHY address */
63e73c9a WD	296	#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
63e73c9a WD	297	#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
7d393aed WD	298	/************************************************************
	299	* RTC
	300	***********************************************************/
	301	#define CONFIG_RTC_MC146818
	302	#undef CONFIG_WATCHDOG /* watchdog disabled */
	303
	304	/************************************************************
	305	* IDE/ATA stuff
	306	************************************************************/
adf32adb	307	#if defined(CONFIG_TARGET_MIP405T)
6d0f6bcf	308	#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
f3e0de60	309	#else
6d0f6bcf	310	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
f3e0de60 WD	311	#endif
f3e0de60 WD	312
6d0f6bcf	313	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
7d393aed	314
6d0f6bcf JCPV	315	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
	316	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	317	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	318	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
	319	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
	320	#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
7d393aed WD	321
	322	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	323	#undef CONFIG_IDE_LED /* no led for ide supported */
	324	#define CONFIG_IDE_RESET /* reset for ide supported... */
	325	#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
7205e407	326	#define CONFIG_SUPPORT_VFAT
7d393aed WD	327	/************************************************************
	328	* ATAPI support (experimental)
	329	************************************************************/
	330	#define CONFIG_ATAPI /* enable ATAPI Support */
	331
7d393aed WD	332	/************************************************************
	333	* DISK Partition support
	334	************************************************************/
	335	#define CONFIG_DOS_PARTITION
	336	#define CONFIG_MAC_PARTITION
	337	#define CONFIG_ISO_PARTITION /* Experimental */
	338
7d393aed WD	339	/************************************************************
	340	* Video support
	341	************************************************************/
7d393aed WD	342	#define CONFIG_VIDEO_LOGO
	343	#define CONFIG_CONSOLE_EXTRA_INFO
	344	#define CONFIG_VGA_AS_SINGLE_DEVICE
	345	#define CONFIG_VIDEO_SW_CURSOR
	346	#undef CONFIG_VIDEO_ONBOARD
	347	/************************************************************
	348	* USB support EXPERIMENTAL
	349	************************************************************/
adf32adb	350	#if !defined(CONFIG_TARGET_MIP405T)
7d393aed WD	351	#define CONFIG_USB_UHCI
7d393aed WD	352	#define CONFIG_USB_KEYBOARD
7d393aed WD	353
7d393aed WD	354	/* Enable needed helper functions */
52cb4d4f	355	#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
f3e0de60	356	#endif
7d393aed WD	357	/************************************************************
	358	* Debug support
	359	************************************************************/
8353e139	360	#if defined(CONFIG_CMD_KGDB)
7d393aed	361	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
7d393aed WD	362	#endif
7d393aed WD	363
a2663ea4 WD	364	/************************************************************
	365	* support BZIP2 compression
	366	************************************************************/
	367	#define CONFIG_BZIP2 1
	368
7d393aed	369	#endif /* __CONFIG_H */