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Commit | Line | Data |
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19580e66 DL |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
19580e66 DL |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
19580e66 DL |
11 | /* |
12 | * High Level Configuration Options | |
13 | */ | |
14 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 15 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
19580e66 DL |
16 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ |
17 | ||
2ae18241 WD |
18 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
19 | ||
19580e66 DL |
20 | /* |
21 | * System Clock Setup | |
22 | */ | |
23 | #ifdef CONFIG_PCISLAVE | |
24 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
25 | #else | |
26 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
27 | #endif | |
28 | ||
29 | #ifndef CONFIG_SYS_CLK_FREQ | |
30 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
31 | #endif | |
32 | ||
33 | /* | |
34 | * Hardware Reset Configuration Word | |
35 | * if CLKIN is 66MHz, then | |
36 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz | |
37 | */ | |
6d0f6bcf | 38 | #define CONFIG_SYS_HRCW_LOW (\ |
19580e66 DL |
39 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
40 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
41 | HRCWL_SVCOD_DIV_2 |\ | |
42 | HRCWL_CSB_TO_CLKIN_6X1 |\ | |
43 | HRCWL_CORE_TO_CSB_1_5X1) | |
44 | ||
45 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 46 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
47 | HRCWH_PCI_AGENT |\ |
48 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
49 | HRCWH_CORE_ENABLE |\ | |
50 | HRCWH_FROM_0XFFF00100 |\ | |
51 | HRCWH_BOOTSEQ_DISABLE |\ | |
52 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
53 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
54 | HRCWH_RL_EXT_LEGACY |\ | |
55 | HRCWH_TSEC1M_IN_RGMII |\ | |
56 | HRCWH_TSEC2M_IN_RGMII |\ | |
57 | HRCWH_BIG_ENDIAN |\ | |
58 | HRCWH_LDP_CLEAR) | |
59 | #else | |
6d0f6bcf | 60 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
61 | HRCWH_PCI_HOST |\ |
62 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
63 | HRCWH_CORE_ENABLE |\ | |
64 | HRCWH_FROM_0X00000100 |\ | |
65 | HRCWH_BOOTSEQ_DISABLE |\ | |
66 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
67 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
68 | HRCWH_RL_EXT_LEGACY |\ | |
69 | HRCWH_TSEC1M_IN_RGMII |\ | |
70 | HRCWH_TSEC2M_IN_RGMII |\ | |
71 | HRCWH_BIG_ENDIAN |\ | |
72 | HRCWH_LDP_CLEAR) | |
73 | #endif | |
74 | ||
bd4458cb | 75 | /* Arbiter Configuration Register */ |
6d0f6bcf | 76 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
8d85808f | 77 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
bd4458cb DL |
78 | |
79 | /* System Priority Control Register */ | |
8d85808f | 80 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ |
bd4458cb | 81 | |
19580e66 | 82 | /* |
bd4458cb | 83 | * IP blocks clock configuration |
19580e66 | 84 | */ |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ |
86 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ | |
8d85808f | 87 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ |
19580e66 DL |
88 | |
89 | /* | |
90 | * System IO Config | |
91 | */ | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_SICRH 0x00000000 |
93 | #define CONFIG_SYS_SICRL 0x00000000 | |
19580e66 DL |
94 | |
95 | /* | |
96 | * Output Buffer Impedance | |
97 | */ | |
6d0f6bcf | 98 | #define CONFIG_SYS_OBIR 0x31100000 |
19580e66 DL |
99 | |
100 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
101 | #define CONFIG_BOARD_EARLY_INIT_R | |
c78c6783 | 102 | #define CONFIG_HWCONFIG |
19580e66 DL |
103 | |
104 | /* | |
105 | * IMMR new address | |
106 | */ | |
6d0f6bcf | 107 | #define CONFIG_SYS_IMMR 0xE0000000 |
19580e66 DL |
108 | |
109 | /* | |
110 | * DDR Setup | |
111 | */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
113 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
114 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
115 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
116 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
2fef4020 JH |
117 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
118 | | DDRCDR_ODT \ | |
119 | | DDRCDR_Q_DRN) | |
120 | /* 0x80080001 */ /* ODT 150ohm on SoC */ | |
19580e66 DL |
121 | |
122 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
123 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
124 | ||
125 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
126 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
127 | ||
128 | #if defined(CONFIG_SPD_EEPROM) | |
129 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ | |
130 | #else | |
131 | /* | |
132 | * Manually set up DDR parameters | |
7e74d63d | 133 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
19580e66 DL |
134 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
135 | */ | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
137 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f | |
8d85808f | 138 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
139 | | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ |
140 | | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ | |
141 | | CSCONFIG_ROW_BIT_14 \ | |
142 | | CSCONFIG_COL_BIT_10) | |
143 | /* 0x80010202 */ | |
6d0f6bcf | 144 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
8d85808f JH |
145 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
146 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
147 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
148 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
149 | | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
150 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
151 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
152 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
19580e66 | 153 | /* 0x00620802 */ |
8d85808f JH |
154 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
155 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
156 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
157 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
158 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
159 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
160 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
161 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
19580e66 | 162 | /* 0x3935d322 */ |
8d85808f JH |
163 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
164 | | (6 << TIMING_CFG2_CPO_SHIFT) \ | |
165 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
166 | | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
167 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
168 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
169 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
7e74d63d | 170 | /* 0x131088c8 */ |
8d85808f JH |
171 | #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
172 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
19580e66 | 173 | /* 0x03E00100 */ |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
175 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ | |
8d85808f JH |
176 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
177 | | (0x1432 << SDRAM_MODE_SD_SHIFT)) | |
7e74d63d | 178 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
8d85808f | 179 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
19580e66 DL |
180 | #endif |
181 | ||
182 | /* | |
183 | * Memory test | |
184 | */ | |
6d0f6bcf JCPV |
185 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
186 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
187 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
19580e66 DL |
188 | |
189 | /* | |
190 | * The reserved memory | |
191 | */ | |
14d0a02a | 192 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
19580e66 | 193 | |
6d0f6bcf JCPV |
194 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
195 | #define CONFIG_SYS_RAMBOOT | |
19580e66 | 196 | #else |
6d0f6bcf | 197 | #undef CONFIG_SYS_RAMBOOT |
19580e66 DL |
198 | #endif |
199 | ||
6d0f6bcf | 200 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
8d85808f JH |
201 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
202 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
19580e66 DL |
203 | |
204 | /* | |
205 | * Initial RAM Base Address Setup | |
206 | */ | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
208 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 209 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
8d85808f JH |
210 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
211 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
19580e66 DL |
212 | |
213 | /* | |
214 | * Local Bus Configuration & Clock Setup | |
215 | */ | |
c7190f02 KP |
216 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
217 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 218 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 219 | #define CONFIG_FSL_ELBC 1 |
19580e66 DL |
220 | |
221 | /* | |
222 | * FLASH on the Local Bus | |
223 | */ | |
8d85808f | 224 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 225 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
8d85808f JH |
226 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
227 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
228 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
19580e66 | 229 | |
8d85808f JH |
230 | /* Window base at flash base */ |
231 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 232 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
19580e66 | 233 | |
8d85808f | 234 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
235 | | BR_PS_16 /* 16 bit port */ \ |
236 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
237 | | BR_V) /* valid */ | |
238 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
ded08317 DL |
239 | | OR_UPM_XAM \ |
240 | | OR_GPCM_CSNT \ | |
f9023afb | 241 | | OR_GPCM_ACS_DIV2 \ |
ded08317 DL |
242 | | OR_GPCM_XACS \ |
243 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
244 | | OR_GPCM_TRLX_SET \ |
245 | | OR_GPCM_EHTR_SET \ | |
8d85808f | 246 | | OR_GPCM_EAD) |
ded08317 | 247 | /* 0xFE000FF7 */ |
19580e66 | 248 | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
250 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
19580e66 | 251 | |
6d0f6bcf JCPV |
252 | #undef CONFIG_SYS_FLASH_CHECKSUM |
253 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
254 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
19580e66 DL |
255 | |
256 | /* | |
257 | * BCSR on the Local Bus | |
258 | */ | |
6d0f6bcf | 259 | #define CONFIG_SYS_BCSR 0xF8000000 |
8d85808f JH |
260 | /* Access window base at BCSR base */ |
261 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
262 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
263 | ||
264 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
265 | | BR_PS_8 \ | |
266 | | BR_MS_GPCM \ | |
267 | | BR_V) | |
268 | /* 0xF8000801 */ | |
269 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
270 | | OR_GPCM_XAM \ | |
271 | | OR_GPCM_CSNT \ | |
272 | | OR_GPCM_XACS \ | |
273 | | OR_GPCM_SCY_15 \ | |
274 | | OR_GPCM_TRLX_SET \ | |
275 | | OR_GPCM_EHTR_SET \ | |
276 | | OR_GPCM_EAD) | |
277 | /* 0xFFFFE9F7 */ | |
19580e66 DL |
278 | |
279 | /* | |
280 | * NAND Flash on the Local Bus | |
281 | */ | |
b3379f3f AV |
282 | #define CONFIG_CMD_NAND 1 |
283 | #define CONFIG_MTD_NAND_VERIFY_WRITE 1 | |
284 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
8d85808f | 285 | #define CONFIG_NAND_FSL_ELBC 1 |
b3379f3f | 286 | |
7d6a0982 | 287 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
8d85808f | 288 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 289 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
8d85808f | 290 | | BR_PS_8 /* 8 bit port */ \ |
19580e66 | 291 | | BR_MS_FCM /* MSEL = FCM */ \ |
7d6a0982 JH |
292 | | BR_V) /* valid */ |
293 | #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | |
b3379f3f | 294 | | OR_FCM_BCTLD \ |
19580e66 DL |
295 | | OR_FCM_CST \ |
296 | | OR_FCM_CHT \ | |
297 | | OR_FCM_SCY_1 \ | |
b3379f3f | 298 | | OR_FCM_RST \ |
19580e66 | 299 | | OR_FCM_TRLX \ |
8d85808f | 300 | | OR_FCM_EHTR) |
b3379f3f | 301 | /* 0xFFFF919E */ |
19580e66 | 302 | |
6d0f6bcf | 303 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 304 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
19580e66 DL |
305 | |
306 | /* | |
307 | * Serial Port | |
308 | */ | |
309 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_NS16550 |
311 | #define CONFIG_SYS_NS16550_SERIAL | |
312 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
313 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
19580e66 | 314 | |
6d0f6bcf | 315 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8d85808f | 316 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
19580e66 | 317 | |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
319 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
19580e66 DL |
320 | |
321 | /* Use the HUSH parser */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_HUSH_PARSER |
19580e66 DL |
323 | |
324 | /* Pass open firmware flat tree */ | |
325 | #define CONFIG_OF_LIBFDT 1 | |
326 | #define CONFIG_OF_BOARD_SETUP 1 | |
5b8bc606 | 327 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
19580e66 DL |
328 | |
329 | /* I2C */ | |
00f792e0 HS |
330 | #define CONFIG_SYS_I2C |
331 | #define CONFIG_SYS_I2C_FSL | |
332 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
333 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
334 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
335 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
19580e66 DL |
336 | |
337 | /* | |
338 | * Config on-board RTC | |
339 | */ | |
340 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 341 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
19580e66 DL |
342 | |
343 | /* | |
344 | * General PCI | |
345 | * Addresses are mapped 1-1. | |
346 | */ | |
8d85808f JH |
347 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
348 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
349 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
351 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
352 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
353 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
354 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
355 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
19580e66 | 356 | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
358 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
359 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
19580e66 | 360 | |
8b34557c AV |
361 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
362 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
363 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
364 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
365 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
366 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
367 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
368 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
369 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
370 | ||
371 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
372 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
373 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
374 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
375 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
376 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
377 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
378 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
379 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
380 | ||
19580e66 | 381 | #ifdef CONFIG_PCI |
842033e6 | 382 | #define CONFIG_PCI_INDIRECT_BRIDGE |
00f7bbae AV |
383 | #ifndef __ASSEMBLY__ |
384 | extern int board_pci_host_broken(void); | |
385 | #endif | |
be9b56df | 386 | #define CONFIG_PCIE |
19580e66 DL |
387 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ |
388 | ||
3bf1be3c | 389 | #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ |
6c3c5750 NB |
390 | #define CONFIG_CMD_USB |
391 | #define CONFIG_USB_STORAGE | |
392 | #define CONFIG_USB_EHCI | |
393 | #define CONFIG_USB_EHCI_FSL | |
394 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
3bf1be3c | 395 | |
19580e66 DL |
396 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
397 | ||
398 | #undef CONFIG_EEPRO100 | |
399 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 400 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
19580e66 DL |
401 | #endif /* CONFIG_PCI */ |
402 | ||
19580e66 DL |
403 | /* |
404 | * TSEC | |
405 | */ | |
406 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf | 407 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
8d85808f | 408 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 409 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
8d85808f | 410 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
19580e66 DL |
411 | |
412 | /* | |
413 | * TSEC ethernet configuration | |
414 | */ | |
415 | #define CONFIG_MII 1 /* MII PHY management */ | |
416 | #define CONFIG_TSEC1 1 | |
417 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
418 | #define CONFIG_TSEC2 1 | |
419 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
420 | #define TSEC1_PHY_ADDR 2 | |
421 | #define TSEC2_PHY_ADDR 3 | |
1da83a63 AV |
422 | #define TSEC1_PHY_ADDR_SGMII 8 |
423 | #define TSEC2_PHY_ADDR_SGMII 4 | |
19580e66 DL |
424 | #define TSEC1_PHYIDX 0 |
425 | #define TSEC2_PHYIDX 0 | |
426 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
427 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
428 | ||
429 | /* Options are: TSEC[0-1] */ | |
430 | #define CONFIG_ETHPRIME "eTSEC1" | |
431 | ||
6f8c85e8 DL |
432 | /* SERDES */ |
433 | #define CONFIG_FSL_SERDES | |
434 | #define CONFIG_FSL_SERDES1 0xe3000 | |
435 | #define CONFIG_FSL_SERDES2 0xe3100 | |
436 | ||
2eeb3e4f DL |
437 | /* |
438 | * SATA | |
439 | */ | |
440 | #define CONFIG_LIBATA | |
441 | #define CONFIG_FSL_SATA | |
442 | ||
6d0f6bcf | 443 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
2eeb3e4f | 444 | #define CONFIG_SATA1 |
6d0f6bcf | 445 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
8d85808f JH |
446 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
447 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
2eeb3e4f | 448 | #define CONFIG_SATA2 |
6d0f6bcf | 449 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
8d85808f JH |
450 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
451 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
2eeb3e4f DL |
452 | |
453 | #ifdef CONFIG_FSL_SATA | |
454 | #define CONFIG_LBA48 | |
455 | #define CONFIG_CMD_SATA | |
456 | #define CONFIG_DOS_PARTITION | |
457 | #define CONFIG_CMD_EXT2 | |
458 | #endif | |
459 | ||
19580e66 DL |
460 | /* |
461 | * Environment | |
462 | */ | |
6d0f6bcf | 463 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 464 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8d85808f JH |
465 | #define CONFIG_ENV_ADDR \ |
466 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
467 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
468 | #define CONFIG_ENV_SIZE 0x2000 | |
19580e66 | 469 | #else |
8d85808f | 470 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 471 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 472 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 473 | #define CONFIG_ENV_SIZE 0x2000 |
19580e66 DL |
474 | #endif |
475 | ||
476 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 477 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
19580e66 DL |
478 | |
479 | /* | |
480 | * BOOTP options | |
481 | */ | |
482 | #define CONFIG_BOOTP_BOOTFILESIZE | |
483 | #define CONFIG_BOOTP_BOOTPATH | |
484 | #define CONFIG_BOOTP_GATEWAY | |
485 | #define CONFIG_BOOTP_HOSTNAME | |
486 | ||
487 | ||
488 | /* | |
489 | * Command line configuration. | |
490 | */ | |
491 | #include <config_cmd_default.h> | |
492 | ||
493 | #define CONFIG_CMD_PING | |
494 | #define CONFIG_CMD_I2C | |
495 | #define CONFIG_CMD_MII | |
496 | #define CONFIG_CMD_DATE | |
497 | ||
498 | #if defined(CONFIG_PCI) | |
499 | #define CONFIG_CMD_PCI | |
500 | #endif | |
501 | ||
6d0f6bcf | 502 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 503 | #undef CONFIG_CMD_SAVEENV |
19580e66 DL |
504 | #undef CONFIG_CMD_LOADS |
505 | #endif | |
506 | ||
507 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
a059e90e | 508 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
19580e66 DL |
509 | |
510 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
511 | ||
e1ac387f AF |
512 | #define CONFIG_MMC 1 |
513 | ||
514 | #ifdef CONFIG_MMC | |
515 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 516 | #define CONFIG_FSL_ESDHC_PIN_MUX |
e1ac387f AF |
517 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
518 | #define CONFIG_CMD_MMC | |
519 | #define CONFIG_GENERIC_MMC | |
520 | #define CONFIG_CMD_EXT2 | |
521 | #define CONFIG_CMD_FAT | |
522 | #define CONFIG_DOS_PARTITION | |
523 | #endif | |
524 | ||
19580e66 DL |
525 | /* |
526 | * Miscellaneous configurable options | |
527 | */ | |
6d0f6bcf JCPV |
528 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
529 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
19580e66 DL |
530 | |
531 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 532 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
19580e66 | 533 | #else |
6d0f6bcf | 534 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
19580e66 DL |
535 | #endif |
536 | ||
8d85808f JH |
537 | /* Print Buffer Size */ |
538 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
539 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
540 | /* Boot Argument Buffer Size */ | |
541 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
19580e66 DL |
542 | |
543 | /* | |
544 | * For booting Linux, the board info and command line data | |
9f530d59 | 545 | * have to be in the first 256 MB of memory, since this is |
19580e66 DL |
546 | * the maximum mapped by the Linux kernel during initialization. |
547 | */ | |
8d85808f | 548 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
19580e66 DL |
549 | |
550 | /* | |
551 | * Core HID Setup | |
552 | */ | |
1a2e203b KP |
553 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
554 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
555 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 556 | #define CONFIG_SYS_HID2 HID2_HBE |
19580e66 | 557 | |
19580e66 DL |
558 | /* |
559 | * MMU Setup | |
560 | */ | |
31d82672 | 561 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
19580e66 DL |
562 | |
563 | /* DDR: cache cacheable */ | |
6d0f6bcf JCPV |
564 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
565 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
19580e66 | 566 | |
8d85808f | 567 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 568 | | BATL_PP_RW \ |
8d85808f JH |
569 | | BATL_MEMCOHERENCE) |
570 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
571 | | BATU_BL_256M \ | |
572 | | BATU_VS \ | |
573 | | BATU_VP) | |
6d0f6bcf JCPV |
574 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
575 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
19580e66 | 576 | |
8d85808f | 577 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 578 | | BATL_PP_RW \ |
8d85808f JH |
579 | | BATL_MEMCOHERENCE) |
580 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
581 | | BATU_BL_256M \ | |
582 | | BATU_VS \ | |
583 | | BATU_VP) | |
6d0f6bcf JCPV |
584 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
585 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
19580e66 DL |
586 | |
587 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
8d85808f | 588 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 589 | | BATL_PP_RW \ |
8d85808f JH |
590 | | BATL_CACHEINHIBIT \ |
591 | | BATL_GUARDEDSTORAGE) | |
592 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
593 | | BATU_BL_8M \ | |
594 | | BATU_VS \ | |
595 | | BATU_VP) | |
6d0f6bcf JCPV |
596 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
597 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
19580e66 DL |
598 | |
599 | /* BCSR: cache-inhibit and guarded */ | |
8d85808f | 600 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ |
72cd4087 | 601 | | BATL_PP_RW \ |
8d85808f JH |
602 | | BATL_CACHEINHIBIT \ |
603 | | BATL_GUARDEDSTORAGE) | |
604 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ | |
605 | | BATU_BL_128K \ | |
606 | | BATU_VS \ | |
607 | | BATU_VP) | |
6d0f6bcf JCPV |
608 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
609 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
19580e66 DL |
610 | |
611 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
8d85808f | 612 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 613 | | BATL_PP_RW \ |
8d85808f JH |
614 | | BATL_MEMCOHERENCE) |
615 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
616 | | BATU_BL_32M \ | |
617 | | BATU_VS \ | |
618 | | BATU_VP) | |
619 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 620 | | BATL_PP_RW \ |
8d85808f JH |
621 | | BATL_CACHEINHIBIT \ |
622 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 623 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
19580e66 DL |
624 | |
625 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 626 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
8d85808f JH |
627 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
628 | | BATU_BL_128K \ | |
629 | | BATU_VS \ | |
630 | | BATU_VP) | |
6d0f6bcf JCPV |
631 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
632 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
19580e66 DL |
633 | |
634 | #ifdef CONFIG_PCI | |
635 | /* PCI MEM space: cacheable */ | |
8d85808f | 636 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 637 | | BATL_PP_RW \ |
8d85808f JH |
638 | | BATL_MEMCOHERENCE) |
639 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
640 | | BATU_BL_256M \ | |
641 | | BATU_VS \ | |
642 | | BATU_VP) | |
6d0f6bcf JCPV |
643 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
644 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
19580e66 | 645 | /* PCI MMIO space: cache-inhibit and guarded */ |
8d85808f | 646 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 647 | | BATL_PP_RW \ |
8d85808f JH |
648 | | BATL_CACHEINHIBIT \ |
649 | | BATL_GUARDEDSTORAGE) | |
650 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
651 | | BATU_BL_256M \ | |
652 | | BATU_VS \ | |
653 | | BATU_VP) | |
6d0f6bcf JCPV |
654 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
655 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 | 656 | #else |
6d0f6bcf JCPV |
657 | #define CONFIG_SYS_IBAT6L (0) |
658 | #define CONFIG_SYS_IBAT6U (0) | |
659 | #define CONFIG_SYS_IBAT7L (0) | |
660 | #define CONFIG_SYS_IBAT7U (0) | |
661 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
662 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
663 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
664 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 DL |
665 | #endif |
666 | ||
19580e66 DL |
667 | #if defined(CONFIG_CMD_KGDB) |
668 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
19580e66 DL |
669 | #endif |
670 | ||
671 | /* | |
672 | * Environment Configuration | |
673 | */ | |
674 | ||
675 | #define CONFIG_ENV_OVERWRITE | |
676 | ||
677 | #if defined(CONFIG_TSEC_ENET) | |
678 | #define CONFIG_HAS_ETH0 | |
19580e66 | 679 | #define CONFIG_HAS_ETH1 |
19580e66 DL |
680 | #endif |
681 | ||
682 | #define CONFIG_BAUDRATE 115200 | |
683 | ||
79f516bc | 684 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
19580e66 DL |
685 | |
686 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
687 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
688 | ||
689 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d85808f JH |
690 | "netdev=eth0\0" \ |
691 | "consoledev=ttyS0\0" \ | |
692 | "ramdiskaddr=1000000\0" \ | |
693 | "ramdiskfile=ramfs.83xx\0" \ | |
694 | "fdtaddr=780000\0" \ | |
695 | "fdtfile=mpc8379_mds.dtb\0" \ | |
696 | "" | |
19580e66 DL |
697 | |
698 | #define CONFIG_NFSBOOTCOMMAND \ | |
8d85808f JH |
699 | "setenv bootargs root=/dev/nfs rw " \ |
700 | "nfsroot=$serverip:$rootpath " \ | |
701 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
702 | "$netdev:off " \ | |
703 | "console=$consoledev,$baudrate $othbootargs;" \ | |
704 | "tftp $loadaddr $bootfile;" \ | |
705 | "tftp $fdtaddr $fdtfile;" \ | |
706 | "bootm $loadaddr - $fdtaddr" | |
19580e66 DL |
707 | |
708 | #define CONFIG_RAMBOOTCOMMAND \ | |
8d85808f JH |
709 | "setenv bootargs root=/dev/ram rw " \ |
710 | "console=$consoledev,$baudrate $othbootargs;" \ | |
711 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
712 | "tftp $loadaddr $bootfile;" \ | |
713 | "tftp $fdtaddr $fdtfile;" \ | |
714 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
19580e66 DL |
715 | |
716 | ||
717 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
718 | ||
719 | #endif /* __CONFIG_H */ |