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5e918a98 KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Kevin Lam <kevin.lam@freescale.com> | |
4 | * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5e918a98 KP |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 16 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
5e918a98 | 17 | #define CONFIG_MPC837XERDB 1 |
77d52ed2 SA |
18 | #define CONFIG_DISPLAY_BOARDINFO |
19 | #define CONFIG_SYS_GENERIC_BOARD | |
5e918a98 | 20 | |
2ae18241 WD |
21 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
22 | ||
5e918a98 KP |
23 | #define CONFIG_PCI 1 |
24 | ||
2bd7460e | 25 | #define CONFIG_BOARD_EARLY_INIT_F |
89c7784e | 26 | #define CONFIG_MISC_INIT_R |
c9646ed7 | 27 | #define CONFIG_HWCONFIG |
89c7784e TT |
28 | |
29 | /* | |
30 | * On-board devices | |
31 | */ | |
32 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ | |
33 | #define CONFIG_VSC7385_ENET | |
34 | ||
5e918a98 KP |
35 | /* |
36 | * System Clock Setup | |
37 | */ | |
38 | #ifdef CONFIG_PCISLAVE | |
39 | #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ | |
40 | #else | |
41 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
be9b56df | 42 | #define CONFIG_PCIE |
5e918a98 KP |
43 | #endif |
44 | ||
45 | #ifndef CONFIG_SYS_CLK_FREQ | |
46 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
47 | #endif | |
48 | ||
49 | /* | |
50 | * Hardware Reset Configuration Word | |
51 | */ | |
6d0f6bcf | 52 | #define CONFIG_SYS_HRCW_LOW (\ |
5e918a98 KP |
53 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
54 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
55 | HRCWL_SVCOD_DIV_2 |\ | |
56 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
57 | HRCWL_CORE_TO_CSB_2X1) | |
58 | ||
59 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 60 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
61 | HRCWH_PCI_AGENT |\ |
62 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
63 | HRCWH_CORE_ENABLE |\ | |
64 | HRCWH_FROM_0XFFF00100 |\ | |
65 | HRCWH_BOOTSEQ_DISABLE |\ | |
66 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
67 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
68 | HRCWH_RL_EXT_LEGACY |\ | |
69 | HRCWH_TSEC1M_IN_RGMII |\ | |
70 | HRCWH_TSEC2M_IN_RGMII |\ | |
71 | HRCWH_BIG_ENDIAN |\ | |
72 | HRCWH_LDP_CLEAR) | |
73 | #else | |
6d0f6bcf | 74 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
75 | HRCWH_PCI_HOST |\ |
76 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
77 | HRCWH_CORE_ENABLE |\ | |
78 | HRCWH_FROM_0X00000100 |\ | |
79 | HRCWH_BOOTSEQ_DISABLE |\ | |
80 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
81 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
82 | HRCWH_RL_EXT_LEGACY |\ | |
83 | HRCWH_TSEC1M_IN_RGMII |\ | |
84 | HRCWH_TSEC2M_IN_RGMII |\ | |
85 | HRCWH_BIG_ENDIAN |\ | |
86 | HRCWH_LDP_CLEAR) | |
87 | #endif | |
88 | ||
6d0f6bcf | 89 | /* System performance - define the value i.e. CONFIG_SYS_XXX |
5e918a98 KP |
90 | */ |
91 | ||
92 | /* Arbiter Configuration Register */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
5afe9722 | 94 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
5e918a98 KP |
95 | |
96 | /* System Priority Control Regsiter */ | |
5afe9722 | 97 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ |
5e918a98 KP |
98 | |
99 | /* System Clock Configuration Register */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ |
101 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ | |
5afe9722 | 102 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ |
5e918a98 KP |
103 | |
104 | /* | |
105 | * System IO Config | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_SICRH 0x08200000 |
108 | #define CONFIG_SYS_SICRL 0x00000000 | |
5e918a98 KP |
109 | |
110 | /* | |
111 | * Output Buffer Impedance | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_OBIR 0x30100000 |
5e918a98 KP |
114 | |
115 | /* | |
116 | * IMMR new address | |
117 | */ | |
6d0f6bcf | 118 | #define CONFIG_SYS_IMMR 0xE0000000 |
5e918a98 | 119 | |
89c7784e TT |
120 | /* |
121 | * Device configurations | |
122 | */ | |
123 | ||
124 | /* Vitesse 7385 */ | |
125 | ||
126 | #ifdef CONFIG_VSC7385_ENET | |
127 | ||
128 | #define CONFIG_TSEC2 | |
129 | ||
130 | /* The flash address and size of the VSC7385 firmware image */ | |
131 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
132 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
133 | ||
134 | #endif | |
135 | ||
5e918a98 KP |
136 | /* |
137 | * DDR Setup | |
138 | */ | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
140 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
141 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
142 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 | |
143 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
5e918a98 | 144 | |
6d0f6bcf | 145 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) |
5e918a98 KP |
146 | |
147 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
148 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
149 | ||
150 | #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
151 | ||
152 | /* | |
153 | * Manually set up DDR parameters | |
154 | */ | |
6d0f6bcf | 155 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 JH |
156 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
157 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
158 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
159 | | CSCONFIG_ROW_BIT_13 \ | |
160 | | CSCONFIG_COL_BIT_10) | |
5e918a98 | 161 | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
163 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
5e918a98 KP |
164 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
165 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
166 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
167 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
168 | | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
169 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
170 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
5e918a98 | 171 | /* 0x00260802 */ /* DDR400 */ |
6d0f6bcf | 172 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
5e918a98 KP |
173 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
174 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
175 | | (7 << TIMING_CFG1_CASLAT_SHIFT) \ | |
176 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
177 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
178 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
179 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
5e918a98 | 180 | /* 0x3937d322 */ |
2fef4020 JH |
181 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
182 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
183 | | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
184 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
185 | | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
186 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
187 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
188 | /* 0x02984cc8 */ | |
5e918a98 | 189 | |
8eceeb7f KP |
190 | #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
191 | | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
5e918a98 KP |
192 | /* 0x06090100 */ |
193 | ||
194 | #if defined(CONFIG_DDR_2T_TIMING) | |
5afe9722 | 195 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 JH |
196 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
197 | | SDRAM_CFG_32_BE \ | |
198 | | SDRAM_CFG_2T_EN) | |
199 | /* 0x43088000 */ | |
5e918a98 | 200 | #else |
5afe9722 | 201 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 | 202 | | SDRAM_CFG_SDRAM_TYPE_DDR2) |
5afe9722 | 203 | /* 0x43000000 */ |
5e918a98 | 204 | #endif |
6d0f6bcf | 205 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |
8eceeb7f | 206 | #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ |
5afe9722 JH |
207 | | (0x0442 << SDRAM_MODE_SD_SHIFT)) |
208 | /* 0x04400442 */ /* DDR400 */ | |
6d0f6bcf | 209 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
5e918a98 KP |
210 | |
211 | /* | |
212 | * Memory test | |
213 | */ | |
6d0f6bcf JCPV |
214 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
215 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
216 | #define CONFIG_SYS_MEMTEST_END 0x0ef70010 | |
5e918a98 KP |
217 | |
218 | /* | |
219 | * The reserved memory | |
220 | */ | |
14d0a02a | 221 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5e918a98 | 222 | |
6d0f6bcf JCPV |
223 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
224 | #define CONFIG_SYS_RAMBOOT | |
5e918a98 | 225 | #else |
6d0f6bcf | 226 | #undef CONFIG_SYS_RAMBOOT |
5e918a98 KP |
227 | #endif |
228 | ||
5afe9722 JH |
229 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
230 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
5e918a98 KP |
231 | |
232 | /* | |
233 | * Initial RAM Base Address Setup | |
234 | */ | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
236 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 237 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
5afe9722 JH |
238 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
239 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
5e918a98 KP |
240 | |
241 | /* | |
242 | * Local Bus Configuration & Clock Setup | |
243 | */ | |
c7190f02 KP |
244 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
245 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 246 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 247 | #define CONFIG_FSL_ELBC 1 |
5e918a98 KP |
248 | |
249 | /* | |
250 | * FLASH on the Local Bus | |
251 | */ | |
6d0f6bcf | 252 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 253 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
254 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
255 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ | |
5e918a98 | 256 | |
5afe9722 JH |
257 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
258 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
259 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
5e918a98 | 260 | |
5afe9722 JH |
261 | /* Window base at flash base */ |
262 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
6d0f6bcf | 263 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ |
5e918a98 | 264 | |
5afe9722 | 265 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
266 | | BR_PS_16 /* 16 bit port */ \ |
267 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
268 | | BR_V) /* valid */ | |
269 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
5e918a98 KP |
270 | | OR_GPCM_XACS \ |
271 | | OR_GPCM_SCY_9 \ | |
7d6a0982 | 272 | | OR_GPCM_EHTR_SET \ |
5e918a98 | 273 | | OR_GPCM_EAD) |
7d6a0982 | 274 | /* 0xFF800191 */ |
5e918a98 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
277 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5e918a98 | 278 | |
6d0f6bcf JCPV |
279 | #undef CONFIG_SYS_FLASH_CHECKSUM |
280 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
281 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5e918a98 | 282 | |
46a3aeea AV |
283 | /* |
284 | * NAND Flash on the Local Bus | |
285 | */ | |
7d6a0982 | 286 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
5afe9722 | 287 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 JH |
288 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
289 | | BR_PS_8 /* 8 bit port */ \ | |
290 | | BR_MS_FCM /* MSEL = FCM */ \ | |
5afe9722 | 291 | | BR_V) /* valid */ |
7d6a0982 | 292 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
5afe9722 JH |
293 | | OR_FCM_CSCT \ |
294 | | OR_FCM_CST \ | |
295 | | OR_FCM_CHT \ | |
296 | | OR_FCM_SCY_1 \ | |
297 | | OR_FCM_TRLX \ | |
298 | | OR_FCM_EHTR) | |
6d0f6bcf | 299 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 300 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
46a3aeea | 301 | |
89c7784e TT |
302 | /* Vitesse 7385 */ |
303 | ||
6d0f6bcf | 304 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
5e918a98 | 305 | |
89c7784e TT |
306 | #ifdef CONFIG_VSC7385_ENET |
307 | ||
7d6a0982 JH |
308 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
309 | | BR_PS_8 \ | |
310 | | BR_MS_GPCM \ | |
311 | | BR_V) | |
312 | /* 0xF0000801 */ | |
313 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | |
314 | | OR_GPCM_CSNT \ | |
315 | | OR_GPCM_XACS \ | |
316 | | OR_GPCM_SCY_15 \ | |
317 | | OR_GPCM_SETA \ | |
318 | | OR_GPCM_TRLX_SET \ | |
319 | | OR_GPCM_EHTR_SET \ | |
320 | | OR_GPCM_EAD) | |
321 | /* 0xfffe09ff */ | |
322 | ||
5afe9722 JH |
323 | /* Access Base */ |
324 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 325 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
5e918a98 | 326 | |
89c7784e TT |
327 | #endif |
328 | ||
5e918a98 KP |
329 | /* |
330 | * Serial Port | |
331 | */ | |
332 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_NS16550 |
334 | #define CONFIG_SYS_NS16550_SERIAL | |
335 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
336 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5e918a98 | 337 | |
6d0f6bcf | 338 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5afe9722 | 339 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
5e918a98 | 340 | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
342 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5e918a98 | 343 | |
2bd7460e AV |
344 | /* SERDES */ |
345 | #define CONFIG_FSL_SERDES | |
346 | #define CONFIG_FSL_SERDES1 0xe3000 | |
347 | #define CONFIG_FSL_SERDES2 0xe3100 | |
348 | ||
5e918a98 | 349 | /* Use the HUSH parser */ |
6d0f6bcf | 350 | #define CONFIG_SYS_HUSH_PARSER |
5e918a98 KP |
351 | |
352 | /* Pass open firmware flat tree */ | |
353 | #define CONFIG_OF_LIBFDT 1 | |
354 | #define CONFIG_OF_BOARD_SETUP 1 | |
aabce7fb | 355 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
5e918a98 KP |
356 | |
357 | /* I2C */ | |
00f792e0 HS |
358 | #define CONFIG_SYS_I2C |
359 | #define CONFIG_SYS_I2C_FSL | |
360 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
361 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
362 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
363 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
5e918a98 KP |
364 | |
365 | /* | |
366 | * Config on-board RTC | |
367 | */ | |
368 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 369 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5e918a98 KP |
370 | |
371 | /* | |
372 | * General PCI | |
373 | * Addresses are mapped 1-1. | |
374 | */ | |
5afe9722 JH |
375 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
376 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
377 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
379 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
380 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
381 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
382 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
383 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
384 | ||
385 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
386 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
387 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5e918a98 | 388 | |
7e915580 AV |
389 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
390 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
391 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
392 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
393 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
394 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
395 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
396 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
397 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
398 | ||
399 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
400 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
401 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
402 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
403 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
404 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
405 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
406 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
407 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
408 | ||
5e918a98 | 409 | #ifdef CONFIG_PCI |
842033e6 | 410 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5e918a98 KP |
411 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
412 | ||
5e918a98 | 413 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 414 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5e918a98 KP |
415 | #endif /* CONFIG_PCI */ |
416 | ||
5e918a98 KP |
417 | /* |
418 | * TSEC | |
419 | */ | |
89c7784e | 420 | #ifdef CONFIG_TSEC_ENET |
5e918a98 | 421 | |
89c7784e TT |
422 | #define CONFIG_GMII /* MII PHY management */ |
423 | ||
424 | #define CONFIG_TSEC1 | |
425 | ||
426 | #ifdef CONFIG_TSEC1 | |
427 | #define CONFIG_HAS_ETH0 | |
5e918a98 | 428 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 429 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
5e918a98 | 430 | #define TSEC1_PHY_ADDR 2 |
5e918a98 | 431 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
5e918a98 | 432 | #define TSEC1_PHYIDX 0 |
89c7784e | 433 | #endif |
5e918a98 | 434 | |
89c7784e TT |
435 | #ifdef CONFIG_TSEC2 |
436 | #define CONFIG_HAS_ETH1 | |
437 | #define CONFIG_TSEC2_NAME "TSEC1" | |
6d0f6bcf | 438 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
439 | #define TSEC2_PHY_ADDR 0x1c |
440 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
441 | #define TSEC2_PHYIDX 0 | |
442 | #endif | |
5e918a98 KP |
443 | |
444 | /* Options are: TSEC[0-1] */ | |
445 | #define CONFIG_ETHPRIME "TSEC0" | |
446 | ||
89c7784e TT |
447 | #endif |
448 | ||
730e7929 KP |
449 | /* |
450 | * SATA | |
451 | */ | |
452 | #define CONFIG_LIBATA | |
453 | #define CONFIG_FSL_SATA | |
454 | ||
6d0f6bcf | 455 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 456 | #define CONFIG_SATA1 |
6d0f6bcf | 457 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
5afe9722 JH |
458 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
459 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 460 | #define CONFIG_SATA2 |
6d0f6bcf | 461 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
5afe9722 JH |
462 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
463 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
464 | |
465 | #ifdef CONFIG_FSL_SATA | |
466 | #define CONFIG_LBA48 | |
467 | #define CONFIG_CMD_SATA | |
468 | #define CONFIG_DOS_PARTITION | |
469 | #define CONFIG_CMD_EXT2 | |
470 | #endif | |
471 | ||
5e918a98 KP |
472 | /* |
473 | * Environment | |
474 | */ | |
6d0f6bcf | 475 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 476 | #define CONFIG_ENV_IS_IN_FLASH 1 |
5afe9722 JH |
477 | #define CONFIG_ENV_ADDR \ |
478 | (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
479 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ |
480 | #define CONFIG_ENV_SIZE 0x4000 | |
5e918a98 | 481 | #else |
5afe9722 | 482 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 483 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 484 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) |
0e8d1586 | 485 | #define CONFIG_ENV_SIZE 0x2000 |
5e918a98 KP |
486 | #endif |
487 | ||
488 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 489 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5e918a98 KP |
490 | |
491 | /* | |
492 | * BOOTP options | |
493 | */ | |
494 | #define CONFIG_BOOTP_BOOTFILESIZE | |
495 | #define CONFIG_BOOTP_BOOTPATH | |
496 | #define CONFIG_BOOTP_GATEWAY | |
497 | #define CONFIG_BOOTP_HOSTNAME | |
498 | ||
499 | ||
500 | /* | |
501 | * Command line configuration. | |
502 | */ | |
503 | #include <config_cmd_default.h> | |
504 | ||
505 | #define CONFIG_CMD_PING | |
506 | #define CONFIG_CMD_I2C | |
507 | #define CONFIG_CMD_MII | |
508 | #define CONFIG_CMD_DATE | |
509 | ||
510 | #if defined(CONFIG_PCI) | |
511 | #define CONFIG_CMD_PCI | |
512 | #endif | |
513 | ||
6d0f6bcf | 514 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 515 | #undef CONFIG_CMD_SAVEENV |
5e918a98 KP |
516 | #undef CONFIG_CMD_LOADS |
517 | #endif | |
518 | ||
519 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
5afe9722 | 520 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
5e918a98 KP |
521 | |
522 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
523 | ||
c9646ed7 AV |
524 | #define CONFIG_MMC 1 |
525 | ||
526 | #ifdef CONFIG_MMC | |
527 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 528 | #define CONFIG_FSL_ESDHC_PIN_MUX |
c9646ed7 AV |
529 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
530 | #define CONFIG_CMD_MMC | |
531 | #define CONFIG_GENERIC_MMC | |
532 | #define CONFIG_CMD_EXT2 | |
533 | #define CONFIG_CMD_FAT | |
534 | #define CONFIG_DOS_PARTITION | |
535 | #endif | |
536 | ||
5e918a98 KP |
537 | /* |
538 | * Miscellaneous configurable options | |
539 | */ | |
5afe9722 JH |
540 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
541 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
5e918a98 KP |
542 | |
543 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 544 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5e918a98 | 545 | #else |
6d0f6bcf | 546 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5e918a98 KP |
547 | #endif |
548 | ||
5afe9722 JH |
549 | /* Print Buffer Size */ |
550 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
551 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
552 | /* Boot Argument Buffer Size */ | |
553 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
5e918a98 KP |
554 | |
555 | /* | |
556 | * For booting Linux, the board info and command line data | |
9f530d59 | 557 | * have to be in the first 256 MB of memory, since this is |
5e918a98 KP |
558 | * the maximum mapped by the Linux kernel during initialization. |
559 | */ | |
5afe9722 | 560 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
5e918a98 KP |
561 | |
562 | /* | |
563 | * Core HID Setup | |
564 | */ | |
1a2e203b | 565 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
5afe9722 JH |
566 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
567 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 568 | #define CONFIG_SYS_HID2 HID2_HBE |
5e918a98 KP |
569 | |
570 | /* | |
571 | * MMU Setup | |
572 | */ | |
573 | ||
31d82672 BB |
574 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
575 | ||
5e918a98 | 576 | /* DDR: cache cacheable */ |
6d0f6bcf JCPV |
577 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
578 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
5e918a98 | 579 | |
5afe9722 | 580 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 581 | | BATL_PP_RW \ |
5afe9722 JH |
582 | | BATL_MEMCOHERENCE) |
583 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
584 | | BATU_BL_256M \ | |
585 | | BATU_VS \ | |
586 | | BATU_VP) | |
6d0f6bcf JCPV |
587 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
588 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5e918a98 | 589 | |
5afe9722 | 590 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 591 | | BATL_PP_RW \ |
5afe9722 JH |
592 | | BATL_MEMCOHERENCE) |
593 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
594 | | BATU_BL_256M \ | |
595 | | BATU_VS \ | |
596 | | BATU_VP) | |
6d0f6bcf JCPV |
597 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
598 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5e918a98 KP |
599 | |
600 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
5afe9722 | 601 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 602 | | BATL_PP_RW \ |
5afe9722 JH |
603 | | BATL_CACHEINHIBIT \ |
604 | | BATL_GUARDEDSTORAGE) | |
605 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
606 | | BATU_BL_8M \ | |
607 | | BATU_VS \ | |
608 | | BATU_VP) | |
6d0f6bcf JCPV |
609 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
610 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5e918a98 KP |
611 | |
612 | /* L2 Switch: cache-inhibit and guarded */ | |
5afe9722 | 613 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ |
72cd4087 | 614 | | BATL_PP_RW \ |
5afe9722 JH |
615 | | BATL_CACHEINHIBIT \ |
616 | | BATL_GUARDEDSTORAGE) | |
617 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ | |
618 | | BATU_BL_128K \ | |
619 | | BATU_VS \ | |
620 | | BATU_VP) | |
6d0f6bcf JCPV |
621 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
622 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
5e918a98 KP |
623 | |
624 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
5afe9722 | 625 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 626 | | BATL_PP_RW \ |
5afe9722 JH |
627 | | BATL_MEMCOHERENCE) |
628 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
629 | | BATU_BL_32M \ | |
630 | | BATU_VS \ | |
631 | | BATU_VP) | |
632 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 633 | | BATL_PP_RW \ |
5afe9722 JH |
634 | | BATL_CACHEINHIBIT \ |
635 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 636 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
5e918a98 KP |
637 | |
638 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 639 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
5afe9722 JH |
640 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
641 | | BATU_BL_128K \ | |
642 | | BATU_VS \ | |
643 | | BATU_VP) | |
6d0f6bcf JCPV |
644 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
645 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5e918a98 KP |
646 | |
647 | #ifdef CONFIG_PCI | |
648 | /* PCI MEM space: cacheable */ | |
5afe9722 | 649 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 650 | | BATL_PP_RW \ |
5afe9722 JH |
651 | | BATL_MEMCOHERENCE) |
652 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
653 | | BATU_BL_256M \ | |
654 | | BATU_VS \ | |
655 | | BATU_VP) | |
6d0f6bcf JCPV |
656 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
657 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5e918a98 | 658 | /* PCI MMIO space: cache-inhibit and guarded */ |
5afe9722 | 659 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 660 | | BATL_PP_RW \ |
5afe9722 JH |
661 | | BATL_CACHEINHIBIT \ |
662 | | BATL_GUARDEDSTORAGE) | |
663 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
664 | | BATU_BL_256M \ | |
665 | | BATU_VS \ | |
666 | | BATU_VP) | |
6d0f6bcf JCPV |
667 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
668 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 | 669 | #else |
6d0f6bcf JCPV |
670 | #define CONFIG_SYS_IBAT6L (0) |
671 | #define CONFIG_SYS_IBAT6U (0) | |
672 | #define CONFIG_SYS_IBAT7L (0) | |
673 | #define CONFIG_SYS_IBAT7U (0) | |
674 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
675 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
676 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
677 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 KP |
678 | #endif |
679 | ||
5e918a98 KP |
680 | #if defined(CONFIG_CMD_KGDB) |
681 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
5e918a98 KP |
682 | #endif |
683 | ||
684 | /* | |
685 | * Environment Configuration | |
686 | */ | |
687 | #define CONFIG_ENV_OVERWRITE | |
688 | ||
18e69a35 | 689 | #define CONFIG_HAS_FSL_DR_USB |
6c3c5750 NB |
690 | #define CONFIG_CMD_USB |
691 | #define CONFIG_USB_STORAGE | |
692 | #define CONFIG_USB_EHCI | |
693 | #define CONFIG_USB_EHCI_FSL | |
694 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
18e69a35 | 695 | |
5afe9722 | 696 | #define CONFIG_NETDEV "eth1" |
5e918a98 KP |
697 | |
698 | #define CONFIG_HOSTNAME mpc837x_rdb | |
8b3637c6 | 699 | #define CONFIG_ROOTPATH "/nfsroot" |
5afe9722 | 700 | #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" |
b3f44c21 | 701 | #define CONFIG_BOOTFILE "uImage" |
5afe9722 JH |
702 | /* U-Boot image on TFTP server */ |
703 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
704 | #define CONFIG_FDTFILE "mpc8379_rdb.dtb" | |
5e918a98 | 705 | |
5afe9722 JH |
706 | /* default location for tftp and bootm */ |
707 | #define CONFIG_LOADADDR 800000 | |
7fd0bea2 | 708 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
5e918a98 KP |
709 | #define CONFIG_BAUDRATE 115200 |
710 | ||
5e918a98 | 711 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5afe9722 JH |
712 | "netdev=" CONFIG_NETDEV "\0" \ |
713 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
5e918a98 | 714 | "tftpflash=tftp $loadaddr $uboot;" \ |
5368c55d MV |
715 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
716 | " +$filesize; " \ | |
717 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
718 | " +$filesize; " \ | |
719 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
720 | " $filesize; " \ | |
721 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
722 | " +$filesize; " \ | |
723 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
724 | " $filesize\0" \ | |
79f516bc | 725 | "fdtaddr=780000\0" \ |
5afe9722 | 726 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
5e918a98 | 727 | "ramdiskaddr=1000000\0" \ |
5afe9722 | 728 | "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ |
5e918a98 KP |
729 | "console=ttyS0\0" \ |
730 | "setbootargs=setenv bootargs " \ | |
731 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
732 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
5afe9722 JH |
733 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
734 | "$netdev:off " \ | |
5e918a98 KP |
735 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
736 | ||
737 | #define CONFIG_NFSBOOTCOMMAND \ | |
738 | "setenv rootdev /dev/nfs;" \ | |
739 | "run setbootargs;" \ | |
740 | "run setipargs;" \ | |
741 | "tftp $loadaddr $bootfile;" \ | |
742 | "tftp $fdtaddr $fdtfile;" \ | |
743 | "bootm $loadaddr - $fdtaddr" | |
744 | ||
745 | #define CONFIG_RAMBOOTCOMMAND \ | |
746 | "setenv rootdev /dev/ram;" \ | |
747 | "run setbootargs;" \ | |
748 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
749 | "tftp $loadaddr $bootfile;" \ | |
750 | "tftp $fdtaddr $fdtfile;" \ | |
751 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
752 | ||
5e918a98 | 753 | #endif /* __CONFIG_H */ |