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5e918a98 KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Kevin Lam <kevin.lam@freescale.com> | |
4 | * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5e918a98 KP |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 16 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
5e918a98 KP |
17 | #define CONFIG_MPC837XERDB 1 |
18 | ||
89c7784e | 19 | #define CONFIG_MISC_INIT_R |
c9646ed7 | 20 | #define CONFIG_HWCONFIG |
89c7784e TT |
21 | |
22 | /* | |
23 | * On-board devices | |
24 | */ | |
25 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ | |
26 | #define CONFIG_VSC7385_ENET | |
27 | ||
5e918a98 KP |
28 | /* |
29 | * System Clock Setup | |
30 | */ | |
31 | #ifdef CONFIG_PCISLAVE | |
32 | #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ | |
33 | #else | |
34 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
be9b56df | 35 | #define CONFIG_PCIE |
5e918a98 KP |
36 | #endif |
37 | ||
38 | #ifndef CONFIG_SYS_CLK_FREQ | |
39 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
40 | #endif | |
41 | ||
42 | /* | |
43 | * Hardware Reset Configuration Word | |
44 | */ | |
6d0f6bcf | 45 | #define CONFIG_SYS_HRCW_LOW (\ |
5e918a98 KP |
46 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
47 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
48 | HRCWL_SVCOD_DIV_2 |\ | |
49 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
50 | HRCWL_CORE_TO_CSB_2X1) | |
51 | ||
52 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 53 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
54 | HRCWH_PCI_AGENT |\ |
55 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
56 | HRCWH_CORE_ENABLE |\ | |
57 | HRCWH_FROM_0XFFF00100 |\ | |
58 | HRCWH_BOOTSEQ_DISABLE |\ | |
59 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
60 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
61 | HRCWH_RL_EXT_LEGACY |\ | |
62 | HRCWH_TSEC1M_IN_RGMII |\ | |
63 | HRCWH_TSEC2M_IN_RGMII |\ | |
64 | HRCWH_BIG_ENDIAN |\ | |
65 | HRCWH_LDP_CLEAR) | |
66 | #else | |
6d0f6bcf | 67 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
68 | HRCWH_PCI_HOST |\ |
69 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
70 | HRCWH_CORE_ENABLE |\ | |
71 | HRCWH_FROM_0X00000100 |\ | |
72 | HRCWH_BOOTSEQ_DISABLE |\ | |
73 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
74 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
75 | HRCWH_RL_EXT_LEGACY |\ | |
76 | HRCWH_TSEC1M_IN_RGMII |\ | |
77 | HRCWH_TSEC2M_IN_RGMII |\ | |
78 | HRCWH_BIG_ENDIAN |\ | |
79 | HRCWH_LDP_CLEAR) | |
80 | #endif | |
81 | ||
6d0f6bcf | 82 | /* System performance - define the value i.e. CONFIG_SYS_XXX |
5e918a98 KP |
83 | */ |
84 | ||
85 | /* Arbiter Configuration Register */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
5afe9722 | 87 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
5e918a98 KP |
88 | |
89 | /* System Priority Control Regsiter */ | |
5afe9722 | 90 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ |
5e918a98 KP |
91 | |
92 | /* System Clock Configuration Register */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ |
94 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ | |
5afe9722 | 95 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ |
5e918a98 KP |
96 | |
97 | /* | |
98 | * System IO Config | |
99 | */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_SICRH 0x08200000 |
101 | #define CONFIG_SYS_SICRL 0x00000000 | |
5e918a98 KP |
102 | |
103 | /* | |
104 | * Output Buffer Impedance | |
105 | */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_OBIR 0x30100000 |
5e918a98 KP |
107 | |
108 | /* | |
109 | * IMMR new address | |
110 | */ | |
6d0f6bcf | 111 | #define CONFIG_SYS_IMMR 0xE0000000 |
5e918a98 | 112 | |
89c7784e TT |
113 | /* |
114 | * Device configurations | |
115 | */ | |
116 | ||
117 | /* Vitesse 7385 */ | |
118 | ||
119 | #ifdef CONFIG_VSC7385_ENET | |
120 | ||
121 | #define CONFIG_TSEC2 | |
122 | ||
123 | /* The flash address and size of the VSC7385 firmware image */ | |
124 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
125 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
126 | ||
127 | #endif | |
128 | ||
5e918a98 KP |
129 | /* |
130 | * DDR Setup | |
131 | */ | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
133 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
134 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
135 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 | |
136 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
5e918a98 | 137 | |
6d0f6bcf | 138 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) |
5e918a98 KP |
139 | |
140 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
141 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
142 | ||
143 | #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
144 | ||
145 | /* | |
146 | * Manually set up DDR parameters | |
147 | */ | |
6d0f6bcf | 148 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 JH |
149 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
150 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
151 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
152 | | CSCONFIG_ROW_BIT_13 \ | |
153 | | CSCONFIG_COL_BIT_10) | |
5e918a98 | 154 | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
156 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
5e918a98 KP |
157 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
158 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
159 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
160 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
161 | | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
162 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
163 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
5e918a98 | 164 | /* 0x00260802 */ /* DDR400 */ |
6d0f6bcf | 165 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
5e918a98 KP |
166 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
167 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
168 | | (7 << TIMING_CFG1_CASLAT_SHIFT) \ | |
169 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
170 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
171 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
172 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
5e918a98 | 173 | /* 0x3937d322 */ |
2fef4020 JH |
174 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
175 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
176 | | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
177 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
178 | | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
179 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
180 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
181 | /* 0x02984cc8 */ | |
5e918a98 | 182 | |
8eceeb7f KP |
183 | #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
184 | | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
5e918a98 KP |
185 | /* 0x06090100 */ |
186 | ||
187 | #if defined(CONFIG_DDR_2T_TIMING) | |
5afe9722 | 188 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 JH |
189 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
190 | | SDRAM_CFG_32_BE \ | |
191 | | SDRAM_CFG_2T_EN) | |
192 | /* 0x43088000 */ | |
5e918a98 | 193 | #else |
5afe9722 | 194 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 | 195 | | SDRAM_CFG_SDRAM_TYPE_DDR2) |
5afe9722 | 196 | /* 0x43000000 */ |
5e918a98 | 197 | #endif |
6d0f6bcf | 198 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |
8eceeb7f | 199 | #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ |
5afe9722 JH |
200 | | (0x0442 << SDRAM_MODE_SD_SHIFT)) |
201 | /* 0x04400442 */ /* DDR400 */ | |
6d0f6bcf | 202 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
5e918a98 KP |
203 | |
204 | /* | |
205 | * Memory test | |
206 | */ | |
6d0f6bcf JCPV |
207 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
208 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
209 | #define CONFIG_SYS_MEMTEST_END 0x0ef70010 | |
5e918a98 KP |
210 | |
211 | /* | |
212 | * The reserved memory | |
213 | */ | |
14d0a02a | 214 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5e918a98 | 215 | |
6d0f6bcf JCPV |
216 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
217 | #define CONFIG_SYS_RAMBOOT | |
5e918a98 | 218 | #else |
6d0f6bcf | 219 | #undef CONFIG_SYS_RAMBOOT |
5e918a98 KP |
220 | #endif |
221 | ||
16c8c170 | 222 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
5afe9722 | 223 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
5e918a98 KP |
224 | |
225 | /* | |
226 | * Initial RAM Base Address Setup | |
227 | */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
229 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 230 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
5afe9722 JH |
231 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
232 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
5e918a98 KP |
233 | |
234 | /* | |
235 | * Local Bus Configuration & Clock Setup | |
236 | */ | |
c7190f02 KP |
237 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
238 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 239 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 240 | #define CONFIG_FSL_ELBC 1 |
5e918a98 KP |
241 | |
242 | /* | |
243 | * FLASH on the Local Bus | |
244 | */ | |
6d0f6bcf | 245 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 246 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
248 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ | |
5e918a98 | 249 | |
5afe9722 JH |
250 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
251 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
252 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
5e918a98 | 253 | |
5afe9722 JH |
254 | /* Window base at flash base */ |
255 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
6d0f6bcf | 256 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ |
5e918a98 | 257 | |
5afe9722 | 258 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
259 | | BR_PS_16 /* 16 bit port */ \ |
260 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
261 | | BR_V) /* valid */ | |
262 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
5e918a98 KP |
263 | | OR_GPCM_XACS \ |
264 | | OR_GPCM_SCY_9 \ | |
7d6a0982 | 265 | | OR_GPCM_EHTR_SET \ |
5e918a98 | 266 | | OR_GPCM_EAD) |
7d6a0982 | 267 | /* 0xFF800191 */ |
5e918a98 | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
270 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5e918a98 | 271 | |
6d0f6bcf JCPV |
272 | #undef CONFIG_SYS_FLASH_CHECKSUM |
273 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
274 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5e918a98 | 275 | |
46a3aeea AV |
276 | /* |
277 | * NAND Flash on the Local Bus | |
278 | */ | |
7d6a0982 | 279 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
5afe9722 | 280 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 JH |
281 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
282 | | BR_PS_8 /* 8 bit port */ \ | |
283 | | BR_MS_FCM /* MSEL = FCM */ \ | |
5afe9722 | 284 | | BR_V) /* valid */ |
7d6a0982 | 285 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
5afe9722 JH |
286 | | OR_FCM_CSCT \ |
287 | | OR_FCM_CST \ | |
288 | | OR_FCM_CHT \ | |
289 | | OR_FCM_SCY_1 \ | |
290 | | OR_FCM_TRLX \ | |
291 | | OR_FCM_EHTR) | |
6d0f6bcf | 292 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 293 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
46a3aeea | 294 | |
89c7784e TT |
295 | /* Vitesse 7385 */ |
296 | ||
6d0f6bcf | 297 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
5e918a98 | 298 | |
89c7784e TT |
299 | #ifdef CONFIG_VSC7385_ENET |
300 | ||
7d6a0982 JH |
301 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
302 | | BR_PS_8 \ | |
303 | | BR_MS_GPCM \ | |
304 | | BR_V) | |
305 | /* 0xF0000801 */ | |
306 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | |
307 | | OR_GPCM_CSNT \ | |
308 | | OR_GPCM_XACS \ | |
309 | | OR_GPCM_SCY_15 \ | |
310 | | OR_GPCM_SETA \ | |
311 | | OR_GPCM_TRLX_SET \ | |
312 | | OR_GPCM_EHTR_SET \ | |
313 | | OR_GPCM_EAD) | |
314 | /* 0xfffe09ff */ | |
315 | ||
5afe9722 JH |
316 | /* Access Base */ |
317 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 318 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
5e918a98 | 319 | |
89c7784e TT |
320 | #endif |
321 | ||
5e918a98 KP |
322 | /* |
323 | * Serial Port | |
324 | */ | |
325 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_NS16550_SERIAL |
327 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
328 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5e918a98 | 329 | |
6d0f6bcf | 330 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5afe9722 | 331 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
5e918a98 | 332 | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
334 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5e918a98 | 335 | |
2bd7460e AV |
336 | /* SERDES */ |
337 | #define CONFIG_FSL_SERDES | |
338 | #define CONFIG_FSL_SERDES1 0xe3000 | |
339 | #define CONFIG_FSL_SERDES2 0xe3100 | |
340 | ||
5e918a98 | 341 | /* I2C */ |
00f792e0 HS |
342 | #define CONFIG_SYS_I2C |
343 | #define CONFIG_SYS_I2C_FSL | |
344 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
345 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
346 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
347 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
5e918a98 KP |
348 | |
349 | /* | |
350 | * Config on-board RTC | |
351 | */ | |
352 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5e918a98 KP |
354 | |
355 | /* | |
356 | * General PCI | |
357 | * Addresses are mapped 1-1. | |
358 | */ | |
5afe9722 JH |
359 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
360 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
361 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
363 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
364 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
365 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
366 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
367 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
368 | ||
369 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
370 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
371 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5e918a98 | 372 | |
7e915580 AV |
373 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
374 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
375 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
376 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
377 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
378 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
379 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
380 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
381 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
382 | ||
383 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
384 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
385 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
386 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
387 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
388 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
389 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
390 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
391 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
392 | ||
5e918a98 | 393 | #ifdef CONFIG_PCI |
842033e6 | 394 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5e918a98 | 395 | |
5e918a98 | 396 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 397 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5e918a98 KP |
398 | #endif /* CONFIG_PCI */ |
399 | ||
5e918a98 KP |
400 | /* |
401 | * TSEC | |
402 | */ | |
89c7784e | 403 | #ifdef CONFIG_TSEC_ENET |
5e918a98 | 404 | |
89c7784e TT |
405 | #define CONFIG_GMII /* MII PHY management */ |
406 | ||
407 | #define CONFIG_TSEC1 | |
408 | ||
409 | #ifdef CONFIG_TSEC1 | |
410 | #define CONFIG_HAS_ETH0 | |
5e918a98 | 411 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 412 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
5e918a98 | 413 | #define TSEC1_PHY_ADDR 2 |
5e918a98 | 414 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
5e918a98 | 415 | #define TSEC1_PHYIDX 0 |
89c7784e | 416 | #endif |
5e918a98 | 417 | |
89c7784e TT |
418 | #ifdef CONFIG_TSEC2 |
419 | #define CONFIG_HAS_ETH1 | |
420 | #define CONFIG_TSEC2_NAME "TSEC1" | |
6d0f6bcf | 421 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
422 | #define TSEC2_PHY_ADDR 0x1c |
423 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
424 | #define TSEC2_PHYIDX 0 | |
425 | #endif | |
5e918a98 KP |
426 | |
427 | /* Options are: TSEC[0-1] */ | |
428 | #define CONFIG_ETHPRIME "TSEC0" | |
429 | ||
89c7784e TT |
430 | #endif |
431 | ||
730e7929 KP |
432 | /* |
433 | * SATA | |
434 | */ | |
6d0f6bcf | 435 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 436 | #define CONFIG_SATA1 |
6d0f6bcf | 437 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
5afe9722 JH |
438 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
439 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 440 | #define CONFIG_SATA2 |
6d0f6bcf | 441 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
5afe9722 JH |
442 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
443 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
444 | |
445 | #ifdef CONFIG_FSL_SATA | |
446 | #define CONFIG_LBA48 | |
730e7929 KP |
447 | #endif |
448 | ||
5e918a98 KP |
449 | /* |
450 | * Environment | |
451 | */ | |
6d0f6bcf | 452 | #ifndef CONFIG_SYS_RAMBOOT |
5afe9722 JH |
453 | #define CONFIG_ENV_ADDR \ |
454 | (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
455 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ |
456 | #define CONFIG_ENV_SIZE 0x4000 | |
5e918a98 | 457 | #else |
6d0f6bcf | 458 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) |
0e8d1586 | 459 | #define CONFIG_ENV_SIZE 0x2000 |
5e918a98 KP |
460 | #endif |
461 | ||
462 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 463 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5e918a98 KP |
464 | |
465 | /* | |
466 | * BOOTP options | |
467 | */ | |
468 | #define CONFIG_BOOTP_BOOTFILESIZE | |
5e918a98 | 469 | |
5e918a98 KP |
470 | /* |
471 | * Command line configuration. | |
472 | */ | |
5e918a98 | 473 | |
5e918a98 KP |
474 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
475 | ||
c9646ed7 AV |
476 | #ifdef CONFIG_MMC |
477 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 478 | #define CONFIG_FSL_ESDHC_PIN_MUX |
c9646ed7 | 479 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
c9646ed7 AV |
480 | #endif |
481 | ||
5e918a98 KP |
482 | /* |
483 | * Miscellaneous configurable options | |
484 | */ | |
5afe9722 | 485 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
5e918a98 | 486 | |
5e918a98 KP |
487 | /* |
488 | * For booting Linux, the board info and command line data | |
9f530d59 | 489 | * have to be in the first 256 MB of memory, since this is |
5e918a98 KP |
490 | * the maximum mapped by the Linux kernel during initialization. |
491 | */ | |
5afe9722 | 492 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
63865278 | 493 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
5e918a98 KP |
494 | |
495 | /* | |
496 | * Core HID Setup | |
497 | */ | |
1a2e203b | 498 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
5afe9722 JH |
499 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
500 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 501 | #define CONFIG_SYS_HID2 HID2_HBE |
5e918a98 KP |
502 | |
503 | /* | |
504 | * MMU Setup | |
505 | */ | |
506 | ||
31d82672 BB |
507 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
508 | ||
5e918a98 | 509 | /* DDR: cache cacheable */ |
6d0f6bcf JCPV |
510 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
511 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
5e918a98 | 512 | |
5afe9722 | 513 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 514 | | BATL_PP_RW \ |
5afe9722 JH |
515 | | BATL_MEMCOHERENCE) |
516 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
517 | | BATU_BL_256M \ | |
518 | | BATU_VS \ | |
519 | | BATU_VP) | |
6d0f6bcf JCPV |
520 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
521 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5e918a98 | 522 | |
5afe9722 | 523 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 524 | | BATL_PP_RW \ |
5afe9722 JH |
525 | | BATL_MEMCOHERENCE) |
526 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
527 | | BATU_BL_256M \ | |
528 | | BATU_VS \ | |
529 | | BATU_VP) | |
6d0f6bcf JCPV |
530 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
531 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5e918a98 KP |
532 | |
533 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
5afe9722 | 534 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 535 | | BATL_PP_RW \ |
5afe9722 JH |
536 | | BATL_CACHEINHIBIT \ |
537 | | BATL_GUARDEDSTORAGE) | |
538 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
539 | | BATU_BL_8M \ | |
540 | | BATU_VS \ | |
541 | | BATU_VP) | |
6d0f6bcf JCPV |
542 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
543 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5e918a98 KP |
544 | |
545 | /* L2 Switch: cache-inhibit and guarded */ | |
5afe9722 | 546 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ |
72cd4087 | 547 | | BATL_PP_RW \ |
5afe9722 JH |
548 | | BATL_CACHEINHIBIT \ |
549 | | BATL_GUARDEDSTORAGE) | |
550 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ | |
551 | | BATU_BL_128K \ | |
552 | | BATU_VS \ | |
553 | | BATU_VP) | |
6d0f6bcf JCPV |
554 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
555 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
5e918a98 KP |
556 | |
557 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
5afe9722 | 558 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 559 | | BATL_PP_RW \ |
5afe9722 JH |
560 | | BATL_MEMCOHERENCE) |
561 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
562 | | BATU_BL_32M \ | |
563 | | BATU_VS \ | |
564 | | BATU_VP) | |
565 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 566 | | BATL_PP_RW \ |
5afe9722 JH |
567 | | BATL_CACHEINHIBIT \ |
568 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 569 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
5e918a98 KP |
570 | |
571 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 572 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
5afe9722 JH |
573 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
574 | | BATU_BL_128K \ | |
575 | | BATU_VS \ | |
576 | | BATU_VP) | |
6d0f6bcf JCPV |
577 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
578 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5e918a98 KP |
579 | |
580 | #ifdef CONFIG_PCI | |
581 | /* PCI MEM space: cacheable */ | |
5afe9722 | 582 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 583 | | BATL_PP_RW \ |
5afe9722 JH |
584 | | BATL_MEMCOHERENCE) |
585 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
586 | | BATU_BL_256M \ | |
587 | | BATU_VS \ | |
588 | | BATU_VP) | |
6d0f6bcf JCPV |
589 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
590 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5e918a98 | 591 | /* PCI MMIO space: cache-inhibit and guarded */ |
5afe9722 | 592 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 593 | | BATL_PP_RW \ |
5afe9722 JH |
594 | | BATL_CACHEINHIBIT \ |
595 | | BATL_GUARDEDSTORAGE) | |
596 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
597 | | BATU_BL_256M \ | |
598 | | BATU_VS \ | |
599 | | BATU_VP) | |
6d0f6bcf JCPV |
600 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
601 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 | 602 | #else |
6d0f6bcf JCPV |
603 | #define CONFIG_SYS_IBAT6L (0) |
604 | #define CONFIG_SYS_IBAT6U (0) | |
605 | #define CONFIG_SYS_IBAT7L (0) | |
606 | #define CONFIG_SYS_IBAT7U (0) | |
607 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
608 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
609 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
610 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 KP |
611 | #endif |
612 | ||
5e918a98 KP |
613 | #if defined(CONFIG_CMD_KGDB) |
614 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
5e918a98 KP |
615 | #endif |
616 | ||
617 | /* | |
618 | * Environment Configuration | |
619 | */ | |
620 | #define CONFIG_ENV_OVERWRITE | |
621 | ||
18e69a35 | 622 | #define CONFIG_HAS_FSL_DR_USB |
6c3c5750 NB |
623 | #define CONFIG_USB_EHCI_FSL |
624 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
18e69a35 | 625 | |
5afe9722 | 626 | #define CONFIG_NETDEV "eth1" |
5e918a98 KP |
627 | |
628 | #define CONFIG_HOSTNAME mpc837x_rdb | |
8b3637c6 | 629 | #define CONFIG_ROOTPATH "/nfsroot" |
5afe9722 | 630 | #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" |
b3f44c21 | 631 | #define CONFIG_BOOTFILE "uImage" |
5afe9722 JH |
632 | /* U-Boot image on TFTP server */ |
633 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
634 | #define CONFIG_FDTFILE "mpc8379_rdb.dtb" | |
5e918a98 | 635 | |
5afe9722 JH |
636 | /* default location for tftp and bootm */ |
637 | #define CONFIG_LOADADDR 800000 | |
5e918a98 | 638 | |
5e918a98 | 639 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5afe9722 JH |
640 | "netdev=" CONFIG_NETDEV "\0" \ |
641 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
5e918a98 | 642 | "tftpflash=tftp $loadaddr $uboot;" \ |
5368c55d MV |
643 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
644 | " +$filesize; " \ | |
645 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
646 | " +$filesize; " \ | |
647 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
648 | " $filesize; " \ | |
649 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
650 | " +$filesize; " \ | |
651 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
652 | " $filesize\0" \ | |
79f516bc | 653 | "fdtaddr=780000\0" \ |
5afe9722 | 654 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
5e918a98 | 655 | "ramdiskaddr=1000000\0" \ |
5afe9722 | 656 | "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ |
5e918a98 KP |
657 | "console=ttyS0\0" \ |
658 | "setbootargs=setenv bootargs " \ | |
659 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
660 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
5afe9722 JH |
661 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
662 | "$netdev:off " \ | |
5e918a98 KP |
663 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
664 | ||
665 | #define CONFIG_NFSBOOTCOMMAND \ | |
666 | "setenv rootdev /dev/nfs;" \ | |
667 | "run setbootargs;" \ | |
668 | "run setipargs;" \ | |
669 | "tftp $loadaddr $bootfile;" \ | |
670 | "tftp $fdtaddr $fdtfile;" \ | |
671 | "bootm $loadaddr - $fdtaddr" | |
672 | ||
673 | #define CONFIG_RAMBOOTCOMMAND \ | |
674 | "setenv rootdev /dev/ram;" \ | |
675 | "run setbootargs;" \ | |
676 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
677 | "tftp $loadaddr $bootfile;" \ | |
678 | "tftp $fdtaddr $fdtfile;" \ | |
679 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
680 | ||
5e918a98 | 681 | #endif /* __CONFIG_H */ |