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9490a7f1 | 1 | /* |
3d7506fa | 2 | * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. |
9490a7f1 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
9490a7f1 KG |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8536ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
15672c6d | 14 | #define CONFIG_DISPLAY_BOARDINFO |
c7e1a43d KG |
15 | #include "../board/freescale/common/ics307_clk.h" |
16 | ||
d24f2d32 | 17 | #ifdef CONFIG_36BIT |
337f9fde KG |
18 | #define CONFIG_PHYS_64BIT 1 |
19 | #endif | |
20 | ||
d24f2d32 | 21 | #ifdef CONFIG_SDCARD |
e40ac487 | 22 | #define CONFIG_RAMBOOT_SDCARD 1 |
e2c9bc5e | 23 | #define CONFIG_SYS_TEXT_BASE 0xf8f40000 |
7a577fda | 24 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
e40ac487 MH |
25 | #endif |
26 | ||
d24f2d32 | 27 | #ifdef CONFIG_SPIFLASH |
e40ac487 | 28 | #define CONFIG_RAMBOOT_SPIFLASH 1 |
e2c9bc5e | 29 | #define CONFIG_SYS_TEXT_BASE 0xf8f40000 |
7a577fda | 30 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
2ae18241 WD |
31 | #endif |
32 | ||
33 | #ifndef CONFIG_SYS_TEXT_BASE | |
c6e8f49a | 34 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
e40ac487 MH |
35 | #endif |
36 | ||
7a577fda KG |
37 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
38 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
39 | #endif | |
40 | ||
96196a1f HW |
41 | #ifndef CONFIG_SYS_MONITOR_BASE |
42 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
43 | #endif | |
44 | ||
9490a7f1 KG |
45 | /* High Level Configuration Options */ |
46 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
47 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
9490a7f1 KG |
48 | #define CONFIG_MPC8536 1 |
49 | #define CONFIG_MPC8536DS 1 | |
50 | ||
c51fc5d5 | 51 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
9490a7f1 KG |
52 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
53 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ | |
54 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
55 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
56 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
57 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 58 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
9490a7f1 | 59 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 60 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
9490a7f1 KG |
61 | |
62 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
63 | ||
64 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
65 | #define CONFIG_ENV_OVERWRITE | |
66 | ||
c7e1a43d KG |
67 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
68 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
9490a7f1 | 69 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
9490a7f1 KG |
70 | |
71 | /* | |
72 | * These can be toggled for performance analysis, otherwise use default. | |
73 | */ | |
74 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
75 | #define CONFIG_BTB /* toggle branch predition */ | |
9490a7f1 | 76 | |
80522dc8 AF |
77 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
78 | ||
9490a7f1 KG |
79 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
80 | ||
337f9fde KG |
81 | #ifdef CONFIG_PHYS_64BIT |
82 | #define CONFIG_ADDR_MAP 1 | |
83 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
84 | #endif | |
85 | ||
07355700 MH |
86 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ |
87 | #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ | |
9490a7f1 KG |
88 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
89 | ||
9a1a0aed MH |
90 | /* |
91 | * Config the L2 Cache as L2 SRAM | |
92 | */ | |
93 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
94 | #ifdef CONFIG_PHYS_64BIT | |
95 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
96 | #else | |
97 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
98 | #endif | |
99 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
100 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
101 | ||
e46fedfe TT |
102 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
103 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
9490a7f1 | 104 | |
8d22ddca | 105 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 106 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
9a1a0aed MH |
107 | #endif |
108 | ||
9490a7f1 | 109 | /* DDR Setup */ |
337f9fde | 110 | #define CONFIG_VERY_BIG_RAM |
5614e71b | 111 | #define CONFIG_SYS_FSL_DDR2 |
9490a7f1 KG |
112 | #undef CONFIG_FSL_DDR_INTERACTIVE |
113 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
114 | #define CONFIG_DDR_SPD | |
9490a7f1 | 115 | |
9b0ad1b1 | 116 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
9490a7f1 KG |
117 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
118 | ||
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
120 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9490a7f1 KG |
121 | |
122 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
123 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
124 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
125 | ||
126 | /* I2C addresses of SPD EEPROMs */ | |
127 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
9490a7f1 KG |
129 | |
130 | /* These are used when DDR doesn't use SPD. */ | |
07355700 | 131 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
6d0f6bcf | 132 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
07355700 | 133 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
135 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
136 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
137 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
138 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
139 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
140 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
141 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
142 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
143 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
144 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
07355700 | 145 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
147 | ||
148 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
149 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
150 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
9490a7f1 | 151 | |
9490a7f1 KG |
152 | /* Make sure required options are set */ |
153 | #ifndef CONFIG_SPD_EEPROM | |
154 | #error ("CONFIG_SPD_EEPROM is required") | |
155 | #endif | |
156 | ||
157 | #undef CONFIG_CLOCKS_IN_MHZ | |
158 | ||
159 | ||
160 | /* | |
161 | * Memory map -- xxx -this is wrong, needs updating | |
162 | * | |
163 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
164 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
165 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
166 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
167 | * | |
168 | * Localbus cacheable (TBD) | |
169 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
170 | * | |
171 | * Localbus non-cacheable | |
c57fc289 | 172 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
9490a7f1 | 173 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
c57fc289 | 174 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
9490a7f1 KG |
175 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
176 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
177 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
178 | */ | |
179 | ||
180 | /* | |
181 | * Local Bus Definitions | |
182 | */ | |
6d0f6bcf | 183 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
337f9fde KG |
184 | #ifdef CONFIG_PHYS_64BIT |
185 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
186 | #else | |
c953ddfd | 187 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
337f9fde | 188 | #endif |
9490a7f1 | 189 | |
9a1a0aed | 190 | #define CONFIG_FLASH_BR_PRELIM \ |
7ee41107 | 191 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
9a1a0aed | 192 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
9490a7f1 | 193 | |
07355700 MH |
194 | #define CONFIG_SYS_BR1_PRELIM \ |
195 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
196 | | BR_PS_16 | BR_V) | |
c953ddfd | 197 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
9490a7f1 | 198 | |
07355700 MH |
199 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ |
200 | CONFIG_SYS_FLASH_BASE_PHYS } | |
6d0f6bcf | 201 | #define CONFIG_SYS_FLASH_QUIET_TEST |
9490a7f1 KG |
202 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
203 | ||
07355700 MH |
204 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
205 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
6d0f6bcf | 206 | #undef CONFIG_SYS_FLASH_CHECKSUM |
07355700 MH |
207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
9490a7f1 | 209 | |
0234446f | 210 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
9a1a0aed | 211 | #define CONFIG_SYS_RAMBOOT |
a55bb834 | 212 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
9a1a0aed MH |
213 | #else |
214 | #undef CONFIG_SYS_RAMBOOT | |
215 | #endif | |
216 | ||
9490a7f1 | 217 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_FLASH_CFI |
219 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
220 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
9490a7f1 KG |
221 | |
222 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
223 | ||
68d4230c | 224 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
9490a7f1 KG |
225 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
226 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
337f9fde KG |
227 | #ifdef CONFIG_PHYS_64BIT |
228 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
229 | #else | |
52b565f5 | 230 | #define PIXIS_BASE_PHYS PIXIS_BASE |
337f9fde | 231 | #endif |
9490a7f1 | 232 | |
52b565f5 | 233 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
07355700 | 234 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
9490a7f1 KG |
235 | |
236 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
237 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
238 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
239 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
240 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
241 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
242 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
243 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
244 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
245 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
246 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
247 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
248 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
249 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
250 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
251 | #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ |
252 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
253 | #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ | |
254 | #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ | |
255 | #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ | |
256 | #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ | |
257 | #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ | |
9490a7f1 KG |
258 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
259 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
260 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
261 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ | |
262 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ | |
263 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ | |
264 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ | |
265 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ | |
266 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ | |
267 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
268 | #define PIXIS_LED 0x25 /* LED Register */ | |
269 | ||
9a1a0aed MH |
270 | #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ |
271 | ||
9490a7f1 KG |
272 | /* old pixis referenced names */ |
273 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
274 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
509e19ca | 275 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e |
9490a7f1 | 276 | |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
278 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
553f0982 | 279 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
9490a7f1 | 280 | |
07355700 | 281 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 282 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 283 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9490a7f1 | 284 | |
07355700 MH |
285 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
286 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
9490a7f1 | 287 | |
9a1a0aed | 288 | #ifndef CONFIG_NAND_SPL |
337f9fde KG |
289 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
290 | #ifdef CONFIG_PHYS_64BIT | |
291 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
292 | #else | |
293 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
294 | #endif | |
9a1a0aed MH |
295 | #else |
296 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
297 | #ifdef CONFIG_PHYS_64BIT | |
298 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
299 | #else | |
300 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
301 | #endif | |
302 | #endif | |
c57fc289 JJ |
303 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
304 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
305 | CONFIG_SYS_NAND_BASE + 0x80000, \ | |
306 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
307 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
c57fc289 JJ |
308 | #define CONFIG_CMD_NAND 1 |
309 | #define CONFIG_NAND_FSL_ELBC 1 | |
310 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
311 | ||
9a1a0aed MH |
312 | /* NAND boot: 4K NAND loader config */ |
313 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
c6e8f49a | 314 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
9a1a0aed MH |
315 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
316 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
317 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
318 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
319 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
320 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
321 | ||
c57fc289 | 322 | /* NAND flash config */ |
a3055c58 | 323 | #define CONFIG_SYS_NAND_BR_PRELIM \ |
07355700 MH |
324 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
325 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
326 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
327 | | BR_MS_FCM /* MSEL = FCM */ \ | |
328 | | BR_V) /* valid */ | |
a3055c58 | 329 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
07355700 MH |
330 | | OR_FCM_PGS /* Large Page*/ \ |
331 | | OR_FCM_CSCT \ | |
332 | | OR_FCM_CST \ | |
333 | | OR_FCM_CHT \ | |
334 | | OR_FCM_SCY_1 \ | |
335 | | OR_FCM_TRLX \ | |
336 | | OR_FCM_EHTR) | |
337 | ||
9a1a0aed MH |
338 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
339 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
340 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
341 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
07355700 MH |
342 | |
343 | #define CONFIG_SYS_BR4_PRELIM \ | |
7ee41107 | 344 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
07355700 MH |
345 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
346 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
347 | | BR_MS_FCM /* MSEL = FCM */ \ | |
348 | | BR_V) /* valid */ | |
a3055c58 | 349 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
07355700 | 350 | #define CONFIG_SYS_BR5_PRELIM \ |
7ee41107 | 351 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ |
07355700 MH |
352 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
353 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
354 | | BR_MS_FCM /* MSEL = FCM */ \ | |
355 | | BR_V) /* valid */ | |
a3055c58 | 356 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
07355700 MH |
357 | |
358 | #define CONFIG_SYS_BR6_PRELIM \ | |
7ee41107 | 359 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ |
07355700 MH |
360 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
361 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
362 | | BR_MS_FCM /* MSEL = FCM */ \ | |
363 | | BR_V) /* valid */ | |
a3055c58 | 364 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
c57fc289 | 365 | |
9490a7f1 KG |
366 | /* Serial Port - controlled on board with jumper J8 |
367 | * open - index 2 | |
368 | * shorted - index 1 | |
369 | */ | |
370 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_NS16550_SERIAL |
372 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
373 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
93341909 KG |
374 | #ifdef CONFIG_NAND_SPL |
375 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
376 | #endif | |
9490a7f1 | 377 | |
6d0f6bcf | 378 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9490a7f1 KG |
379 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
380 | ||
07355700 MH |
381 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) |
382 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
9490a7f1 KG |
383 | |
384 | /* Use the HUSH parser */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_HUSH_PARSER |
9490a7f1 KG |
386 | |
387 | /* | |
388 | * Pass open firmware flat tree | |
389 | */ | |
9490a7f1 KG |
390 | #define CONFIG_OF_BOARD_SETUP 1 |
391 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
392 | ||
9490a7f1 KG |
393 | /* |
394 | * I2C | |
395 | */ | |
00f792e0 HS |
396 | #define CONFIG_SYS_I2C |
397 | #define CONFIG_SYS_I2C_FSL | |
398 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
399 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
400 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
401 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
402 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
403 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
404 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
9490a7f1 KG |
405 | |
406 | /* | |
407 | * I2C2 EEPROM | |
408 | */ | |
32628c50 JCPV |
409 | #define CONFIG_ID_EEPROM |
410 | #ifdef CONFIG_ID_EEPROM | |
6d0f6bcf | 411 | #define CONFIG_SYS_I2C_EEPROM_NXID |
9490a7f1 | 412 | #endif |
6d0f6bcf JCPV |
413 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
414 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
415 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
9490a7f1 | 416 | |
ae2044d8 XX |
417 | /* |
418 | * eSPI - Enhanced SPI | |
419 | */ | |
420 | #define CONFIG_HARD_SPI | |
ae2044d8 XX |
421 | |
422 | #if defined(CONFIG_SPI_FLASH) | |
ae2044d8 XX |
423 | #define CONFIG_CMD_SF |
424 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
425 | #define CONFIG_SF_DEFAULT_MODE 0 | |
426 | #endif | |
427 | ||
9490a7f1 KG |
428 | /* |
429 | * General PCI | |
430 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
431 | */ | |
432 | ||
5af0fdd8 | 433 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
337f9fde KG |
434 | #ifdef CONFIG_PHYS_64BIT |
435 | #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 | |
436 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
437 | #else | |
5af0fdd8 KG |
438 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
439 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
337f9fde | 440 | #endif |
6d0f6bcf | 441 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
337f9fde KG |
442 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
443 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
444 | #ifdef CONFIG_PHYS_64BIT | |
445 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull | |
446 | #else | |
447 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 | |
448 | #endif | |
449 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
9490a7f1 KG |
450 | |
451 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
5f7b31b0 | 452 | #define CONFIG_SYS_PCIE1_NAME "Slot 1" |
5af0fdd8 | 453 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 |
337f9fde KG |
454 | #ifdef CONFIG_PHYS_64BIT |
455 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 | |
456 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull | |
457 | #else | |
10795f42 | 458 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
5af0fdd8 | 459 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 |
337f9fde | 460 | #endif |
6d0f6bcf | 461 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
aca5f018 | 462 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 |
337f9fde KG |
463 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
464 | #ifdef CONFIG_PHYS_64BIT | |
465 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull | |
466 | #else | |
6d0f6bcf | 467 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
337f9fde | 468 | #endif |
6d0f6bcf | 469 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
9490a7f1 KG |
470 | |
471 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
5f7b31b0 | 472 | #define CONFIG_SYS_PCIE2_NAME "Slot 2" |
5af0fdd8 | 473 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 |
337f9fde KG |
474 | #ifdef CONFIG_PHYS_64BIT |
475 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 | |
476 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull | |
477 | #else | |
10795f42 | 478 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
5af0fdd8 | 479 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 |
337f9fde | 480 | #endif |
6d0f6bcf | 481 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
aca5f018 | 482 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 |
337f9fde KG |
483 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
484 | #ifdef CONFIG_PHYS_64BIT | |
485 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull | |
486 | #else | |
6d0f6bcf | 487 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
337f9fde | 488 | #endif |
6d0f6bcf | 489 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
9490a7f1 KG |
490 | |
491 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ | |
5f7b31b0 | 492 | #define CONFIG_SYS_PCIE3_NAME "Slot 3" |
5af0fdd8 | 493 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
337f9fde KG |
494 | #ifdef CONFIG_PHYS_64BIT |
495 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
496 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
497 | #else | |
10795f42 | 498 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
5af0fdd8 | 499 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
337f9fde | 500 | #endif |
6d0f6bcf | 501 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 502 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 |
337f9fde KG |
503 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
504 | #ifdef CONFIG_PHYS_64BIT | |
505 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull | |
506 | #else | |
6d0f6bcf | 507 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
337f9fde | 508 | #endif |
6d0f6bcf | 509 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
9490a7f1 KG |
510 | |
511 | #if defined(CONFIG_PCI) | |
512 | ||
9490a7f1 KG |
513 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
514 | ||
515 | /*PCIE video card used*/ | |
aca5f018 | 516 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT |
9490a7f1 KG |
517 | |
518 | /*PCI video card used*/ | |
aca5f018 | 519 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
9490a7f1 KG |
520 | |
521 | /* video */ | |
522 | #define CONFIG_VIDEO | |
523 | ||
524 | #if defined(CONFIG_VIDEO) | |
525 | #define CONFIG_BIOSEMU | |
526 | #define CONFIG_CFB_CONSOLE | |
527 | #define CONFIG_VIDEO_SW_CURSOR | |
528 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
529 | #define CONFIG_ATI_RADEON_FB | |
530 | #define CONFIG_VIDEO_LOGO | |
aca5f018 | 531 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT |
9490a7f1 KG |
532 | #endif |
533 | ||
534 | #undef CONFIG_EEPRO100 | |
535 | #undef CONFIG_TULIP | |
536 | #undef CONFIG_RTL8139 | |
537 | ||
9490a7f1 | 538 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
539 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
540 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
9490a7f1 KG |
541 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
542 | #endif | |
543 | ||
544 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
545 | ||
546 | #endif /* CONFIG_PCI */ | |
547 | ||
548 | /* SATA */ | |
549 | #define CONFIG_LIBATA | |
550 | #define CONFIG_FSL_SATA | |
551 | ||
6d0f6bcf | 552 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
9490a7f1 | 553 | #define CONFIG_SATA1 |
6d0f6bcf JCPV |
554 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
555 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
9490a7f1 | 556 | #define CONFIG_SATA2 |
6d0f6bcf JCPV |
557 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
558 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
9490a7f1 KG |
559 | |
560 | #ifdef CONFIG_FSL_SATA | |
561 | #define CONFIG_LBA48 | |
562 | #define CONFIG_CMD_SATA | |
563 | #define CONFIG_DOS_PARTITION | |
564 | #define CONFIG_CMD_EXT2 | |
565 | #endif | |
566 | ||
567 | #if defined(CONFIG_TSEC_ENET) | |
568 | ||
9490a7f1 KG |
569 | #define CONFIG_MII 1 /* MII PHY management */ |
570 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
571 | #define CONFIG_TSEC1 1 | |
572 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
573 | #define CONFIG_TSEC3 1 | |
574 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
575 | ||
2e26d837 JJ |
576 | #define CONFIG_FSL_SGMII_RISER 1 |
577 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
578 | ||
9490a7f1 KG |
579 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
580 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ | |
581 | ||
582 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
583 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
584 | ||
585 | #define TSEC1_PHYIDX 0 | |
586 | #define TSEC3_PHYIDX 0 | |
587 | ||
588 | #define CONFIG_ETHPRIME "eTSEC1" | |
589 | ||
590 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
591 | ||
592 | #endif /* CONFIG_TSEC_ENET */ | |
593 | ||
594 | /* | |
595 | * Environment | |
596 | */ | |
9a1a0aed MH |
597 | |
598 | #if defined(CONFIG_SYS_RAMBOOT) | |
0234446f | 599 | #if defined(CONFIG_RAMBOOT_SPIFLASH) |
2d4afd49 XX |
600 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
601 | #define CONFIG_ENV_SPI_BUS 0 | |
602 | #define CONFIG_ENV_SPI_CS 0 | |
603 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
604 | #define CONFIG_ENV_SPI_MODE 0 | |
605 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
606 | #define CONFIG_ENV_OFFSET 0xF0000 | |
607 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
608 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
609 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 610 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
2d4afd49 XX |
611 | #define CONFIG_ENV_SIZE 0x2000 |
612 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
613 | #else | |
e40ac487 MH |
614 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
615 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
616 | #define CONFIG_ENV_SIZE 0x2000 | |
9a1a0aed | 617 | #endif |
9490a7f1 | 618 | #else |
9a1a0aed | 619 | #define CONFIG_ENV_IS_IN_FLASH 1 |
9a1a0aed | 620 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
9a1a0aed MH |
621 | #define CONFIG_ENV_SIZE 0x2000 |
622 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
9490a7f1 | 623 | #endif |
9490a7f1 KG |
624 | |
625 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 626 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9490a7f1 KG |
627 | |
628 | /* | |
629 | * Command line configuration. | |
630 | */ | |
9490a7f1 KG |
631 | #define CONFIG_CMD_IRQ |
632 | #define CONFIG_CMD_PING | |
633 | #define CONFIG_CMD_I2C | |
634 | #define CONFIG_CMD_MII | |
1c9aa76b | 635 | #define CONFIG_CMD_IRQ |
199e262e | 636 | #define CONFIG_CMD_REGINFO |
9490a7f1 KG |
637 | |
638 | #if defined(CONFIG_PCI) | |
639 | #define CONFIG_CMD_PCI | |
9490a7f1 KG |
640 | #endif |
641 | ||
642 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
643 | ||
80522dc8 AF |
644 | #define CONFIG_MMC 1 |
645 | ||
646 | #ifdef CONFIG_MMC | |
647 | #define CONFIG_FSL_ESDHC | |
648 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
649 | #define CONFIG_CMD_MMC | |
650 | #define CONFIG_GENERIC_MMC | |
1116ebb9 F |
651 | #endif |
652 | ||
653 | /* | |
654 | * USB | |
655 | */ | |
3d7506fa | 656 | #define CONFIG_HAS_FSL_MPH_USB |
657 | #ifdef CONFIG_HAS_FSL_MPH_USB | |
1116ebb9 F |
658 | #define CONFIG_USB_EHCI |
659 | ||
660 | #ifdef CONFIG_USB_EHCI | |
661 | #define CONFIG_CMD_USB | |
662 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
663 | #define CONFIG_USB_EHCI_FSL | |
664 | #define CONFIG_USB_STORAGE | |
665 | #endif | |
3d7506fa | 666 | #endif |
1116ebb9 F |
667 | |
668 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
80522dc8 AF |
669 | #define CONFIG_CMD_EXT2 |
670 | #define CONFIG_CMD_FAT | |
671 | #define CONFIG_DOS_PARTITION | |
672 | #endif | |
673 | ||
9490a7f1 KG |
674 | /* |
675 | * Miscellaneous configurable options | |
676 | */ | |
6d0f6bcf | 677 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
07355700 | 678 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
5be58f5f | 679 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
6d0f6bcf | 680 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
9490a7f1 | 681 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 682 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9490a7f1 | 683 | #else |
6d0f6bcf | 684 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9490a7f1 | 685 | #endif |
07355700 MH |
686 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
687 | + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ | |
6d0f6bcf | 688 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
07355700 | 689 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
9490a7f1 KG |
690 | |
691 | /* | |
692 | * For booting Linux, the board info and command line data | |
a832ac41 | 693 | * have to be in the first 64 MB of memory, since this is |
9490a7f1 KG |
694 | * the maximum mapped by the Linux kernel during initialization. |
695 | */ | |
a832ac41 KG |
696 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ |
697 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
9490a7f1 | 698 | |
9490a7f1 KG |
699 | #if defined(CONFIG_CMD_KGDB) |
700 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
9490a7f1 KG |
701 | #endif |
702 | ||
703 | /* | |
704 | * Environment Configuration | |
705 | */ | |
706 | ||
707 | /* The mac addresses for all ethernet interface */ | |
708 | #if defined(CONFIG_TSEC_ENET) | |
709 | #define CONFIG_HAS_ETH0 | |
9490a7f1 | 710 | #define CONFIG_HAS_ETH1 |
9490a7f1 | 711 | #define CONFIG_HAS_ETH2 |
9490a7f1 | 712 | #define CONFIG_HAS_ETH3 |
9490a7f1 KG |
713 | #endif |
714 | ||
715 | #define CONFIG_IPADDR 192.168.1.254 | |
716 | ||
717 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 718 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 719 | #define CONFIG_BOOTFILE "uImage" |
07355700 | 720 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
9490a7f1 KG |
721 | |
722 | #define CONFIG_SERVERIP 192.168.1.1 | |
723 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
724 | #define CONFIG_NETMASK 255.255.255.0 | |
725 | ||
726 | /* default location for tftp and bootm */ | |
727 | #define CONFIG_LOADADDR 1000000 | |
728 | ||
729 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
730 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
731 | ||
732 | #define CONFIG_BAUDRATE 115200 | |
733 | ||
734 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d MV |
735 | "netdev=eth0\0" \ |
736 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
737 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
738 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
739 | " +$filesize; " \ | |
740 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
741 | " +$filesize; " \ | |
742 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
743 | " $filesize; " \ | |
744 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
745 | " +$filesize; " \ | |
746 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
747 | " $filesize\0" \ | |
748 | "consoledev=ttyS0\0" \ | |
749 | "ramdiskaddr=2000000\0" \ | |
750 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ | |
751 | "fdtaddr=c00000\0" \ | |
752 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ | |
753 | "bdev=sda3\0" \ | |
754 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" | |
9490a7f1 KG |
755 | |
756 | #define CONFIG_HDBOOT \ | |
757 | "setenv bootargs root=/dev/$bdev rw " \ | |
758 | "console=$consoledev,$baudrate $othbootargs;" \ | |
759 | "tftp $loadaddr $bootfile;" \ | |
760 | "tftp $fdtaddr $fdtfile;" \ | |
761 | "bootm $loadaddr - $fdtaddr" | |
762 | ||
763 | #define CONFIG_NFSBOOTCOMMAND \ | |
764 | "setenv bootargs root=/dev/nfs rw " \ | |
765 | "nfsroot=$serverip:$rootpath " \ | |
766 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
767 | "console=$consoledev,$baudrate $othbootargs;" \ | |
768 | "tftp $loadaddr $bootfile;" \ | |
769 | "tftp $fdtaddr $fdtfile;" \ | |
770 | "bootm $loadaddr - $fdtaddr" | |
771 | ||
772 | #define CONFIG_RAMBOOTCOMMAND \ | |
773 | "setenv bootargs root=/dev/ram rw " \ | |
774 | "console=$consoledev,$baudrate $othbootargs;" \ | |
775 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
776 | "tftp $loadaddr $bootfile;" \ | |
777 | "tftp $fdtaddr $fdtfile;" \ | |
778 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
779 | ||
780 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
781 | ||
782 | #endif /* __CONFIG_H */ |