]>
Commit | Line | Data |
---|---|---|
03f5c550 WD |
1 | /* |
2 | * Copyright 2004 Freescale Semiconductor. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8541cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
03f5c550 WD |
29 | #ifndef __CONFIG_H |
30 | #define __CONFIG_H | |
31 | ||
32 | /* High Level Configuration Options */ | |
33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ | |
9c4c5ae3 | 36 | #define CONFIG_CPM2 1 /* has CPM2 */ |
03f5c550 WD |
37 | #define CONFIG_MPC8541 1 /* MPC8541 specific */ |
38 | #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ | |
39 | ||
2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
41 | ||
03f5c550 | 42 | #define CONFIG_PCI |
0151cbac | 43 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 44 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
03f5c550 | 45 | #define CONFIG_ENV_OVERWRITE |
d9b94f28 | 46 | |
2cfaa1aa | 47 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
03f5c550 | 48 | |
25eedb2c | 49 | #define CONFIG_FSL_VIA |
25eedb2c | 50 | |
03f5c550 WD |
51 | #ifndef __ASSEMBLY__ |
52 | extern unsigned long get_clock_freq(void); | |
53 | #endif | |
54 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
55 | ||
56 | /* | |
57 | * These can be toggled for performance analysis, otherwise use default. | |
58 | */ | |
53677ef1 | 59 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
03f5c550 | 60 | #define CONFIG_BTB /* toggle branch predition */ |
03f5c550 | 61 | |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
63 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
03f5c550 | 64 | |
03f5c550 WD |
65 | /* |
66 | * Base addresses -- Note these are effective addresses where the | |
67 | * actual resources get mapped (not physical addresses) | |
68 | */ | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
70 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
71 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
72 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
03f5c550 | 73 | |
aa11d85c JL |
74 | /* DDR Setup */ |
75 | #define CONFIG_FSL_DDR1 | |
76 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
77 | #define CONFIG_DDR_SPD | |
78 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
79 | ||
80 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
81 | ||
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
83 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
03f5c550 | 84 | |
aa11d85c JL |
85 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
86 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
87 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
88 | ||
89 | /* I2C addresses of SPD EEPROMs */ | |
90 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
03f5c550 WD |
91 | |
92 | /* | |
93 | * Make sure required options are set | |
94 | */ | |
95 | #ifndef CONFIG_SPD_EEPROM | |
96 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") | |
97 | #endif | |
98 | ||
7202d43d JL |
99 | #undef CONFIG_CLOCKS_IN_MHZ |
100 | ||
03f5c550 | 101 | /* |
7202d43d | 102 | * Local Bus Definitions |
03f5c550 | 103 | */ |
7202d43d JL |
104 | |
105 | /* | |
106 | * FLASH on the Local Bus | |
107 | * Two banks, 8M each, using the CFI driver. | |
108 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
109 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
110 | * | |
111 | * BR0, BR1: | |
112 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
113 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
114 | * Port Size = 16 bits = BRx[19:20] = 10 | |
115 | * Use GPCM = BRx[24:26] = 000 | |
116 | * Valid = BRx[31] = 1 | |
117 | * | |
118 | * 0 4 8 12 16 20 24 28 | |
119 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
120 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
121 | * | |
122 | * OR0, OR1: | |
123 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
124 | * Reserved ORx[17:18] = 11, confusion here? | |
125 | * CSNT = ORx[20] = 1 | |
126 | * ACS = half cycle delay = ORx[21:22] = 11 | |
127 | * SCY = 6 = ORx[24:27] = 0110 | |
128 | * TRLX = use relaxed timing = ORx[29] = 1 | |
129 | * EAD = use external address latch delay = OR[31] = 1 | |
130 | * | |
131 | * 0 4 8 12 16 20 24 28 | |
132 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
133 | */ | |
134 | ||
6d0f6bcf | 135 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
03f5c550 | 136 | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
138 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 | |
03f5c550 | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
141 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
03f5c550 | 142 | |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
144 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
145 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
146 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
147 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
148 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
03f5c550 | 149 | |
14d0a02a | 150 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
03f5c550 | 151 | |
00b1883a | 152 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_FLASH_CFI |
154 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
03f5c550 | 155 | |
03f5c550 WD |
156 | |
157 | /* | |
7202d43d | 158 | * SDRAM on the Local Bus |
03f5c550 | 159 | */ |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
161 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
03f5c550 WD |
162 | |
163 | /* | |
164 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 165 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
03f5c550 WD |
166 | * |
167 | * For BR2, need: | |
168 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
169 | * port-size = 32-bits = BR2[19:20] = 11 | |
170 | * no parity checking = BR2[21:22] = 00 | |
171 | * SDRAM for MSEL = BR2[24:26] = 011 | |
172 | * Valid = BR[31] = 1 | |
173 | * | |
174 | * 0 4 8 12 16 20 24 28 | |
175 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
176 | * | |
6d0f6bcf | 177 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
03f5c550 WD |
178 | * FIXME: the top 17 bits of BR2. |
179 | */ | |
180 | ||
6d0f6bcf | 181 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
03f5c550 WD |
182 | |
183 | /* | |
6d0f6bcf | 184 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
03f5c550 WD |
185 | * |
186 | * For OR2, need: | |
187 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
188 | * XAM, OR2[17:18] = 11 | |
189 | * 9 columns OR2[19-21] = 010 | |
190 | * 13 rows OR2[23-25] = 100 | |
191 | * EAD set for extra time OR[31] = 1 | |
192 | * | |
193 | * 0 4 8 12 16 20 24 28 | |
194 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
195 | */ | |
196 | ||
6d0f6bcf | 197 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
03f5c550 | 198 | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
200 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
201 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
202 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
03f5c550 | 203 | |
03f5c550 WD |
204 | /* |
205 | * Common settings for all Local Bus SDRAM commands. | |
206 | * At run time, either BSMA1516 (for CPU 1.1) | |
207 | * or BSMA1617 (for CPU 1.0) (old) | |
208 | * is OR'ed in too. | |
209 | */ | |
b0fe93ed KG |
210 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
211 | | LSDMR_PRETOACT7 \ | |
212 | | LSDMR_ACTTORW7 \ | |
213 | | LSDMR_BL8 \ | |
214 | | LSDMR_WRC4 \ | |
215 | | LSDMR_CL3 \ | |
216 | | LSDMR_RFEN \ | |
03f5c550 WD |
217 | ) |
218 | ||
219 | /* | |
220 | * The CADMUS registers are connected to CS3 on CDS. | |
221 | * The new memory map places CADMUS at 0xf8000000. | |
222 | * | |
223 | * For BR3, need: | |
224 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
225 | * port-size = 8-bits = BR[19:20] = 01 | |
226 | * no parity checking = BR[21:22] = 00 | |
227 | * GPMC for MSEL = BR[24:26] = 000 | |
228 | * Valid = BR[31] = 1 | |
229 | * | |
230 | * 0 4 8 12 16 20 24 28 | |
231 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
232 | * | |
233 | * For OR3, need: | |
234 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
235 | * disable buffer ctrl OR[19] = 0 | |
236 | * CSNT OR[20] = 1 | |
237 | * ACS OR[21:22] = 11 | |
238 | * XACS OR[23] = 1 | |
239 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
240 | * SETA OR[28] = 0 | |
241 | * TRLX OR[29] = 1 | |
242 | * EHTR OR[30] = 1 | |
243 | * EAD extra time OR[31] = 1 | |
244 | * | |
245 | * 0 4 8 12 16 20 24 28 | |
246 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
247 | */ | |
248 | ||
25eedb2c JL |
249 | #define CONFIG_FSL_CADMUS |
250 | ||
03f5c550 | 251 | #define CADMUS_BASE_ADDR 0xf8000000 |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
253 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 | |
03f5c550 | 254 | |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
256 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 257 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
03f5c550 | 258 | |
6d0f6bcf | 259 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
553f0982 | 260 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) |
6d0f6bcf | 261 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
03f5c550 | 262 | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
264 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
03f5c550 WD |
265 | |
266 | /* Serial Port */ | |
267 | #define CONFIG_CONS_INDEX 2 | |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_NS16550 |
269 | #define CONFIG_SYS_NS16550_SERIAL | |
270 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
271 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
03f5c550 | 272 | |
6d0f6bcf | 273 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
03f5c550 WD |
274 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
275 | ||
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
277 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
03f5c550 WD |
278 | |
279 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_HUSH_PARSER |
281 | #ifdef CONFIG_SYS_HUSH_PARSER | |
282 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
03f5c550 WD |
283 | #endif |
284 | ||
0e16387d | 285 | /* pass open firmware flat tree */ |
b90d2549 KG |
286 | #define CONFIG_OF_LIBFDT 1 |
287 | #define CONFIG_OF_BOARD_SETUP 1 | |
288 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0e16387d | 289 | |
20476726 JL |
290 | /* |
291 | * I2C | |
292 | */ | |
293 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
294 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
03f5c550 | 295 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
297 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
298 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
299 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
03f5c550 | 300 | |
e8d18541 TT |
301 | /* EEPROM */ |
302 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_I2C_EEPROM_CCID |
304 | #define CONFIG_SYS_ID_EEPROM | |
305 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
306 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 307 | |
03f5c550 WD |
308 | /* |
309 | * General PCI | |
362dd830 | 310 | * Memory space is mapped 1-1, but I/O space must start from 0. |
03f5c550 | 311 | */ |
5af0fdd8 | 312 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 313 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 314 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 315 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 316 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 317 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
319 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
320 | ||
5af0fdd8 | 321 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
10795f42 | 322 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
5af0fdd8 | 323 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
6d0f6bcf | 324 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 325 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 |
5f91ef6a | 326 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 |
328 | #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ | |
03f5c550 | 329 | |
7f3f2bd2 RV |
330 | #ifdef CONFIG_LEGACY |
331 | #define BRIDGE_ID 17 | |
332 | #define VIA_ID 2 | |
333 | #else | |
334 | #define BRIDGE_ID 28 | |
335 | #define VIA_ID 4 | |
336 | #endif | |
03f5c550 WD |
337 | |
338 | #if defined(CONFIG_PCI) | |
339 | ||
bf1dfffd | 340 | #define CONFIG_MPC85XX_PCI2 |
03f5c550 | 341 | #define CONFIG_NET_MULTI |
53677ef1 | 342 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
03f5c550 WD |
343 | |
344 | #undef CONFIG_EEPRO100 | |
345 | #undef CONFIG_TULIP | |
346 | ||
03f5c550 | 347 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 348 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
03f5c550 WD |
349 | |
350 | #endif /* CONFIG_PCI */ | |
351 | ||
352 | ||
353 | #if defined(CONFIG_TSEC_ENET) | |
354 | ||
355 | #ifndef CONFIG_NET_MULTI | |
53677ef1 | 356 | #define CONFIG_NET_MULTI 1 |
03f5c550 WD |
357 | #endif |
358 | ||
359 | #define CONFIG_MII 1 /* MII PHY management */ | |
255a3577 KP |
360 | #define CONFIG_TSEC1 1 |
361 | #define CONFIG_TSEC1_NAME "TSEC0" | |
362 | #define CONFIG_TSEC2 1 | |
363 | #define CONFIG_TSEC2_NAME "TSEC1" | |
03f5c550 WD |
364 | #define TSEC1_PHY_ADDR 0 |
365 | #define TSEC2_PHY_ADDR 1 | |
03f5c550 WD |
366 | #define TSEC1_PHYIDX 0 |
367 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
368 | #define TSEC1_FLAGS TSEC_GIGABIT |
369 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
370 | |
371 | /* Options are: TSEC[0-1] */ | |
372 | #define CONFIG_ETHPRIME "TSEC0" | |
03f5c550 WD |
373 | |
374 | #endif /* CONFIG_TSEC_ENET */ | |
375 | ||
03f5c550 WD |
376 | /* |
377 | * Environment | |
378 | */ | |
5a1aceb0 | 379 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 380 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
381 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
382 | #define CONFIG_ENV_SIZE 0x2000 | |
03f5c550 WD |
383 | |
384 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
03f5c550 | 386 | |
659e2f67 JL |
387 | /* |
388 | * BOOTP options | |
389 | */ | |
390 | #define CONFIG_BOOTP_BOOTFILESIZE | |
391 | #define CONFIG_BOOTP_BOOTPATH | |
392 | #define CONFIG_BOOTP_GATEWAY | |
393 | #define CONFIG_BOOTP_HOSTNAME | |
394 | ||
395 | ||
2835e518 JL |
396 | /* |
397 | * Command line configuration. | |
398 | */ | |
399 | #include <config_cmd_default.h> | |
400 | ||
401 | #define CONFIG_CMD_PING | |
402 | #define CONFIG_CMD_I2C | |
403 | #define CONFIG_CMD_MII | |
82ac8c97 | 404 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
405 | #define CONFIG_CMD_IRQ |
406 | #define CONFIG_CMD_SETEXPR | |
199e262e | 407 | #define CONFIG_CMD_REGINFO |
2835e518 | 408 | |
03f5c550 | 409 | #if defined(CONFIG_PCI) |
2835e518 | 410 | #define CONFIG_CMD_PCI |
03f5c550 | 411 | #endif |
2835e518 | 412 | |
03f5c550 WD |
413 | |
414 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
415 | ||
416 | /* | |
417 | * Miscellaneous configurable options | |
418 | */ | |
6d0f6bcf | 419 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
420 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
421 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
422 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
423 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 424 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 425 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
03f5c550 | 426 | #else |
6d0f6bcf | 427 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
03f5c550 | 428 | #endif |
6d0f6bcf JCPV |
429 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
430 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
431 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
432 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
03f5c550 WD |
433 | |
434 | /* | |
435 | * For booting Linux, the board info and command line data | |
89188a62 | 436 | * have to be in the first 16 MB of memory, since this is |
03f5c550 WD |
437 | * the maximum mapped by the Linux kernel during initialization. |
438 | */ | |
89188a62 | 439 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
03f5c550 | 440 | |
2835e518 | 441 | #if defined(CONFIG_CMD_KGDB) |
03f5c550 WD |
442 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
443 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
444 | #endif | |
445 | ||
03f5c550 WD |
446 | /* |
447 | * Environment Configuration | |
448 | */ | |
449 | ||
450 | /* The mac addresses for all ethernet interface */ | |
451 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 452 | #define CONFIG_HAS_ETH0 |
03f5c550 | 453 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
e2ffd59b | 454 | #define CONFIG_HAS_ETH1 |
03f5c550 | 455 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
e2ffd59b | 456 | #define CONFIG_HAS_ETH2 |
03f5c550 WD |
457 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
458 | #endif | |
459 | ||
460 | #define CONFIG_IPADDR 192.168.1.253 | |
461 | ||
462 | #define CONFIG_HOSTNAME unknown | |
463 | #define CONFIG_ROOTPATH /nfsroot | |
464 | #define CONFIG_BOOTFILE your.uImage | |
465 | ||
466 | #define CONFIG_SERVERIP 192.168.1.1 | |
467 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
468 | #define CONFIG_NETMASK 255.255.255.0 | |
469 | ||
470 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
471 | ||
472 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
473 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
474 | ||
475 | #define CONFIG_BAUDRATE 115200 | |
476 | ||
477 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
478 | "netdev=eth0\0" \ | |
479 | "consoledev=ttyS1\0" \ | |
8272dc2f AF |
480 | "ramdiskaddr=600000\0" \ |
481 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
482 | "fdtaddr=400000\0" \ | |
483 | "fdtfile=your.fdt.dtb\0" | |
03f5c550 WD |
484 | |
485 | #define CONFIG_NFSBOOTCOMMAND \ | |
486 | "setenv bootargs root=/dev/nfs rw " \ | |
487 | "nfsroot=$serverip:$rootpath " \ | |
488 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
489 | "console=$consoledev,$baudrate $othbootargs;" \ | |
490 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f AF |
491 | "tftp $fdtaddr $fdtfile;" \ |
492 | "bootm $loadaddr - $fdtaddr" | |
03f5c550 WD |
493 | |
494 | #define CONFIG_RAMBOOTCOMMAND \ | |
495 | "setenv bootargs root=/dev/ram rw " \ | |
496 | "console=$consoledev,$baudrate $othbootargs;" \ | |
497 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
498 | "tftp $loadaddr $bootfile;" \ | |
499 | "bootm $loadaddr $ramdiskaddr" | |
500 | ||
501 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
502 | ||
03f5c550 | 503 | #endif /* __CONFIG_H */ |