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d9b94f28 | 1 | /* |
f2cff6b1 | 2 | * Copyright 2004, 2007 Freescale Semiconductor. |
d9b94f28 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f2cff6b1 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d9b94f28 JL |
15 | * GNU General Public License for more details. |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8548cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* High Level Configuration Options */ | |
33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
36 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ | |
37 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ | |
38 | ||
f2cff6b1 ES |
39 | #define CONFIG_PCI /* enable any pci type devices */ |
40 | #define CONFIG_PCI1 /* PCI controller 1 */ | |
41 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
42 | #undef CONFIG_RIO | |
43 | #undef CONFIG_PCI2 | |
44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
8ff3de61 | 45 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 46 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
f2cff6b1 ES |
47 | |
48 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
d9b94f28 | 49 | #define CONFIG_ENV_OVERWRITE |
f2cff6b1 | 50 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
2cfaa1aa | 51 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
d9b94f28 | 52 | |
25eedb2c | 53 | #define CONFIG_FSL_VIA |
25eedb2c | 54 | |
d9b94f28 JL |
55 | #ifndef __ASSEMBLY__ |
56 | extern unsigned long get_clock_freq(void); | |
57 | #endif | |
58 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
59 | ||
60 | /* | |
61 | * These can be toggled for performance analysis, otherwise use default. | |
62 | */ | |
f2cff6b1 ES |
63 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
64 | #define CONFIG_BTB /* toggle branch predition */ | |
d9b94f28 JL |
65 | |
66 | /* | |
67 | * Only possible on E500 Version 2 or newer cores. | |
68 | */ | |
69 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
70 | ||
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
72 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
d9b94f28 JL |
73 | |
74 | /* | |
75 | * Base addresses -- Note these are effective addresses where the | |
76 | * actual resources get mapped (not physical addresses) | |
77 | */ | |
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
79 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
80 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
81 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
d9b94f28 | 82 | |
e31d2c1e JL |
83 | /* DDR Setup */ |
84 | #define CONFIG_FSL_DDR2 | |
85 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
86 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
87 | #define CONFIG_DDR_SPD | |
88 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
89 | ||
9b0ad1b1 | 90 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e31d2c1e JL |
91 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
92 | ||
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
94 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
d9b94f28 | 95 | |
e31d2c1e JL |
96 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
97 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
98 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
d9b94f28 | 99 | |
e31d2c1e JL |
100 | /* I2C addresses of SPD EEPROMs */ |
101 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
102 | ||
103 | /* Make sure required options are set */ | |
d9b94f28 JL |
104 | #ifndef CONFIG_SPD_EEPROM |
105 | #error ("CONFIG_SPD_EEPROM is required") | |
106 | #endif | |
107 | ||
108 | #undef CONFIG_CLOCKS_IN_MHZ | |
109 | ||
d9b94f28 JL |
110 | /* |
111 | * Local Bus Definitions | |
112 | */ | |
113 | ||
114 | /* | |
115 | * FLASH on the Local Bus | |
116 | * Two banks, 8M each, using the CFI driver. | |
117 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
118 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
119 | * | |
120 | * BR0, BR1: | |
121 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
122 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
123 | * Port Size = 16 bits = BRx[19:20] = 10 | |
124 | * Use GPCM = BRx[24:26] = 000 | |
125 | * Valid = BRx[31] = 1 | |
126 | * | |
f2cff6b1 ES |
127 | * 0 4 8 12 16 20 24 28 |
128 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
129 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
d9b94f28 JL |
130 | * |
131 | * OR0, OR1: | |
132 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
133 | * Reserved ORx[17:18] = 11, confusion here? | |
134 | * CSNT = ORx[20] = 1 | |
135 | * ACS = half cycle delay = ORx[21:22] = 11 | |
136 | * SCY = 6 = ORx[24:27] = 0110 | |
137 | * TRLX = use relaxed timing = ORx[29] = 1 | |
138 | * EAD = use external address latch delay = OR[31] = 1 | |
139 | * | |
f2cff6b1 ES |
140 | * 0 4 8 12 16 20 24 28 |
141 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
d9b94f28 JL |
142 | */ |
143 | ||
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ |
145 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ | |
d9b94f28 | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
148 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 | |
d9b94f28 | 149 | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
151 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
d9b94f28 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
154 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
155 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
156 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
157 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
158 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
d9b94f28 | 159 | |
14d0a02a | 160 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d9b94f28 | 161 | |
00b1883a | 162 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_FLASH_CFI |
164 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
d9b94f28 JL |
165 | |
166 | ||
167 | /* | |
168 | * SDRAM on the Local Bus | |
169 | */ | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
171 | #define CONFIG_SYS_LBC_CACHE_SIZE 64 | |
172 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ | |
173 | #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 | |
f2cff6b1 | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ |
176 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
d9b94f28 JL |
177 | |
178 | /* | |
179 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 180 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
d9b94f28 JL |
181 | * |
182 | * For BR2, need: | |
183 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
184 | * port-size = 32-bits = BR2[19:20] = 11 | |
185 | * no parity checking = BR2[21:22] = 00 | |
186 | * SDRAM for MSEL = BR2[24:26] = 011 | |
187 | * Valid = BR[31] = 1 | |
188 | * | |
f2cff6b1 | 189 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
190 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
191 | * | |
6d0f6bcf | 192 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
d9b94f28 JL |
193 | * FIXME: the top 17 bits of BR2. |
194 | */ | |
195 | ||
6d0f6bcf | 196 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
d9b94f28 JL |
197 | |
198 | /* | |
6d0f6bcf | 199 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
d9b94f28 JL |
200 | * |
201 | * For OR2, need: | |
202 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
203 | * XAM, OR2[17:18] = 11 | |
204 | * 9 columns OR2[19-21] = 010 | |
f2cff6b1 | 205 | * 13 rows OR2[23-25] = 100 |
d9b94f28 JL |
206 | * EAD set for extra time OR[31] = 1 |
207 | * | |
f2cff6b1 | 208 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
209 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
210 | */ | |
211 | ||
6d0f6bcf | 212 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
d9b94f28 | 213 | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
215 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
216 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
217 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
d9b94f28 | 218 | |
d9b94f28 JL |
219 | /* |
220 | * Common settings for all Local Bus SDRAM commands. | |
221 | * At run time, either BSMA1516 (for CPU 1.1) | |
f2cff6b1 | 222 | * or BSMA1617 (for CPU 1.0) (old) |
d9b94f28 JL |
223 | * is OR'ed in too. |
224 | */ | |
b0fe93ed KG |
225 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
226 | | LSDMR_PRETOACT7 \ | |
227 | | LSDMR_ACTTORW7 \ | |
228 | | LSDMR_BL8 \ | |
229 | | LSDMR_WRC4 \ | |
230 | | LSDMR_CL3 \ | |
231 | | LSDMR_RFEN \ | |
d9b94f28 JL |
232 | ) |
233 | ||
234 | /* | |
235 | * The CADMUS registers are connected to CS3 on CDS. | |
236 | * The new memory map places CADMUS at 0xf8000000. | |
237 | * | |
238 | * For BR3, need: | |
239 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
240 | * port-size = 8-bits = BR[19:20] = 01 | |
241 | * no parity checking = BR[21:22] = 00 | |
f2cff6b1 ES |
242 | * GPMC for MSEL = BR[24:26] = 000 |
243 | * Valid = BR[31] = 1 | |
d9b94f28 | 244 | * |
f2cff6b1 | 245 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
246 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
247 | * | |
248 | * For OR3, need: | |
f2cff6b1 | 249 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
d9b94f28 | 250 | * disable buffer ctrl OR[19] = 0 |
f2cff6b1 ES |
251 | * CSNT OR[20] = 1 |
252 | * ACS OR[21:22] = 11 | |
253 | * XACS OR[23] = 1 | |
d9b94f28 | 254 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
f2cff6b1 ES |
255 | * SETA OR[28] = 0 |
256 | * TRLX OR[29] = 1 | |
257 | * EHTR OR[30] = 1 | |
258 | * EAD extra time OR[31] = 1 | |
d9b94f28 | 259 | * |
f2cff6b1 | 260 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
261 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
262 | */ | |
263 | ||
25eedb2c JL |
264 | #define CONFIG_FSL_CADMUS |
265 | ||
d9b94f28 | 266 | #define CADMUS_BASE_ADDR 0xf8000000 |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
268 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 | |
d9b94f28 | 269 | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
271 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
272 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
f2cff6b1 | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
d9b94f28 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
277 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
278 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
d9b94f28 | 279 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
281 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
d9b94f28 JL |
282 | |
283 | /* Serial Port */ | |
f2cff6b1 | 284 | #define CONFIG_CONS_INDEX 2 |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_NS16550 |
286 | #define CONFIG_SYS_NS16550_SERIAL | |
287 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
288 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
d9b94f28 | 289 | |
6d0f6bcf | 290 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
d9b94f28 JL |
291 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
292 | ||
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
294 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
d9b94f28 JL |
295 | |
296 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
297 | #define CONFIG_SYS_HUSH_PARSER |
298 | #ifdef CONFIG_SYS_HUSH_PARSER | |
299 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
d9b94f28 JL |
300 | #endif |
301 | ||
40d5fa35 | 302 | /* pass open firmware flat tree */ |
b90d2549 KG |
303 | #define CONFIG_OF_LIBFDT 1 |
304 | #define CONFIG_OF_BOARD_SETUP 1 | |
305 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
40d5fa35 | 306 | |
20476726 JL |
307 | /* |
308 | * I2C | |
309 | */ | |
310 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
311 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
f2cff6b1 | 312 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
314 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
315 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
316 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
d9b94f28 | 317 | |
e8d18541 TT |
318 | /* EEPROM */ |
319 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_I2C_EEPROM_CCID |
321 | #define CONFIG_SYS_ID_EEPROM | |
322 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
323 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 324 | |
d9b94f28 JL |
325 | /* |
326 | * General PCI | |
362dd830 | 327 | * Memory space is mapped 1-1, but I/O space must start from 0. |
d9b94f28 | 328 | */ |
5af0fdd8 | 329 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
6d0f6bcf | 330 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
f2cff6b1 | 331 | |
5af0fdd8 | 332 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 333 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 334 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 335 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 336 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 337 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
339 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
d9b94f28 | 340 | |
f2cff6b1 | 341 | #ifdef CONFIG_PCI2 |
5af0fdd8 | 342 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
10795f42 | 343 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
5af0fdd8 | 344 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
6d0f6bcf | 345 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 346 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 |
5f91ef6a | 347 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 |
349 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
f2cff6b1 | 350 | #endif |
41fb7e0f | 351 | |
f2cff6b1 | 352 | #ifdef CONFIG_PCIE1 |
5af0fdd8 | 353 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 354 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 355 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 356 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 357 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
5f91ef6a | 358 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
360 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
f2cff6b1 | 361 | #endif |
d9b94f28 | 362 | |
f2cff6b1 | 363 | #ifdef CONFIG_RIO |
41fb7e0f ZR |
364 | /* |
365 | * RapidIO MMU | |
366 | */ | |
5af0fdd8 | 367 | #define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 |
10795f42 | 368 | #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 |
6d0f6bcf | 369 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ |
f2cff6b1 | 370 | #endif |
d9b94f28 | 371 | |
7f3f2bd2 RV |
372 | #ifdef CONFIG_LEGACY |
373 | #define BRIDGE_ID 17 | |
374 | #define VIA_ID 2 | |
375 | #else | |
376 | #define BRIDGE_ID 28 | |
377 | #define VIA_ID 4 | |
378 | #endif | |
379 | ||
d9b94f28 JL |
380 | #if defined(CONFIG_PCI) |
381 | ||
382 | #define CONFIG_NET_MULTI | |
f2cff6b1 | 383 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d9b94f28 JL |
384 | |
385 | #undef CONFIG_EEPRO100 | |
386 | #undef CONFIG_TULIP | |
387 | ||
d9b94f28 | 388 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
f2cff6b1 | 389 | |
d9b94f28 JL |
390 | #endif /* CONFIG_PCI */ |
391 | ||
392 | ||
393 | #if defined(CONFIG_TSEC_ENET) | |
394 | ||
395 | #ifndef CONFIG_NET_MULTI | |
f2cff6b1 | 396 | #define CONFIG_NET_MULTI 1 |
d9b94f28 JL |
397 | #endif |
398 | ||
399 | #define CONFIG_MII 1 /* MII PHY management */ | |
255a3577 KP |
400 | #define CONFIG_TSEC1 1 |
401 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
402 | #define CONFIG_TSEC2 1 | |
403 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
404 | #define CONFIG_TSEC3 1 | |
405 | #define CONFIG_TSEC3_NAME "eTSEC2" | |
f2cff6b1 | 406 | #define CONFIG_TSEC4 |
255a3577 | 407 | #define CONFIG_TSEC4_NAME "eTSEC3" |
d9b94f28 JL |
408 | #undef CONFIG_MPC85XX_FEC |
409 | ||
410 | #define TSEC1_PHY_ADDR 0 | |
411 | #define TSEC2_PHY_ADDR 1 | |
412 | #define TSEC3_PHY_ADDR 2 | |
413 | #define TSEC4_PHY_ADDR 3 | |
d9b94f28 JL |
414 | |
415 | #define TSEC1_PHYIDX 0 | |
416 | #define TSEC2_PHYIDX 0 | |
417 | #define TSEC3_PHYIDX 0 | |
418 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
419 | #define TSEC1_FLAGS TSEC_GIGABIT |
420 | #define TSEC2_FLAGS TSEC_GIGABIT | |
421 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
422 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
d9b94f28 JL |
423 | |
424 | /* Options are: eTSEC[0-3] */ | |
425 | #define CONFIG_ETHPRIME "eTSEC0" | |
f2cff6b1 | 426 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d9b94f28 JL |
427 | #endif /* CONFIG_TSEC_ENET */ |
428 | ||
429 | /* | |
430 | * Environment | |
431 | */ | |
5a1aceb0 | 432 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 433 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
434 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
435 | #define CONFIG_ENV_SIZE 0x2000 | |
d9b94f28 JL |
436 | |
437 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 438 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d9b94f28 | 439 | |
659e2f67 JL |
440 | /* |
441 | * BOOTP options | |
442 | */ | |
443 | #define CONFIG_BOOTP_BOOTFILESIZE | |
444 | #define CONFIG_BOOTP_BOOTPATH | |
445 | #define CONFIG_BOOTP_GATEWAY | |
446 | #define CONFIG_BOOTP_HOSTNAME | |
447 | ||
448 | ||
2835e518 JL |
449 | /* |
450 | * Command line configuration. | |
451 | */ | |
452 | #include <config_cmd_default.h> | |
453 | ||
454 | #define CONFIG_CMD_PING | |
455 | #define CONFIG_CMD_I2C | |
456 | #define CONFIG_CMD_MII | |
82ac8c97 | 457 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
458 | #define CONFIG_CMD_IRQ |
459 | #define CONFIG_CMD_SETEXPR | |
199e262e | 460 | #define CONFIG_CMD_REGINFO |
2835e518 | 461 | |
d9b94f28 | 462 | #if defined(CONFIG_PCI) |
2835e518 | 463 | #define CONFIG_CMD_PCI |
d9b94f28 | 464 | #endif |
2835e518 | 465 | |
d9b94f28 JL |
466 | |
467 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
468 | ||
469 | /* | |
470 | * Miscellaneous configurable options | |
471 | */ | |
6d0f6bcf | 472 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
473 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
474 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
475 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
476 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 477 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 478 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d9b94f28 | 479 | #else |
6d0f6bcf | 480 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d9b94f28 | 481 | #endif |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
483 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
484 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
485 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
d9b94f28 JL |
486 | |
487 | /* | |
488 | * For booting Linux, the board info and command line data | |
89188a62 | 489 | * have to be in the first 16 MB of memory, since this is |
d9b94f28 JL |
490 | * the maximum mapped by the Linux kernel during initialization. |
491 | */ | |
89188a62 | 492 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
d9b94f28 | 493 | |
d9b94f28 JL |
494 | /* |
495 | * Internal Definitions | |
496 | * | |
497 | * Boot Flags | |
498 | */ | |
499 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
500 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
501 | ||
2835e518 | 502 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 JL |
503 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
504 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
505 | #endif | |
506 | ||
507 | /* | |
508 | * Environment Configuration | |
509 | */ | |
510 | ||
511 | /* The mac addresses for all ethernet interface */ | |
512 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 513 | #define CONFIG_HAS_ETH0 |
f2cff6b1 | 514 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
d9b94f28 | 515 | #define CONFIG_HAS_ETH1 |
f2cff6b1 | 516 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
d9b94f28 | 517 | #define CONFIG_HAS_ETH2 |
f2cff6b1 | 518 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
09f3e09e | 519 | #define CONFIG_HAS_ETH3 |
f2cff6b1 | 520 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
d9b94f28 JL |
521 | #endif |
522 | ||
f2cff6b1 | 523 | #define CONFIG_IPADDR 192.168.1.253 |
d9b94f28 | 524 | |
f2cff6b1 ES |
525 | #define CONFIG_HOSTNAME unknown |
526 | #define CONFIG_ROOTPATH /nfsroot | |
527 | #define CONFIG_BOOTFILE 8548cds/uImage.uboot | |
528 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ | |
d9b94f28 | 529 | |
f2cff6b1 | 530 | #define CONFIG_SERVERIP 192.168.1.1 |
d9b94f28 | 531 | #define CONFIG_GATEWAYIP 192.168.1.1 |
f2cff6b1 | 532 | #define CONFIG_NETMASK 255.255.255.0 |
d9b94f28 | 533 | |
f2cff6b1 | 534 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
d9b94f28 | 535 | |
f2cff6b1 ES |
536 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
537 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
d9b94f28 JL |
538 | |
539 | #define CONFIG_BAUDRATE 115200 | |
540 | ||
f2cff6b1 ES |
541 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
542 | "netdev=eth0\0" \ | |
543 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
544 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
545 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
546 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
547 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
548 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
549 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
f2cff6b1 ES |
550 | "consoledev=ttyS1\0" \ |
551 | "ramdiskaddr=2000000\0" \ | |
6c543597 | 552 | "ramdiskfile=ramdisk.uboot\0" \ |
4bf4abb8 | 553 | "fdtaddr=c00000\0" \ |
22abb2d2 | 554 | "fdtfile=mpc8548cds.dtb\0" |
f2cff6b1 ES |
555 | |
556 | #define CONFIG_NFSBOOTCOMMAND \ | |
557 | "setenv bootargs root=/dev/nfs rw " \ | |
558 | "nfsroot=$serverip:$rootpath " \ | |
d9b94f28 | 559 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
f2cff6b1 ES |
560 | "console=$consoledev,$baudrate $othbootargs;" \ |
561 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
562 | "tftp $fdtaddr $fdtfile;" \ |
563 | "bootm $loadaddr - $fdtaddr" | |
8272dc2f | 564 | |
d9b94f28 JL |
565 | |
566 | #define CONFIG_RAMBOOTCOMMAND \ | |
f2cff6b1 ES |
567 | "setenv bootargs root=/dev/ram rw " \ |
568 | "console=$consoledev,$baudrate $othbootargs;" \ | |
569 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
570 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
571 | "tftp $fdtaddr $fdtfile;" \ |
572 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
f2cff6b1 ES |
573 | |
574 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
d9b94f28 JL |
575 | |
576 | #endif /* __CONFIG_H */ |