[people/ms/u-boot.git] / include / configs / MPC8548CDS.h

/*
 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8548cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */

#define CONFIG_PCI1		/* PCI controller 1 */
#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

#define CONFIG_FSL_VIA

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
#endif

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD

#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ
/*
 * Physical Address Map
 *
 * 32bit:
 * 0x0000_0000	0x7fff_ffff	DDR			2G	cacheable
 * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M	cacheable
 * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M	cacheable
 * 0xc000_0000	0xdfff_ffff	RapidIO			512M	cacheable
 * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
 * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
 * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
 * 0xf000_0000	0xf3ff_ffff	SDRAM			64M	cacheable
 * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
 * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
 *
 * 36bit:
 * 0x00000_0000	0x07fff_ffff	DDR			2G	cacheable
 * 0xc0000_0000	0xc1fff_ffff	PCI1 MEM		512M	cacheable
 * 0xc2000_0000	0xc3fff_ffff	PCIe MEM		512M	cacheable
 * 0xc4000_0000	0xc5fff_ffff	RapidIO			512M	cacheable
 * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
 * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
 * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
 * 0xff000_0000	0xff3ff_ffff	SDRAM			64M	cacheable
 * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
 * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
 * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
 *
 */

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
 */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_SYS_BR0_PRELIM \
	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
#define CONFIG_SYS_BR1_PRELIM \
	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)

#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
#define	CONFIG_SYS_OR1_PRELIM		0xff806e65

#define CONFIG_SYS_FLASH_BANKS_LIST \
	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_HWCONFIG			/* enable hwconfig */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
#else
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM \
	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
	| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows	OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *		    or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL	  = BR[24:26] = 000
 *    Valid		  = BR[31]    = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT		  OR[20]    = 1
 *    ACS		  OR[21:22] = 11
 *    XACS		  OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA		  OR[28]    = 0
 *    TRLX		  OR[29]    = 1
 *    EHTR		  OR[30]    = 1
 *    EAD extra time	  OR[31]    = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CONFIG_FSL_CADMUS

#define CADMUS_BASE_ADDR 0xf8000000
#ifdef CONFIG_PHYS_64BIT
#define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
#else
#define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
#endif
#define CONFIG_SYS_BR3_PRELIM \
	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX	2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_CCID
#define CONFIG_SYS_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
#else
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
#else
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#endif
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_NAME		"Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
#endif

/*
 * RapidIO MMU
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */

#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC2"
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME	"eTSEC3"
#undef CONFIG_MPC85XX_FEC

#define CONFIG_PHY_MARVELL

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC3_PHY_ADDR		2
#define TSEC4_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC4_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME		"eTSEC0"
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR	0xfff80000
#else
#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K for env */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR	 192.168.1.253

#define CONFIG_HOSTNAME	 unknown
#define CONFIG_ROOTPATH	 "/nfsroot"
#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK	 255.255.255.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#define	CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:ecc=off\0"		\
	"netdev=eth0\0"				\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot; "	\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"consoledev=ttyS1\0"			\
	"ramdiskaddr=2000000\0"			\
	"ramdiskfile=ramdisk.uboot\0"		\
	"fdtaddr=1e00000\0"			\
	"fdtfile=mpc8548cds.dtb\0"

#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
d9b94f28	1	/*
8b47d7ec	2	* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
d9b94f28	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
d9b94f28 JL	5	*/
	6
	7	/*
	8	* mpc8548cds board configuration file
	9	*
	10	* Please refer to doc/README.mpc85xxcds for more info.
	11	*
	12	*/
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
8b47d7ec KG	16	#define CONFIG_SYS_SRIO
	17	#define CONFIG_SRIO1 /* SRIO port 1 */
	18
f2cff6b1	19	#define CONFIG_PCI1 /* PCI controller 1 */
b38eaec5	20	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
f2cff6b1 ES	21	#undef CONFIG_PCI2
f2cff6b1 ES	22	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	23	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
8ff3de61	24	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
0151cbac	25	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
f2cff6b1 ES	26
f2cff6b1 ES	27	#define CONFIG_TSEC_ENET /* tsec ethernet support */
d9b94f28	28	#define CONFIG_ENV_OVERWRITE
f2cff6b1	29	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
d9b94f28	30
25eedb2c	31	#define CONFIG_FSL_VIA
25eedb2c	32
d9b94f28 JL	33	#ifndef __ASSEMBLY__
	34	extern unsigned long get_clock_freq(void);
	35	#endif
	36	#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
	37
	38	/*
	39	* These can be toggled for performance analysis, otherwise use default.
	40	*/
f2cff6b1 ES	41	#define CONFIG_L2_CACHE /* toggle L2 cache */
f2cff6b1 ES	42	#define CONFIG_BTB /* toggle branch predition */
d9b94f28 JL	43
	44	/*
	45	* Only possible on E500 Version 2 or newer cores.
	46	*/
	47	#define CONFIG_ENABLE_36BIT_PHYS 1
	48
b76aef60	49	#ifdef CONFIG_PHYS_64BIT
	50	#define CONFIG_ADDR_MAP
	51	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	52	#endif
	53
6d0f6bcf JCPV	54	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	55	#define CONFIG_SYS_MEMTEST_END 0x00400000
d9b94f28	56
e46fedfe TT	57	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	58	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
d9b94f28	59
e31d2c1e	60	/* DDR Setup */
e31d2c1e JL	61	#undef CONFIG_FSL_DDR_INTERACTIVE
	62	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	63	#define CONFIG_DDR_SPD
e31d2c1e	64
867b06f4	65	#define CONFIG_DDR_ECC
9b0ad1b1	66	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
e31d2c1e JL	67	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
e31d2c1e JL	68
6d0f6bcf JCPV	69	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	70	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
d9b94f28	71
e31d2c1e JL	72	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
e31d2c1e JL	73	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
d9b94f28	74
e31d2c1e JL	75	/* I2C addresses of SPD EEPROMs */
	76	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	77
	78	/* Make sure required options are set */
d9b94f28 JL	79	#ifndef CONFIG_SPD_EEPROM
	80	#error ("CONFIG_SPD_EEPROM is required")
	81	#endif
	82
	83	#undef CONFIG_CLOCKS_IN_MHZ
fff80975	84	/*
	85	* Physical Address Map
	86	*
	87	* 32bit:
	88	* 0x0000_0000 0x7fff_ffff DDR 2G cacheable
	89	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
	90	* 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
	91	* 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
	92	* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
	93	* 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
	94	* 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
	95	* 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
	96	* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
	97	* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
	98	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
	99	*
b76aef60	100	* 36bit:
	101	* 0x00000_0000 0x07fff_ffff DDR 2G cacheable
	102	* 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
	103	* 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
	104	* 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
	105	* 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
	106	* 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
	107	* 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
	108	* 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
	109	* 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
	110	* 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
	111	* 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
	112	*
fff80975	113	*/
fff80975	114
d9b94f28 JL	115	/*
	116	* Local Bus Definitions
	117	*/
	118
	119	/*
	120	* FLASH on the Local Bus
	121	* Two banks, 8M each, using the CFI driver.
	122	* Boot from BR0/OR0 bank at 0xff00_0000
	123	* Alternate BR1/OR1 bank at 0xff80_0000
	124	*
	125	* BR0, BR1:
	126	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	127	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	128	* Port Size = 16 bits = BRx[19:20] = 10
	129	* Use GPCM = BRx[24:26] = 000
	130	* Valid = BRx[31] = 1
	131	*
f2cff6b1 ES	132	* 0 4 8 12 16 20 24 28
	133	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	134	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
d9b94f28 JL	135	*
	136	* OR0, OR1:
	137	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	138	* Reserved ORx[17:18] = 11, confusion here?
	139	* CSNT = ORx[20] = 1
	140	* ACS = half cycle delay = ORx[21:22] = 11
	141	* SCY = 6 = ORx[24:27] = 0110
	142	* TRLX = use relaxed timing = ORx[29] = 1
	143	* EAD = use external address latch delay = OR[31] = 1
	144	*
f2cff6b1 ES	145	* 0 4 8 12 16 20 24 28
f2cff6b1 ES	146	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
d9b94f28 JL	147	*/
d9b94f28 JL	148
fff80975	149	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
b76aef60	150	#ifdef CONFIG_PHYS_64BIT
	151	#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
	152	#else
fff80975	153	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
b76aef60	154	#endif
d9b94f28	155
fff80975	156	#define CONFIG_SYS_BR0_PRELIM \
7ee41107	157	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) \| BR_PS_16 \| BR_V)
fff80975	158	#define CONFIG_SYS_BR1_PRELIM \
fff80975	159	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| BR_PS_16 \| BR_V)
d9b94f28	160
6d0f6bcf JCPV	161	#define CONFIG_SYS_OR0_PRELIM 0xff806e65
6d0f6bcf JCPV	162	#define CONFIG_SYS_OR1_PRELIM 0xff806e65
d9b94f28	163
fff80975	164	#define CONFIG_SYS_FLASH_BANKS_LIST \
fff80975	165	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
6d0f6bcf JCPV	166	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	167	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	168	#undef CONFIG_SYS_FLASH_CHECKSUM
	169	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	170	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
d9b94f28	171
14d0a02a	172	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
d9b94f28	173
00b1883a	174	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH_EMPTY_INFO
d9b94f28	177
867b06f4	178	#define CONFIG_HWCONFIG /* enable hwconfig */
d9b94f28 JL	179
	180	/*
	181	* SDRAM on the Local Bus
	182	*/
fff80975	183	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
b76aef60	184	#ifdef CONFIG_PHYS_64BIT
	185	#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
	186	#else
fff80975	187	#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
b76aef60	188	#endif
6d0f6bcf	189	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
d9b94f28 JL	190
	191	/*
	192	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	193	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
d9b94f28 JL	194	*
	195	* For BR2, need:
	196	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	197	* port-size = 32-bits = BR2[19:20] = 11
	198	* no parity checking = BR2[21:22] = 00
	199	* SDRAM for MSEL = BR2[24:26] = 011
	200	* Valid = BR[31] = 1
	201	*
f2cff6b1	202	* 0 4 8 12 16 20 24 28
d9b94f28 JL	203	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
d9b94f28 JL	204	*
6d0f6bcf	205	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
d9b94f28 JL	206	* FIXME: the top 17 bits of BR2.
	207	*/
	208
fff80975	209	#define CONFIG_SYS_BR2_PRELIM \
	210	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
	211	\| BR_PS_32 \| (3<<BR_MSEL_SHIFT) \| BR_V)
d9b94f28 JL	212
d9b94f28 JL	213	/*
6d0f6bcf	214	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
d9b94f28 JL	215	*
	216	* For OR2, need:
	217	* 64MB mask for AM, OR2[0:7] = 1111 1100
	218	* XAM, OR2[17:18] = 11
	219	* 9 columns OR2[19-21] = 010
f2cff6b1	220	* 13 rows OR2[23-25] = 100
d9b94f28 JL	221	* EAD set for extra time OR[31] = 1
d9b94f28 JL	222	*
f2cff6b1	223	* 0 4 8 12 16 20 24 28
d9b94f28 JL	224	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	225	*/
	226
6d0f6bcf	227	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
d9b94f28	228
6d0f6bcf JCPV	229	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	230	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	231	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	232	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
d9b94f28	233
d9b94f28 JL	234	/*
	235	* Common settings for all Local Bus SDRAM commands.
	236	* At run time, either BSMA1516 (for CPU 1.1)
f2cff6b1	237	* or BSMA1617 (for CPU 1.0) (old)
d9b94f28 JL	238	* is OR'ed in too.
d9b94f28 JL	239	*/
b0fe93ed KG	240	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	241	\| LSDMR_PRETOACT7 \
	242	\| LSDMR_ACTTORW7 \
	243	\| LSDMR_BL8 \
	244	\| LSDMR_WRC4 \
	245	\| LSDMR_CL3 \
	246	\| LSDMR_RFEN \
d9b94f28 JL	247	)
	248
	249	/*
	250	* The CADMUS registers are connected to CS3 on CDS.
	251	* The new memory map places CADMUS at 0xf8000000.
	252	*
	253	* For BR3, need:
	254	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	255	* port-size = 8-bits = BR[19:20] = 01
	256	* no parity checking = BR[21:22] = 00
f2cff6b1 ES	257	* GPMC for MSEL = BR[24:26] = 000
f2cff6b1 ES	258	* Valid = BR[31] = 1
d9b94f28	259	*
f2cff6b1	260	* 0 4 8 12 16 20 24 28
d9b94f28 JL	261	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	262	*
	263	* For OR3, need:
f2cff6b1	264	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
d9b94f28	265	* disable buffer ctrl OR[19] = 0
f2cff6b1 ES	266	* CSNT OR[20] = 1
	267	* ACS OR[21:22] = 11
	268	* XACS OR[23] = 1
d9b94f28	269	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
f2cff6b1 ES	270	* SETA OR[28] = 0
	271	* TRLX OR[29] = 1
	272	* EHTR OR[30] = 1
	273	* EAD extra time OR[31] = 1
d9b94f28	274	*
f2cff6b1	275	* 0 4 8 12 16 20 24 28
d9b94f28 JL	276	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	277	*/
	278
25eedb2c JL	279	#define CONFIG_FSL_CADMUS
25eedb2c JL	280
d9b94f28	281	#define CADMUS_BASE_ADDR 0xf8000000
b76aef60	282	#ifdef CONFIG_PHYS_64BIT
	283	#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
	284	#else
fff80975	285	#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
b76aef60	286	#endif
fff80975	287	#define CONFIG_SYS_BR3_PRELIM \
fff80975	288	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) \| BR_PS_8 \| BR_V)
6d0f6bcf	289	#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
d9b94f28	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	292	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	293	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
f2cff6b1	294
25ddd1fb	295	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	296	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d9b94f28	297
6d0f6bcf	298	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
867b06f4	299	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
d9b94f28 JL	300
d9b94f28 JL	301	/* Serial Port */
f2cff6b1	302	#define CONFIG_CONS_INDEX 2
6d0f6bcf JCPV	303	#define CONFIG_SYS_NS16550_SERIAL
	304	#define CONFIG_SYS_NS16550_REG_SIZE 1
	305	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
d9b94f28	306
6d0f6bcf	307	#define CONFIG_SYS_BAUDRATE_TABLE \
d9b94f28 JL	308	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
d9b94f28 JL	309
6d0f6bcf JCPV	310	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	311	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
d9b94f28	312
20476726 JL	313	/*
	314	* I2C
	315	*/
00f792e0 HS	316	#define CONFIG_SYS_I2C
	317	#define CONFIG_SYS_I2C_FSL
	318	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	319	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	320	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	321	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
d9b94f28	322
e8d18541 TT	323	/* EEPROM */
e8d18541 TT	324	#define CONFIG_ID_EEPROM
6d0f6bcf JCPV	325	#define CONFIG_SYS_I2C_EEPROM_CCID
	326	#define CONFIG_SYS_ID_EEPROM
	327	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	328	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
e8d18541	329
d9b94f28 JL	330	/*
d9b94f28 JL	331	* General PCI
362dd830	332	* Memory space is mapped 1-1, but I/O space must start from 0.
d9b94f28	333	*/
5af0fdd8	334	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
b76aef60	335	#ifdef CONFIG_PHYS_64BIT
	336	#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
	337	#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
	338	#else
10795f42	339	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	340	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
b76aef60	341	#endif
6d0f6bcf	342	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	343	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	344	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
b76aef60	345	#ifdef CONFIG_PHYS_64BIT
	346	#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
	347	#else
6d0f6bcf	348	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
b76aef60	349	#endif
6d0f6bcf	350	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
d9b94f28	351
f2cff6b1	352	#ifdef CONFIG_PCIE1
f5fa8f36	353	#define CONFIG_SYS_PCIE1_NAME "Slot"
5af0fdd8	354	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
b76aef60	355	#ifdef CONFIG_PHYS_64BIT
	356	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
	357	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
	358	#else
10795f42	359	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8	360	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
b76aef60	361	#endif
6d0f6bcf	362	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	363	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
5f91ef6a	364	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
b76aef60	365	#ifdef CONFIG_PHYS_64BIT
	366	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
	367	#else
6d0f6bcf	368	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
b76aef60	369	#endif
6d0f6bcf	370	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
f2cff6b1	371	#endif
d9b94f28	372
41fb7e0f ZR	373	/*
	374	* RapidIO MMU
	375	*/
fff80975	376	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
b76aef60	377	#ifdef CONFIG_PHYS_64BIT
	378	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
	379	#else
fff80975	380	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
b76aef60	381	#endif
8b47d7ec	382	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
d9b94f28	383
7f3f2bd2 RV	384	#ifdef CONFIG_LEGACY
	385	#define BRIDGE_ID 17
	386	#define VIA_ID 2
	387	#else
	388	#define BRIDGE_ID 28
	389	#define VIA_ID 4
	390	#endif
	391
d9b94f28	392	#if defined(CONFIG_PCI)
d9b94f28 JL	393	#undef CONFIG_EEPRO100
	394	#undef CONFIG_TULIP
	395
867b06f4	396	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
f2cff6b1	397
d9b94f28 JL	398	#endif /* CONFIG_PCI */
d9b94f28 JL	399
d9b94f28 JL	400	#if defined(CONFIG_TSEC_ENET)
d9b94f28 JL	401
d9b94f28	402	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	403	#define CONFIG_TSEC1 1
	404	#define CONFIG_TSEC1_NAME "eTSEC0"
	405	#define CONFIG_TSEC2 1
	406	#define CONFIG_TSEC2_NAME "eTSEC1"
	407	#define CONFIG_TSEC3 1
	408	#define CONFIG_TSEC3_NAME "eTSEC2"
f2cff6b1	409	#define CONFIG_TSEC4
255a3577	410	#define CONFIG_TSEC4_NAME "eTSEC3"
d9b94f28 JL	411	#undef CONFIG_MPC85XX_FEC
d9b94f28 JL	412
d3701228	413	#define CONFIG_PHY_MARVELL
d3701228	414
d9b94f28 JL	415	#define TSEC1_PHY_ADDR 0
	416	#define TSEC2_PHY_ADDR 1
	417	#define TSEC3_PHY_ADDR 2
	418	#define TSEC4_PHY_ADDR 3
d9b94f28 JL	419
	420	#define TSEC1_PHYIDX 0
	421	#define TSEC2_PHYIDX 0
	422	#define TSEC3_PHYIDX 0
	423	#define TSEC4_PHYIDX 0
3a79013e AF	424	#define TSEC1_FLAGS TSEC_GIGABIT
	425	#define TSEC2_FLAGS TSEC_GIGABIT
	426	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	427	#define TSEC4_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
d9b94f28 JL	428
	429	/* Options are: eTSEC[0-3] */
	430	#define CONFIG_ETHPRIME "eTSEC0"
d9b94f28 JL	431	#endif /* CONFIG_TSEC_ENET */
	432
	433	/*
	434	* Environment
	435	*/
867b06f4	436	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
	437	#define CONFIG_ENV_ADDR 0xfff80000
	438	#else
	439	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	440	#endif
	441	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
0e8d1586	442	#define CONFIG_ENV_SIZE 0x2000
d9b94f28 JL	443
d9b94f28 JL	444	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	445	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
d9b94f28	446
659e2f67 JL	447	/*
	448	* BOOTP options
	449	*/
	450	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	451
d9b94f28 JL	452	#undef CONFIG_WATCHDOG /* watchdog disabled */
	453
	454	/*
	455	* Miscellaneous configurable options
	456	*/
6d0f6bcf	457	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
d9b94f28 JL	458
	459	/*
	460	* For booting Linux, the board info and command line data
a832ac41	461	* have to be in the first 64 MB of memory, since this is
d9b94f28 JL	462	* the maximum mapped by the Linux kernel during initialization.
d9b94f28 JL	463	*/
a832ac41 KG	464	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	465	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
d9b94f28	466
2835e518	467	#if defined(CONFIG_CMD_KGDB)
d9b94f28	468	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
d9b94f28 JL	469	#endif
	470
	471	/*
	472	* Environment Configuration
	473	*/
d9b94f28	474	#if defined(CONFIG_TSEC_ENET)
10327dc5	475	#define CONFIG_HAS_ETH0
d9b94f28	476	#define CONFIG_HAS_ETH1
d9b94f28	477	#define CONFIG_HAS_ETH2
09f3e09e	478	#define CONFIG_HAS_ETH3
d9b94f28 JL	479	#endif
d9b94f28 JL	480
f2cff6b1	481	#define CONFIG_IPADDR 192.168.1.253
d9b94f28	482
f2cff6b1	483	#define CONFIG_HOSTNAME unknown
8b3637c6	484	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	485	#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
f2cff6b1	486	#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
d9b94f28	487
f2cff6b1	488	#define CONFIG_SERVERIP 192.168.1.1
d9b94f28	489	#define CONFIG_GATEWAYIP 192.168.1.1
f2cff6b1	490	#define CONFIG_NETMASK 255.255.255.0
d9b94f28	491
f2cff6b1	492	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
d9b94f28	493
867b06f4	494	#define CONFIG_EXTRA_ENV_SETTINGS \
	495	"hwconfig=fsl_ddr:ecc=off\0" \
	496	"netdev=eth0\0" \
5368c55d	497	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
867b06f4	498	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	499	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	500	" +$filesize; " \
	501	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	502	" +$filesize; " \
	503	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	504	" $filesize; " \
	505	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	506	" +$filesize; " \
	507	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	508	" $filesize\0" \
867b06f4	509	"consoledev=ttyS1\0" \
	510	"ramdiskaddr=2000000\0" \
	511	"ramdiskfile=ramdisk.uboot\0" \
b24a4f62	512	"fdtaddr=1e00000\0" \
867b06f4	513	"fdtfile=mpc8548cds.dtb\0"
f2cff6b1 ES	514
	515	#define CONFIG_NFSBOOTCOMMAND \
	516	"setenv bootargs root=/dev/nfs rw " \
	517	"nfsroot=$serverip:$rootpath " \
d9b94f28	518	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
f2cff6b1 ES	519	"console=$consoledev,$baudrate $othbootargs;" \
f2cff6b1 ES	520	"tftp $loadaddr $bootfile;" \
4bf4abb8 ES	521	"tftp $fdtaddr $fdtfile;" \
4bf4abb8 ES	522	"bootm $loadaddr - $fdtaddr"
8272dc2f	523
d9b94f28	524	#define CONFIG_RAMBOOTCOMMAND \
f2cff6b1 ES	525	"setenv bootargs root=/dev/ram rw " \
	526	"console=$consoledev,$baudrate $othbootargs;" \
	527	"tftp $ramdiskaddr $ramdiskfile;" \
	528	"tftp $loadaddr $bootfile;" \
4bf4abb8 ES	529	"tftp $fdtaddr $fdtfile;" \
4bf4abb8 ES	530	"bootm $loadaddr $ramdiskaddr $fdtaddr"
f2cff6b1 ES	531
f2cff6b1 ES	532	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
d9b94f28 JL	533
d9b94f28 JL	534	#endif /* __CONFIG_H */