[people/ms/u-boot.git] / include / configs / MPC8560ADS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8560ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc. in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
#define CONFIG_MPC8560		1

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */
#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy() */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD.  */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)


/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
#undef  CONFIG_CONS_NONE	/* define if console on something else */
#define CONFIG_CONS_INDEX       1  /* which serial channel for console */

#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#ifdef CONFIG_TSEC_ENET

#ifndef CONFIG_MII
#define CONFIG_MII		1	/* MII PHY management */
#endif
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */

#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX      2       /* which channel for ether */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif					/* CONFIG_ETHER_INDEX */

#ifndef CONFIG_MII
#define CONFIG_MII		1	/* MII PHY management */
#endif

#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */

/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */
#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE	MDIO_DECLARE

#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
#define MDIO_READ	((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

#define MIIDELAY	udelay(1)

#endif


/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_IS_IN_FLASH	1
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif


/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
	"netdev=eth0\0"							\
	"consoledev=ttyCPM\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=your.ramdisk.u-boot\0"				\
	"fdtaddr=400000\0"						\
	"fdtfile=mpc8560ads.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	7	*/
42d1f039 WD	8
0ac6f8b7 WD	9	/*
	10	* mpc8560ads board configuration file
	11	*
	12	* Please refer to doc/README.mpc85xx for more info.
	13	*
	14	* Make sure you change the MAC address and other network params first,
92ac5208	15	* search for CONFIG_SERVERIP, etc. in this file.
42d1f039 WD	16	*/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
	21	/* High Level Configuration Options */
0ac6f8b7 WD	22	#define CONFIG_BOOKE 1 /* BOOKE */
0ac6f8b7 WD	23	#define CONFIG_E500 1 /* BOOKE e500 family */
9c4c5ae3	24	#define CONFIG_CPM2 1 /* has CPM2 */
0ac6f8b7	25	#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
f060054d	26	#define CONFIG_MPC8560 1
0ac6f8b7	27
2ae18241 WD	28	/*
	29	* default CCARBAR is at 0xff700000
	30	* assume U-Boot is less than 0.5MB
	31	*/
	32	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	33
0ac6f8b7	34	#define CONFIG_PCI
842033e6	35	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	36	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	37	#define CONFIG_TSEC_ENET /* tsec ethernet support */
ccc091aa	38	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
42d1f039	39	#define CONFIG_ENV_OVERWRITE
7232a272	40	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
004eca0c	41	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
42d1f039	42
0ac6f8b7 WD	43	/*
	44	* sysclk for MPC85xx
	45	*
	46	* Two valid values are:
	47	* 33000000
	48	* 66000000
	49	*
	50	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	51	* is likely the desired value here, so that is now the default.
	52	* The board, however, can run at 66MHz. In any event, this value
	53	* must match the settings of some switches. Details can be found
	54	* in the README.mpc85xxads.
0ac6f8b7 WD	55	*/
0ac6f8b7 WD	56
9aea9530 WD	57	#ifndef CONFIG_SYS_CLK_FREQ
9aea9530 WD	58	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	59	#endif
42d1f039 WD	60
9aea9530	61
0ac6f8b7 WD	62	/*
	63	* These can be toggled for performance analysis, otherwise use default.
	64	*/
	65	#define CONFIG_L2_CACHE /* toggle L2 cache */
	66	#define CONFIG_BTB /* toggle branch predition */
42d1f039	67
6d0f6bcf	68	#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
0ac6f8b7	69
6d0f6bcf JCPV	70	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	71	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	72
e46fedfe TT	73	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	74	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	75
8b625114	76	/* DDR Setup */
5614e71b	77	#define CONFIG_SYS_FSL_DDR1
8b625114 JL	78	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	79	#define CONFIG_DDR_SPD
	80	#undef CONFIG_FSL_DDR_INTERACTIVE
	81
	82	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	83
6d0f6bcf JCPV	84	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	85	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	86
8b625114 JL	87	#define CONFIG_NUM_DDR_CONTROLLERS 1
	88	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	89	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
9aea9530	90
8b625114 JL	91	/* I2C addresses of SPD EEPROMs */
8b625114 JL	92	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
9aea9530	93
8b625114	94	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	95	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	96	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	97	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	98	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	99	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	100	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	101	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	102	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	103
0ac6f8b7 WD	104	/*
	105	* SDRAM on the Local Bus
	106	*/
6d0f6bcf JCPV	107	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	108	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	109
6d0f6bcf JCPV	110	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	111	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	112
6d0f6bcf JCPV	113	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	114	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	115	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	116	#undef CONFIG_SYS_FLASH_CHECKSUM
	117	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	118	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	119
14d0a02a	120	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	121
6d0f6bcf JCPV	122	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	123	#define CONFIG_SYS_RAMBOOT
42d1f039	124	#else
6d0f6bcf	125	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	126	#endif
42d1f039 WD	127
00b1883a	128	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	129	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	130	#define CONFIG_SYS_FLASH_EMPTY_INFO
0ac6f8b7 WD	131
0ac6f8b7 WD	132	#undef CONFIG_CLOCKS_IN_MHZ
42d1f039	133
42d1f039	134
0ac6f8b7 WD	135	/*
	136	* Local Bus Definitions
	137	*/
	138
	139	/*
	140	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	141	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	142	*
	143	* For BR2, need:
	144	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	145	* port-size = 32-bits = BR2[19:20] = 11
	146	* no parity checking = BR2[21:22] = 00
	147	* SDRAM for MSEL = BR2[24:26] = 011
	148	* Valid = BR[31] = 1
	149	*
	150	* 0 4 8 12 16 20 24 28
	151	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	152	*
6d0f6bcf	153	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	154	* FIXME: the top 17 bits of BR2.
	155	*/
	156
6d0f6bcf	157	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	158
0ac6f8b7 WD	159	/*
6d0f6bcf	160	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	161	*
	162	* For OR2, need:
	163	* 64MB mask for AM, OR2[0:7] = 1111 1100
	164	* XAM, OR2[17:18] = 11
	165	* 9 columns OR2[19-21] = 010
	166	* 13 rows OR2[23-25] = 100
	167	* EAD set for extra time OR[31] = 1
	168	*
	169	* 0 4 8 12 16 20 24 28
	170	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	171	*/
	172
6d0f6bcf	173	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	174
6d0f6bcf JCPV	175	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	176	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	177	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	178	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	179
b0fe93ed KG	180	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	181	\| LSDMR_RFCR5 \
	182	\| LSDMR_PRETOACT3 \
	183	\| LSDMR_ACTTORW3 \
	184	\| LSDMR_BL8 \
	185	\| LSDMR_WRC2 \
	186	\| LSDMR_CL3 \
	187	\| LSDMR_RFEN \
0ac6f8b7 WD	188	)
	189
	190	/*
	191	* SDRAM Controller configuration sequence.
	192	*/
b0fe93ed KG	193	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	194	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	195	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	196	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	197	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	198
42d1f039	199
9aea9530 WD	200	/*
	201	* 32KB, 8-bit wide for ADS config reg
	202	*/
6d0f6bcf JCPV	203	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	204	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	205	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	208	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	209	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	210
25ddd1fb	211	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	212	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	215	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	216
42d1f039 WD	217	/* Serial Port */
0ac6f8b7 WD	218	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	219	#undef CONFIG_CONS_NONE /* define if console on something else */
	220	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
42d1f039	221
53677ef1	222	#define CONFIG_BAUDRATE 115200
42d1f039	223
6d0f6bcf	224	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	225	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	226
	227	/* Use the HUSH parser */
6d0f6bcf JCPV	228	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	229	#ifdef CONFIG_SYS_HUSH_PARSER
42d1f039 WD	230	#endif
42d1f039 WD	231
0e16387d	232	/* pass open firmware flat tree */
5ce71580 KG	233	#define CONFIG_OF_LIBFDT 1
	234	#define CONFIG_OF_BOARD_SETUP 1
	235	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0e16387d	236
20476726 JL	237	/*
	238	* I2C
	239	*/
00f792e0 HS	240	#define CONFIG_SYS_I2C
	241	#define CONFIG_SYS_I2C_FSL
	242	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	243	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	244	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	245	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
42d1f039	246
0ac6f8b7	247	/* RapidIO MMU */
5af0fdd8	248	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	249	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	250	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	251	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	252
	253	/*
	254	* General PCI
362dd830	255	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	256	*/
5af0fdd8	257	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	258	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	259	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	260	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	261	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	262	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	263	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	264	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
0ac6f8b7 WD	265
0ac6f8b7 WD	266	#if defined(CONFIG_PCI)
42d1f039	267
53677ef1	268	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7 WD	269
0ac6f8b7 WD	270	#undef CONFIG_EEPRO100
42d1f039	271	#undef CONFIG_TULIP
0ac6f8b7 WD	272
	273	#if !defined(CONFIG_PCI_PNP)
	274	#define PCI_ENET0_IOADDR 0xe0000000
	275	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	276	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	277	#endif
0ac6f8b7 WD	278
0ac6f8b7 WD	279	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	280	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	281
	282	#endif /* CONFIG_PCI */
	283
	284
ccc091aa	285	#ifdef CONFIG_TSEC_ENET
0ac6f8b7	286
ccc091aa	287	#ifndef CONFIG_MII
0ac6f8b7	288	#define CONFIG_MII 1 /* MII PHY management */
ccc091aa	289	#endif
255a3577 KP	290	#define CONFIG_TSEC1 1
	291	#define CONFIG_TSEC1_NAME "TSEC0"
	292	#define CONFIG_TSEC2 1
	293	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	294	#define TSEC1_PHY_ADDR 0
	295	#define TSEC2_PHY_ADDR 1
	296	#define TSEC1_PHYIDX 0
	297	#define TSEC2_PHYIDX 0
3a79013e AF	298	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	299	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	300
	301	/* Options are: TSEC[0-1] */
	302	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7	303
ccc091aa AF	304	#endif /* CONFIG_TSEC_ENET */
ccc091aa AF	305
53677ef1	306	#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
0ac6f8b7	307
53677ef1	308	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0ac6f8b7 WD	309	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
	310
	311	#if (CONFIG_ETHER_INDEX == 2)
42d1f039 WD	312	/*
	313	* - Rx-CLK is CLK13
	314	* - Tx-CLK is CLK14
	315	* - Select bus for bd/buffers
	316	* - Full duplex
	317	*/
d4590da4 MF	318	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
d4590da4 MF	319	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
6d0f6bcf JCPV	320	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	321	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
42d1f039	322	#define FETH2_RST 0x01
0ac6f8b7	323	#elif (CONFIG_ETHER_INDEX == 3)
42d1f039 WD	324	/* need more definitions here for FE3 */
42d1f039 WD	325	#define FETH3_RST 0x80
53677ef1	326	#endif /* CONFIG_ETHER_INDEX */
0ac6f8b7	327
ccc091aa AF	328	#ifndef CONFIG_MII
	329	#define CONFIG_MII 1 /* MII PHY management */
	330	#endif
	331
0ac6f8b7 WD	332	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
0ac6f8b7 WD	333
42d1f039 WD	334	/*
	335	* GPIO pins used for bit-banged MII communications
	336	*/
	337	#define MDIO_PORT 2 /* Port C */
be225442 LCM	338	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	339	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	340	#define MDC_DECLARE MDIO_DECLARE
	341
42d1f039 WD	342	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	343	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	344	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	345
	346	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	347	else iop->pdat &= ~0x00400000
	348
	349	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	350	else iop->pdat &= ~0x00200000
	351
	352	#define MIIDELAY udelay(1)
0ac6f8b7	353
42d1f039 WD	354	#endif
42d1f039 WD	355
0ac6f8b7 WD	356
	357	/*
	358	* Environment
	359	*/
6d0f6bcf	360	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	361	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	362	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	363	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	364	#define CONFIG_ENV_SIZE 0x2000
42d1f039	365	#else
6d0f6bcf	366	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	367	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	368	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	369	#define CONFIG_ENV_SIZE 0x2000
42d1f039 WD	370	#endif
42d1f039 WD	371
0ac6f8b7	372	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	373	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	374
659e2f67 JL	375	/*
	376	* BOOTP options
	377	*/
	378	#define CONFIG_BOOTP_BOOTFILESIZE
	379	#define CONFIG_BOOTP_BOOTPATH
	380	#define CONFIG_BOOTP_GATEWAY
	381	#define CONFIG_BOOTP_HOSTNAME
	382
	383
2835e518 JL	384	/*
	385	* Command line configuration.
	386	*/
	387	#include <config_cmd_default.h>
	388
	389	#define CONFIG_CMD_PING
	390	#define CONFIG_CMD_I2C
82ac8c97	391	#define CONFIG_CMD_ELF
1c9aa76b	392	#define CONFIG_CMD_IRQ
199e262e	393	#define CONFIG_CMD_REGINFO
2835e518 JL	394
	395	#if defined(CONFIG_PCI)
	396	#define CONFIG_CMD_PCI
	397	#endif
	398
	399	#if defined(CONFIG_ETHER_ON_FCC)
	400	#define CONFIG_CMD_MII
	401	#endif
	402
6d0f6bcf	403	#if defined(CONFIG_SYS_RAMBOOT)
bdab39d3	404	#undef CONFIG_CMD_SAVEENV
2835e518	405	#undef CONFIG_CMD_LOADS
42d1f039	406	#endif
0ac6f8b7	407
42d1f039	408
0ac6f8b7	409	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	410
	411	/*
	412	* Miscellaneous configurable options
	413	*/
6d0f6bcf	414	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	415	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	416	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	417	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
0ac6f8b7	418
2835e518	419	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	420	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	421	#else
6d0f6bcf	422	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	423	#endif
0ac6f8b7	424
6d0f6bcf JCPV	425	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	426	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	427	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42d1f039 WD	428
	429	/*
	430	* For booting Linux, the board info and command line data
a832ac41	431	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	432	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	433	*/
a832ac41 KG	434	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	435	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	436
2835e518	437	#if defined(CONFIG_CMD_KGDB)
42d1f039	438	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	439	#endif
42d1f039 WD	440
9aea9530 WD	441
	442	/*
	443	* Environment Configuration
	444	*/
42d1f039	445	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	446	#define CONFIG_HAS_ETH0
e2ffd59b	447	#define CONFIG_HAS_ETH1
e2ffd59b	448	#define CONFIG_HAS_ETH2
5ce71580	449	#define CONFIG_HAS_ETH3
42d1f039 WD	450	#endif
42d1f039 WD	451
0ac6f8b7 WD	452	#define CONFIG_IPADDR 192.168.1.253
	453
	454	#define CONFIG_HOSTNAME unknown
8b3637c6	455	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	456	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	457
	458	#define CONFIG_SERVERIP 192.168.1.1
	459	#define CONFIG_GATEWAYIP 192.168.1.1
	460	#define CONFIG_NETMASK 255.255.255.0
	461
	462	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	463
9aea9530	464	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
0ac6f8b7 WD	465	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	466
	467	#define CONFIG_BAUDRATE 115200
	468
9aea9530	469	#define CONFIG_EXTRA_ENV_SETTINGS \
6b44a44e AF	470	"netdev=eth0\0" \
	471	"consoledev=ttyCPM\0" \
	472	"ramdiskaddr=1000000\0" \
	473	"ramdiskfile=your.ramdisk.u-boot\0" \
	474	"fdtaddr=400000\0" \
	475	"fdtfile=mpc8560ads.dtb\0"
0ac6f8b7	476
9aea9530	477	#define CONFIG_NFSBOOTCOMMAND \
6b44a44e AF	478	"setenv bootargs root=/dev/nfs rw " \
	479	"nfsroot=$serverip:$rootpath " \
	480	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	481	"console=$consoledev,$baudrate $othbootargs;" \
	482	"tftp $loadaddr $bootfile;" \
	483	"tftp $fdtaddr $fdtfile;" \
	484	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	485
0ac6f8b7 WD	486	#define CONFIG_RAMBOOTCOMMAND \
6b44a44e AF	487	"setenv bootargs root=/dev/ram rw " \
	488	"console=$consoledev,$baudrate $othbootargs;" \
	489	"tftp $ramdiskaddr $ramdiskfile;" \
	490	"tftp $loadaddr $bootfile;" \
	491	"tftp $fdtaddr $fdtfile;" \
	492	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	493
0ac6f8b7 WD	494	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	495
42d1f039 WD	496	#endif /* __CONFIG_H */