[people/ms/u-boot.git] / include / configs / MPC8560ADS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8560ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc. in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_CPM2		1	/* has CPM2 */

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */
#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy() */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD.  */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)

/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
#undef  CONFIG_CONS_NONE	/* define if console on something else */
#define CONFIG_CONS_INDEX       1  /* which serial channel for console */

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#ifdef CONFIG_TSEC_ENET

#ifndef CONFIG_MII
#define CONFIG_MII		1	/* MII PHY management */
#endif
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */

#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX      2       /* which channel for ether */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif					/* CONFIG_ETHER_INDEX */

#ifndef CONFIG_MII
#define CONFIG_MII		1	/* MII PHY management */
#endif

#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */

/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */
#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE	MDIO_DECLARE

#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
#define MDIO_READ	((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

#define MIIDELAY	udelay(1)

#endif

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_ETHER_ON_FCC)
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
	"netdev=eth0\0"							\
	"consoledev=ttyCPM\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=your.ramdisk.u-boot\0"				\
	"fdtaddr=400000\0"						\
	"fdtfile=mpc8560ads.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	7	*/
42d1f039 WD	8
0ac6f8b7 WD	9	/*
	10	* mpc8560ads board configuration file
	11	*
	12	* Please refer to doc/README.mpc85xx for more info.
	13	*
	14	* Make sure you change the MAC address and other network params first,
92ac5208	15	* search for CONFIG_SERVERIP, etc. in this file.
42d1f039 WD	16	*/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
	21	/* High Level Configuration Options */
9c4c5ae3	22	#define CONFIG_CPM2 1 /* has CPM2 */
0ac6f8b7	23
2ae18241 WD	24	/*
	25	* default CCARBAR is at 0xff700000
	26	* assume U-Boot is less than 0.5MB
	27	*/
	28	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	29
842033e6	30	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	31	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	32	#define CONFIG_TSEC_ENET /* tsec ethernet support */
ccc091aa	33	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
42d1f039	34	#define CONFIG_ENV_OVERWRITE
004eca0c	35	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
42d1f039	36
0ac6f8b7 WD	37	/*
	38	* sysclk for MPC85xx
	39	*
	40	* Two valid values are:
	41	* 33000000
	42	* 66000000
	43	*
	44	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	45	* is likely the desired value here, so that is now the default.
	46	* The board, however, can run at 66MHz. In any event, this value
	47	* must match the settings of some switches. Details can be found
	48	* in the README.mpc85xxads.
0ac6f8b7 WD	49	*/
0ac6f8b7 WD	50
9aea9530 WD	51	#ifndef CONFIG_SYS_CLK_FREQ
9aea9530 WD	52	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	53	#endif
42d1f039 WD	54
0ac6f8b7 WD	55	/*
	56	* These can be toggled for performance analysis, otherwise use default.
	57	*/
	58	#define CONFIG_L2_CACHE /* toggle L2 cache */
	59	#define CONFIG_BTB /* toggle branch predition */
42d1f039	60
6d0f6bcf	61	#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
0ac6f8b7	62
6d0f6bcf JCPV	63	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	64	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	65
e46fedfe TT	66	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	67	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	68
8b625114	69	/* DDR Setup */
8b625114 JL	70	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	71	#define CONFIG_DDR_SPD
	72	#undef CONFIG_FSL_DDR_INTERACTIVE
	73
	74	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	75
6d0f6bcf JCPV	76	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	77	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	78
8b625114 JL	79	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
8b625114 JL	80	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
9aea9530	81
8b625114 JL	82	/* I2C addresses of SPD EEPROMs */
8b625114 JL	83	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
9aea9530	84
8b625114	85	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	86	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	87	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	88	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	89	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	90	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	91	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	92	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	93	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	94
0ac6f8b7 WD	95	/*
	96	* SDRAM on the Local Bus
	97	*/
6d0f6bcf JCPV	98	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	99	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	100
6d0f6bcf JCPV	101	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	102	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	105	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	106	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	107	#undef CONFIG_SYS_FLASH_CHECKSUM
	108	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	109	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	110
14d0a02a	111	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	112
6d0f6bcf JCPV	113	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	114	#define CONFIG_SYS_RAMBOOT
42d1f039	115	#else
6d0f6bcf	116	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	117	#endif
42d1f039 WD	118
00b1883a	119	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	121	#define CONFIG_SYS_FLASH_EMPTY_INFO
0ac6f8b7 WD	122
0ac6f8b7 WD	123	#undef CONFIG_CLOCKS_IN_MHZ
42d1f039	124
0ac6f8b7 WD	125	/*
	126	* Local Bus Definitions
	127	*/
	128
	129	/*
	130	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	131	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	132	*
	133	* For BR2, need:
	134	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	135	* port-size = 32-bits = BR2[19:20] = 11
	136	* no parity checking = BR2[21:22] = 00
	137	* SDRAM for MSEL = BR2[24:26] = 011
	138	* Valid = BR[31] = 1
	139	*
	140	* 0 4 8 12 16 20 24 28
	141	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	142	*
6d0f6bcf	143	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	144	* FIXME: the top 17 bits of BR2.
	145	*/
	146
6d0f6bcf	147	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	148
0ac6f8b7 WD	149	/*
6d0f6bcf	150	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	151	*
	152	* For OR2, need:
	153	* 64MB mask for AM, OR2[0:7] = 1111 1100
	154	* XAM, OR2[17:18] = 11
	155	* 9 columns OR2[19-21] = 010
	156	* 13 rows OR2[23-25] = 100
	157	* EAD set for extra time OR[31] = 1
	158	*
	159	* 0 4 8 12 16 20 24 28
	160	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	161	*/
	162
6d0f6bcf	163	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	164
6d0f6bcf JCPV	165	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	166	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	167	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	168	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	169
b0fe93ed KG	170	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	171	\| LSDMR_RFCR5 \
	172	\| LSDMR_PRETOACT3 \
	173	\| LSDMR_ACTTORW3 \
	174	\| LSDMR_BL8 \
	175	\| LSDMR_WRC2 \
	176	\| LSDMR_CL3 \
	177	\| LSDMR_RFEN \
0ac6f8b7 WD	178	)
	179
	180	/*
	181	* SDRAM Controller configuration sequence.
	182	*/
b0fe93ed KG	183	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	184	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	185	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	186	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	187	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	188
9aea9530 WD	189	/*
	190	* 32KB, 8-bit wide for ADS config reg
	191	*/
6d0f6bcf JCPV	192	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	193	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	194	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	197	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	198	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	199
25ddd1fb	200	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	201	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	204	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	205
42d1f039 WD	206	/* Serial Port */
0ac6f8b7 WD	207	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	208	#undef CONFIG_CONS_NONE /* define if console on something else */
	209	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
42d1f039	210
6d0f6bcf	211	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	212	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
42d1f039 WD	213
20476726 JL	214	/*
	215	* I2C
	216	*/
00f792e0 HS	217	#define CONFIG_SYS_I2C
	218	#define CONFIG_SYS_I2C_FSL
	219	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	220	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	221	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	222	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
42d1f039	223
0ac6f8b7	224	/* RapidIO MMU */
5af0fdd8	225	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	226	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	227	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	228	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	229
	230	/*
	231	* General PCI
362dd830	232	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	233	*/
5af0fdd8	234	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	235	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	236	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	237	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	238	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	239	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	240	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	241	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
0ac6f8b7 WD	242
0ac6f8b7 WD	243	#if defined(CONFIG_PCI)
0ac6f8b7	244	#undef CONFIG_EEPRO100
42d1f039	245	#undef CONFIG_TULIP
0ac6f8b7 WD	246
	247	#if !defined(CONFIG_PCI_PNP)
	248	#define PCI_ENET0_IOADDR 0xe0000000
	249	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	250	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	251	#endif
0ac6f8b7 WD	252
0ac6f8b7 WD	253	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	254	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	255
	256	#endif /* CONFIG_PCI */
	257
ccc091aa	258	#ifdef CONFIG_TSEC_ENET
0ac6f8b7	259
ccc091aa	260	#ifndef CONFIG_MII
0ac6f8b7	261	#define CONFIG_MII 1 /* MII PHY management */
ccc091aa	262	#endif
255a3577 KP	263	#define CONFIG_TSEC1 1
	264	#define CONFIG_TSEC1_NAME "TSEC0"
	265	#define CONFIG_TSEC2 1
	266	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	267	#define TSEC1_PHY_ADDR 0
	268	#define TSEC2_PHY_ADDR 1
	269	#define TSEC1_PHYIDX 0
	270	#define TSEC2_PHYIDX 0
3a79013e AF	271	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	272	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	273
	274	/* Options are: TSEC[0-1] */
	275	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7	276
ccc091aa AF	277	#endif /* CONFIG_TSEC_ENET */
ccc091aa AF	278
53677ef1	279	#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
0ac6f8b7	280
53677ef1	281	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0ac6f8b7 WD	282	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
	283
	284	#if (CONFIG_ETHER_INDEX == 2)
42d1f039 WD	285	/*
	286	* - Rx-CLK is CLK13
	287	* - Tx-CLK is CLK14
	288	* - Select bus for bd/buffers
	289	* - Full duplex
	290	*/
d4590da4 MF	291	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
d4590da4 MF	292	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
6d0f6bcf JCPV	293	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	294	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
42d1f039	295	#define FETH2_RST 0x01
0ac6f8b7	296	#elif (CONFIG_ETHER_INDEX == 3)
42d1f039 WD	297	/* need more definitions here for FE3 */
42d1f039 WD	298	#define FETH3_RST 0x80
53677ef1	299	#endif /* CONFIG_ETHER_INDEX */
0ac6f8b7	300
ccc091aa AF	301	#ifndef CONFIG_MII
	302	#define CONFIG_MII 1 /* MII PHY management */
	303	#endif
	304
0ac6f8b7 WD	305	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
0ac6f8b7 WD	306
42d1f039 WD	307	/*
	308	* GPIO pins used for bit-banged MII communications
	309	*/
	310	#define MDIO_PORT 2 /* Port C */
be225442 LCM	311	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	312	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	313	#define MDC_DECLARE MDIO_DECLARE
	314
42d1f039 WD	315	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	316	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	317	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	318
	319	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	320	else iop->pdat &= ~0x00400000
	321
	322	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	323	else iop->pdat &= ~0x00200000
	324
	325	#define MIIDELAY udelay(1)
0ac6f8b7	326
42d1f039 WD	327	#endif
42d1f039 WD	328
0ac6f8b7 WD	329	/*
	330	* Environment
	331	*/
6d0f6bcf	332	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf	333	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	334	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	335	#define CONFIG_ENV_SIZE 0x2000
42d1f039	336	#else
6d0f6bcf	337	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	338	#define CONFIG_ENV_SIZE 0x2000
42d1f039 WD	339	#endif
42d1f039 WD	340
0ac6f8b7	341	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	342	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	343
659e2f67 JL	344	/*
	345	* BOOTP options
	346	*/
	347	#define CONFIG_BOOTP_BOOTFILESIZE
	348	#define CONFIG_BOOTP_BOOTPATH
	349	#define CONFIG_BOOTP_GATEWAY
	350	#define CONFIG_BOOTP_HOSTNAME
	351
2835e518 JL	352	/*
	353	* Command line configuration.
	354	*/
199e262e	355	#define CONFIG_CMD_REGINFO
2835e518 JL	356
	357	#if defined(CONFIG_PCI)
	358	#define CONFIG_CMD_PCI
	359	#endif
	360
	361	#if defined(CONFIG_ETHER_ON_FCC)
2835e518 JL	362	#endif
2835e518 JL	363
0ac6f8b7	364	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	365
	366	/*
	367	* Miscellaneous configurable options
	368	*/
6d0f6bcf	369	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	370	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	371	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	372	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
0ac6f8b7	373
2835e518	374	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	375	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	376	#else
6d0f6bcf	377	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	378	#endif
0ac6f8b7	379
6d0f6bcf JCPV	380	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	381	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	382	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42d1f039 WD	383
	384	/*
	385	* For booting Linux, the board info and command line data
a832ac41	386	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	387	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	388	*/
a832ac41 KG	389	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	390	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	391
2835e518	392	#if defined(CONFIG_CMD_KGDB)
42d1f039	393	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	394	#endif
42d1f039 WD	395
9aea9530 WD	396	/*
	397	* Environment Configuration
	398	*/
42d1f039	399	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	400	#define CONFIG_HAS_ETH0
e2ffd59b	401	#define CONFIG_HAS_ETH1
e2ffd59b	402	#define CONFIG_HAS_ETH2
5ce71580	403	#define CONFIG_HAS_ETH3
42d1f039 WD	404	#endif
42d1f039 WD	405
0ac6f8b7 WD	406	#define CONFIG_IPADDR 192.168.1.253
	407
	408	#define CONFIG_HOSTNAME unknown
8b3637c6	409	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	410	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	411
	412	#define CONFIG_SERVERIP 192.168.1.1
	413	#define CONFIG_GATEWAYIP 192.168.1.1
	414	#define CONFIG_NETMASK 255.255.255.0
	415
	416	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	417
0ac6f8b7 WD	418	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
0ac6f8b7 WD	419
9aea9530	420	#define CONFIG_EXTRA_ENV_SETTINGS \
6b44a44e AF	421	"netdev=eth0\0" \
	422	"consoledev=ttyCPM\0" \
	423	"ramdiskaddr=1000000\0" \
	424	"ramdiskfile=your.ramdisk.u-boot\0" \
	425	"fdtaddr=400000\0" \
	426	"fdtfile=mpc8560ads.dtb\0"
0ac6f8b7	427
9aea9530	428	#define CONFIG_NFSBOOTCOMMAND \
6b44a44e AF	429	"setenv bootargs root=/dev/nfs rw " \
	430	"nfsroot=$serverip:$rootpath " \
	431	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	432	"console=$consoledev,$baudrate $othbootargs;" \
	433	"tftp $loadaddr $bootfile;" \
	434	"tftp $fdtaddr $fdtfile;" \
	435	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	436
0ac6f8b7 WD	437	#define CONFIG_RAMBOOTCOMMAND \
6b44a44e AF	438	"setenv bootargs root=/dev/ram rw " \
	439	"console=$consoledev,$baudrate $othbootargs;" \
	440	"tftp $ramdiskaddr $ramdiskfile;" \
	441	"tftp $loadaddr $bootfile;" \
	442	"tftp $fdtaddr $fdtfile;" \
	443	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	444
0ac6f8b7 WD	445	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	446
42d1f039 WD	447	#endif /* __CONFIG_H */