projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 765547dc | 1 | /* |
| e5fe96b1 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
| 765547dc | 3 | * |
| 3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 765547dc HW |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * mpc8569mds board configuration file | |
| 9 | */ | |
| 10 | #ifndef __CONFIG_H | |
| 11 | #define __CONFIG_H | |
| 12 | ||
| 765547dc HW |
13 | #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ |
| 14 | ||
| e5fe96b1 KG |
15 | #define CONFIG_SYS_SRIO |
| 16 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
| 17 | ||
| 765547dc HW |
18 | #define CONFIG_PCIE1 1 /* PCIE controller */ |
| 19 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
| 842033e6 | 20 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
| 765547dc HW |
21 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 22 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
| 23 | #define CONFIG_QE /* Enable QE */ | |
| 24 | #define CONFIG_ENV_OVERWRITE | |
| 765547dc | 25 | |
| 765547dc HW |
26 | #ifndef __ASSEMBLY__ |
| 27 | extern unsigned long get_clock_freq(void); | |
| 28 | #endif | |
| 29 | /* Replace a call to get_clock_freq (after it is implemented)*/ | |
| 67351049 DL |
30 | #define CONFIG_SYS_CLK_FREQ 66666666 |
| 31 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
| 765547dc | 32 | |
| d24f2d32 | 33 | #ifdef CONFIG_ATM |
| c95d541e LY |
34 | #define CONFIG_PQ_MDS_PIB |
| 35 | #define CONFIG_PQ_MDS_PIB_ATM | |
| 36 | #endif | |
| 37 | ||
| 765547dc HW |
38 | /* |
| 39 | * These can be toggled for performance analysis, otherwise use default. | |
| 40 | */ | |
| 41 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 42 | #define CONFIG_BTB /* toggle branch predition */ | |
| 43 | ||
| 2ae18241 WD |
44 | #ifndef CONFIG_SYS_TEXT_BASE |
| 45 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
| 674ef7bd LY |
46 | #endif |
| 47 | ||
| 96196a1f HW |
48 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 49 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 50 | #endif | |
| 51 | ||
| 765547dc HW |
52 | /* |
| 53 | * Only possible on E500 Version 2 or newer cores. | |
| 54 | */ | |
| 55 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 56 | ||
| 3aed5507 | 57 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
| 7f52ed5e | 58 | #define CONFIG_HWCONFIG |
| 765547dc HW |
59 | |
| 60 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 61 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 62 | ||
| 674ef7bd LY |
63 | /* |
| 64 | * Config the L2 Cache as L2 SRAM | |
| 65 | */ | |
| 66 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 67 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 68 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
| 69 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 70 | ||
| e46fedfe TT |
71 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 72 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 765547dc | 73 | |
| 8d22ddca | 74 | #if defined(CONFIG_NAND_SPL) |
| e46fedfe | 75 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| 674ef7bd LY |
76 | #endif |
| 77 | ||
| 765547dc | 78 | /* DDR Setup */ |
| 765547dc HW |
79 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 80 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
| 81 | #define CONFIG_DDR_SPD | |
| 765547dc HW |
82 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 83 | ||
| 84 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 85 | ||
| 86 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 87 | /* DDR is system memory*/ | |
| 88 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 89 | ||
| 765547dc HW |
90 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 91 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 92 | ||
| 93 | /* I2C addresses of SPD EEPROMs */ | |
| c39f44dc | 94 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| 765547dc HW |
95 | |
| 96 | /* These are used when DDR doesn't use SPD. */ | |
| 97 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ | |
| 98 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
| 99 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
| 100 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 101 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
| 102 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 | |
| 103 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 | |
| 104 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 | |
| 105 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 | |
| 106 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 | |
| 107 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 | |
| 108 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 | |
| 109 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 110 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 | |
| 111 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
| 112 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
| 113 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
| 114 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 | |
| 115 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 | |
| 116 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 | |
| 117 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 118 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 119 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ | |
| 120 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
| 121 | ||
| 122 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 123 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 124 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
| 125 | ||
| 126 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 127 | ||
| 128 | /* | |
| 129 | * Local Bus Definitions | |
| 130 | */ | |
| 131 | ||
| 132 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ | |
| 133 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 134 | ||
| 135 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 | |
| 136 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE | |
| 137 | ||
| 138 | /*Chip select 0 - Flash*/ | |
| 674ef7bd LY |
139 | #define CONFIG_FLASH_BR_PRELIM 0xfe000801 |
| 140 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 | |
| 765547dc | 141 | |
| 399b53cb | 142 | /*Chip select 1 - BCSR*/ |
| 765547dc HW |
143 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
| 144 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
| 145 | ||
| 399b53cb HW |
146 | /*Chip select 4 - PIB*/ |
| 147 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 | |
| 148 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
| 149 | ||
| 150 | /*Chip select 5 - PIB*/ | |
| 151 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 | |
| 152 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 | |
| 153 | ||
| 765547dc HW |
154 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 155 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
| 156 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 157 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 158 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 159 | ||
| 674ef7bd | 160 | #undef CONFIG_SYS_RAMBOOT |
| 674ef7bd | 161 | |
| 765547dc HW |
162 | #define CONFIG_FLASH_CFI_DRIVER |
| 163 | #define CONFIG_SYS_FLASH_CFI | |
| 164 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 165 | ||
| a29155e1 | 166 | /* Chip select 3 - NAND */ |
| 674ef7bd | 167 | #ifndef CONFIG_NAND_SPL |
| a29155e1 | 168 | #define CONFIG_SYS_NAND_BASE 0xFC000000 |
| 674ef7bd LY |
169 | #else |
| 170 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
| 171 | #endif | |
| 172 | ||
| 173 | /* NAND boot: 4K NAND loader config */ | |
| 174 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 175 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
| 176 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
| 177 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
| 178 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
| 179 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 180 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 181 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 182 | ||
| a29155e1 AV |
183 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 184 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } | |
| 185 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| a29155e1 AV |
186 | #define CONFIG_CMD_NAND 1 |
| 187 | #define CONFIG_NAND_FSL_ELBC 1 | |
| 188 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| a3055c58 | 189 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ |
| a29155e1 AV |
190 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 191 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 192 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 193 | | BR_V) /* valid */ | |
| a3055c58 | 194 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
| a29155e1 AV |
195 | | OR_FCM_CSCT \ |
| 196 | | OR_FCM_CST \ | |
| 197 | | OR_FCM_CHT \ | |
| 198 | | OR_FCM_SCY_1 \ | |
| 199 | | OR_FCM_TRLX \ | |
| 200 | | OR_FCM_EHTR) | |
| 674ef7bd | 201 | |
| 674ef7bd LY |
202 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 203 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| a3055c58 MM |
204 | #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 205 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 765547dc | 206 | |
| 765547dc HW |
207 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
| 208 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ | |
| 209 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
| 210 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
| 211 | ||
| 212 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 213 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
| 553f0982 | 214 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| 765547dc | 215 | |
| 765547dc | 216 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 25ddd1fb | 217 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 765547dc HW |
218 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 219 | ||
| 220 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| fb279490 | 221 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
| 765547dc HW |
222 | |
| 223 | /* Serial Port */ | |
| 224 | #define CONFIG_CONS_INDEX 1 | |
| 765547dc HW |
225 | #define CONFIG_SYS_NS16550_SERIAL |
| 226 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 227 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 93341909 KG |
228 | #ifdef CONFIG_NAND_SPL |
| 229 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 230 | #endif | |
| 765547dc HW |
231 | |
| 232 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 233 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 234 | ||
| 235 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 236 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 237 | ||
| 765547dc HW |
238 | /* |
| 239 | * I2C | |
| 240 | */ | |
| 00f792e0 HS |
241 | #define CONFIG_SYS_I2C |
| 242 | #define CONFIG_SYS_I2C_FSL | |
| 243 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 244 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 245 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 246 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 247 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 248 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 249 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| 765547dc HW |
250 | |
| 251 | /* | |
| 252 | * I2C2 EEPROM | |
| 253 | */ | |
| 254 | #define CONFIG_ID_EEPROM | |
| 255 | #ifdef CONFIG_ID_EEPROM | |
| 256 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 257 | #endif | |
| 258 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
| 259 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 260 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 261 | ||
| 262 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F | |
| 263 | #define PLPPAR1_I2C2_VAL 0x00000000 | |
| 7f52ed5e | 264 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
| 765547dc HW |
265 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
| 266 | #define PLPDIR1_I2C2_VAL 0x0000000F | |
| 7f52ed5e | 267 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
| c4ca10f1 AV |
268 | #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 |
| 269 | #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 | |
| 270 | #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 | |
| 271 | #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 | |
| 765547dc HW |
272 | |
| 273 | /* | |
| 274 | * General PCI | |
| 275 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
| 276 | */ | |
| 94f2bc48 | 277 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
| 765547dc HW |
278 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
| 279 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
| 280 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
| 281 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 282 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 | |
| 283 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 284 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
| 285 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
| 286 | ||
| e5fe96b1 KG |
287 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
| 288 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
| 289 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
| 290 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
| 765547dc HW |
291 | |
| 292 | #ifdef CONFIG_QE | |
| 293 | /* | |
| 294 | * QE UEC ethernet configuration | |
| 295 | */ | |
| f82107f6 HW |
296 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
| 297 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ | |
| 765547dc HW |
298 | |
| 299 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
| 300 | #define CONFIG_UEC_ETH | |
| 78b7a8ef | 301 | #define CONFIG_ETHPRIME "UEC0" |
| 765547dc HW |
302 | #define CONFIG_PHY_MODE_NEED_CHANGE |
| 303 | ||
| 304 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
| 305 | #define CONFIG_HAS_ETH0 | |
| 306 | ||
| 307 | #ifdef CONFIG_UEC_ETH1 | |
| 308 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
| 309 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
| f82107f6 | 310 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
| 765547dc HW |
311 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
| 312 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
| 313 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
| 865ff856 | 314 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
| 582c55a0 | 315 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
| f82107f6 HW |
316 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 317 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
| 318 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
| 319 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ | |
| 865ff856 | 320 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 582c55a0 | 321 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
| f82107f6 HW |
322 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 323 | #endif /* CONFIG_UEC_ETH1 */ | |
| 765547dc HW |
324 | |
| 325 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
| 326 | #define CONFIG_HAS_ETH1 | |
| 327 | ||
| 328 | #ifdef CONFIG_UEC_ETH2 | |
| 329 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ | |
| 330 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
| f82107f6 | 331 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
| 765547dc HW |
332 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
| 333 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
| 334 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
| 865ff856 | 335 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
| 582c55a0 | 336 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
| f82107f6 HW |
337 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 338 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ | |
| 339 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
| 340 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ | |
| 865ff856 | 341 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 582c55a0 | 342 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
| f82107f6 HW |
343 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 344 | #endif /* CONFIG_UEC_ETH2 */ | |
| 765547dc | 345 | |
| 750098d3 HW |
346 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
| 347 | #define CONFIG_HAS_ETH2 | |
| 348 | ||
| 349 | #ifdef CONFIG_UEC_ETH3 | |
| 350 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ | |
| 351 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE | |
| f82107f6 | 352 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
| 750098d3 HW |
353 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
| 354 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH | |
| 355 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 | |
| 865ff856 | 356 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
| 582c55a0 | 357 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 |
| f82107f6 HW |
358 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 359 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ | |
| 360 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH | |
| 361 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ | |
| 865ff856 | 362 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 582c55a0 | 363 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 |
| f82107f6 HW |
364 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 365 | #endif /* CONFIG_UEC_ETH3 */ | |
| 750098d3 HW |
366 | |
| 367 | #define CONFIG_UEC_ETH4 /* GETH4 */ | |
| 368 | #define CONFIG_HAS_ETH3 | |
| 369 | ||
| 370 | #ifdef CONFIG_UEC_ETH4 | |
| 371 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ | |
| 372 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE | |
| f82107f6 | 373 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
| 750098d3 HW |
374 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
| 375 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH | |
| 376 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 | |
| 865ff856 | 377 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
| 582c55a0 | 378 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 |
| f82107f6 HW |
379 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 380 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
| 381 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH | |
| 382 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ | |
| 865ff856 | 383 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 582c55a0 | 384 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 |
| f82107f6 HW |
385 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 386 | #endif /* CONFIG_UEC_ETH4 */ | |
| 3bd8e532 HW |
387 | |
| 388 | #undef CONFIG_UEC_ETH6 /* GETH6 */ | |
| 389 | #define CONFIG_HAS_ETH5 | |
| 390 | ||
| 391 | #ifdef CONFIG_UEC_ETH6 | |
| 392 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ | |
| 393 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE | |
| 394 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE | |
| 395 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH | |
| 396 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 | |
| 865ff856 | 397 | #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
| 582c55a0 | 398 | #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 |
| 3bd8e532 HW |
399 | #endif /* CONFIG_UEC_ETH6 */ |
| 400 | ||
| 401 | #undef CONFIG_UEC_ETH8 /* GETH8 */ | |
| 402 | #define CONFIG_HAS_ETH7 | |
| 403 | ||
| 404 | #ifdef CONFIG_UEC_ETH8 | |
| 405 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ | |
| 406 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE | |
| 407 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE | |
| 408 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH | |
| 409 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 | |
| 865ff856 | 410 | #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
| 582c55a0 | 411 | #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 |
| 3bd8e532 HW |
412 | #endif /* CONFIG_UEC_ETH8 */ |
| 413 | ||
| 765547dc HW |
414 | #endif /* CONFIG_QE */ |
| 415 | ||
| 416 | #if defined(CONFIG_PCI) | |
| 765547dc HW |
417 | #undef CONFIG_EEPRO100 |
| 418 | #undef CONFIG_TULIP | |
| 419 | ||
| 420 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 421 | ||
| 422 | #endif /* CONFIG_PCI */ | |
| 423 | ||
| 765547dc HW |
424 | /* |
| 425 | * Environment | |
| 426 | */ | |
| 674ef7bd | 427 | #if defined(CONFIG_SYS_RAMBOOT) |
| 674ef7bd | 428 | #else |
| 765547dc | 429 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| fb279490 | 430 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 1b8e4fa1 HW |
431 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 432 | #define CONFIG_ENV_SIZE 0x2000 | |
| 674ef7bd | 433 | #endif |
| 765547dc HW |
434 | |
| 435 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 436 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 437 | ||
| 438 | /* QE microcode/firmware address */ | |
| f2717b47 | 439 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| dcf1d774 | 440 | #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 |
| 765547dc HW |
441 | |
| 442 | /* | |
| 443 | * BOOTP options | |
| 444 | */ | |
| 445 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 446 | #define CONFIG_BOOTP_BOOTPATH | |
| 447 | #define CONFIG_BOOTP_GATEWAY | |
| 448 | #define CONFIG_BOOTP_HOSTNAME | |
| 449 | ||
| 765547dc HW |
450 | /* |
| 451 | * Command line configuration. | |
| 452 | */ | |
| 765547dc | 453 | #define CONFIG_CMD_IRQ |
| 199e262e | 454 | #define CONFIG_CMD_REGINFO |
| 765547dc HW |
455 | |
| 456 | #if defined(CONFIG_PCI) | |
| 457 | #define CONFIG_CMD_PCI | |
| 458 | #endif | |
| 459 | ||
| 765547dc HW |
460 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 461 | ||
| 7f52ed5e AV |
462 | #ifdef CONFIG_MMC |
| 463 | #define CONFIG_FSL_ESDHC | |
| a6da8b81 | 464 | #define CONFIG_FSL_ESDHC_PIN_MUX |
| 7f52ed5e | 465 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 7f52ed5e | 466 | #define CONFIG_GENERIC_MMC |
| 7f52ed5e AV |
467 | #define CONFIG_DOS_PARTITION |
| 468 | #endif | |
| 469 | ||
| 765547dc HW |
470 | /* |
| 471 | * Miscellaneous configurable options | |
| 472 | */ | |
| 5be58f5f KP |
473 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 474 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 475 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 765547dc | 476 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 765547dc HW |
477 | #if defined(CONFIG_CMD_KGDB) |
| 478 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ | |
| 479 | #else | |
| 480 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
| 481 | #endif | |
| 482 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 483 | /* Print Buffer Size */ | |
| 484 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
| 485 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 486 | /* Boot Argument Buffer Size */ | |
| 765547dc HW |
487 | |
| 488 | /* | |
| 489 | * For booting Linux, the board info and command line data | |
| a832ac41 | 490 | * have to be in the first 64 MB of memory, since this is |
| 765547dc HW |
491 | * the maximum mapped by the Linux kernel during initialization. |
| 492 | */ | |
| a832ac41 KG |
493 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 494 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 765547dc | 495 | |
| 765547dc HW |
496 | #if defined(CONFIG_CMD_KGDB) |
| 497 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 765547dc HW |
498 | #endif |
| 499 | ||
| 500 | /* | |
| 501 | * Environment Configuration | |
| 502 | */ | |
| 503 | #define CONFIG_HOSTNAME mpc8569mds | |
| 8b3637c6 | 504 | #define CONFIG_ROOTPATH "/nfsroot" |
| b3f44c21 | 505 | #define CONFIG_BOOTFILE "your.uImage" |
| 765547dc HW |
506 | |
| 507 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 508 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 509 | #define CONFIG_NETMASK 255.255.255.0 | |
| 510 | ||
| 511 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
| 512 | ||
| 765547dc HW |
513 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 514 | ||
| 515 | #define CONFIG_BAUDRATE 115200 | |
| 516 | ||
| 517 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 518 | "netdev=eth0\0" \ | |
| 519 | "consoledev=ttyS0\0" \ | |
| 520 | "ramdiskaddr=600000\0" \ | |
| 521 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
| 522 | "fdtaddr=400000\0" \ | |
| 523 | "fdtfile=your.fdt.dtb\0" \ | |
| 524 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 525 | "nfsroot=$serverip:$rootpath " \ | |
| 526 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 527 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
| 528 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
| 529 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
| 530 | ||
| 531 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 532 | "run nfsargs;" \ | |
| 533 | "tftp $loadaddr $bootfile;" \ | |
| 534 | "tftp $fdtaddr $fdtfile;" \ | |
| 535 | "bootm $loadaddr - $fdtaddr" | |
| 536 | ||
| 537 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 538 | "run ramargs;" \ | |
| 539 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 540 | "tftp $loadaddr $bootfile;" \ | |
| 541 | "bootm $loadaddr $ramdiskaddr" | |
| 542 | ||
| 543 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 544 | ||
| 545 | #endif /* __CONFIG_H */ |