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56523f12 1/*
8f0b7cbe 2 * (C) Copyright 2003-2005
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
1a459660 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
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19#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
20#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
21#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
22#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 23
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24/*
25 * Valid values for CONFIG_SYS_TEXT_BASE are:
26 * 0xFC000000 boot low (standard configuration with room for
27 * max 64 MByte Flash ROM)
28 * 0xFFF00000 boot high (for a backup copy of U-Boot)
29 * 0x00100000 boot from RAM (for testing only)
30 */
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFC000000
33#endif
34
5196a7a0 35/* On a Cameron or on a FO300 board or ... */
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36#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
37 && !defined(CONFIG_FO300)
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38#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
39#endif
40
6d0f6bcf 41#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 42
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43#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
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45/*
46 * Serial console configuration
47 */
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48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 50#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 51#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 52
6d3bc9b8 53#ifdef CONFIG_FO300
6d0f6bcf 54#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
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55#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
56#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 57#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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58#if 0
59#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
60 /* switch is closed */
61#endif
62
63#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
64 /* switch is open */
5196a7a0 65#endif /* CONFIG_FO300 */
6d3bc9b8 66
98e69567 67#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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68#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
69#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
70#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 71#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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72#define CONFIG_BOARD_EARLY_INIT_R
73#endif /* CONFIG_STK52XX */
56523f12 74
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75/*
76 * PCI Mapping:
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
79 */
98e69567 80#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 81#define CONFIG_PCI 1
56523f12 82#define CONFIG_PCI_PNP 1
31a64923 83/* #define CONFIG_PCI_SCAN_SHOW 1 */
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84
85#define CONFIG_PCI_MEM_BUS 0x40000000
86#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87#define CONFIG_PCI_MEM_SIZE 0x10000000
88
89#define CONFIG_PCI_IO_BUS 0x50000000
90#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91#define CONFIG_PCI_IO_SIZE 0x01000000
92
cd65a3dc 93#define CONFIG_EEPRO100 1
6d0f6bcf 94#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 95#define CONFIG_NS8382X 1
83e40ba7 96#endif /* CONFIG_STK52XX */
56523f12 97
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98/*
99 * Video console
100 */
5078cce8 101#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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102#define CONFIG_VIDEO
103#define CONFIG_VIDEO_SM501
104#define CONFIG_VIDEO_SM501_32BPP
105#define CONFIG_CFB_CONSOLE
106#define CONFIG_VIDEO_LOGO
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107
108#ifndef CONFIG_FO300
8f0b7cbe 109#define CONFIG_CONSOLE_EXTRA_INFO
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110#else
111#define CONFIG_VIDEO_BMP_LOGO
112#endif
113
114#define CONFIG_VGA_AS_SINGLE_DEVICE
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115#define CONFIG_VIDEO_SW_CURSOR
116#define CONFIG_SPLASH_SCREEN
6d0f6bcf 117#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 118#endif /* #ifndef CONFIG_TQM5200S */
56523f12 119
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120
121/* Partitions */
89c02e2c 122#define CONFIG_MAC_PARTITION
56523f12 123#define CONFIG_DOS_PARTITION
8f0b7cbe 124#define CONFIG_ISO_PARTITION
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125
126/* USB */
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127#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
128 defined(CONFIG_STK52XX)
7b59b3c7 129#define CONFIG_USB_OHCI_NEW
6d0f6bcf 130#define CONFIG_SYS_OHCI_BE_CONTROLLER
56523f12 131#define CONFIG_USB_STORAGE
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132#define CONFIG_CMD_FAT
133#define CONFIG_CMD_USB
53e336e9 134
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135#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
136#define CONFIG_SYS_USB_OHCI_CPU_INIT
137#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
138#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
139#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 140
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141#endif
142
135ae006 143#ifndef CONFIG_CAM5200
56523f12 144/* POST support */
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145#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
146 CONFIG_SYS_POST_CPU | \
147 CONFIG_SYS_POST_I2C)
5078cce8 148#endif
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149
150#ifdef CONFIG_POST
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151/* preserve space for the post_word at end of on-chip SRAM */
152#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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153#endif
154
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155
156/*
a1aa0bb5 157 * BOOTP options
56523f12 158 */
a1aa0bb5
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159#define CONFIG_BOOTP_BOOTFILESIZE
160#define CONFIG_BOOTP_BOOTPATH
161#define CONFIG_BOOTP_GATEWAY
162#define CONFIG_BOOTP_HOSTNAME
163
164
56523f12 165/*
2694690e 166 * Command line configuration.
56523f12 167 */
2694690e
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168#include <config_cmd_default.h>
169
170#define CONFIG_CMD_ASKENV
171#define CONFIG_CMD_DATE
172#define CONFIG_CMD_DHCP
173#define CONFIG_CMD_EEPROM
174#define CONFIG_CMD_I2C
175#define CONFIG_CMD_JFFS2
176#define CONFIG_CMD_MII
177#define CONFIG_CMD_NFS
178#define CONFIG_CMD_PING
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179#define CONFIG_CMD_REGINFO
180#define CONFIG_CMD_SNTP
181#define CONFIG_CMD_BSP
182
183#ifdef CONFIG_VIDEO
184 #define CONFIG_CMD_BMP
185#endif
186
187#ifdef CONFIG_PCI
2b2a587d 188#define CONFIG_CMD_PCI
f33fca22 189#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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190#endif
191
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192#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
193 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
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194 #define CONFIG_CMD_IDE
195 #define CONFIG_CMD_FAT
196 #define CONFIG_CMD_EXT2
197#endif
198
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199#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
200 defined(CONFIG_STK52XX)
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201 #define CONFIG_CFG_USB
202 #define CONFIG_CFG_FAT
203#endif
204
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205#ifdef CONFIG_POST
206 #define CONFIG_CMD_DIAG
207#endif
208
56523f12 209
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210#define CONFIG_TIMESTAMP /* display image timestamps */
211
14d0a02a 212#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 213# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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214#endif
215
216/*
217 * Autobooting
218 */
219#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
220
81050926 221#define CONFIG_PREBOOT "echo;" \
4c4aca81 222 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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223 "echo"
224
225#undef CONFIG_BOOTARGS
226
6d0f6bcf 227#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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228# define ENV_UPDT \
229 "update=protect off FFF00000 +${filesize};" \
230 "erase FFF00000 +${filesize};" \
5078cce8 231 "cp.b 200000 FFF00000 ${filesize};" \
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232 "protect on FFF00000 +${filesize}\0"
233#else /* default lowboot configuration */
6d3bc9b8 234# define ENV_UPDT \
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235 "update=protect off FC000000 +${filesize};" \
236 "erase FC000000 +${filesize};" \
6d3bc9b8 237 "cp.b 200000 FC000000 ${filesize};" \
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238 "protect on FC000000 +${filesize}\0"
239#endif
5078cce8 240
e1f601b5 241#if defined(CONFIG_TQM5200)
6abaee42 242#define CUSTOM_ENV_SETTINGS \
e1f601b5 243 "hostname=tqm5200\0" \
6abaee42 244 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 245 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 246 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 247#elif defined(CONFIG_CAM5200)
1636d1c8 248#define CUSTOM_ENV_SETTINGS \
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249 "bootfile=cam5200/uImage\0" \
250 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 251 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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252#endif
253
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254#if defined(CONFIG_TQM5200_B)
255#define ENV_FLASH_LAYOUT \
256 "fdt_addr=FC100000\0" \
257 "kernel_addr=FC140000\0" \
258 "ramdisk_addr=FC600000\0"
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259#elif defined(CONFIG_CHARON)
260#define ENV_FLASH_LAYOUT \
261 "fdt_addr=FDFC0000\0" \
262 "kernel_addr=FC0A0000\0" \
263 "ramdisk_addr=FC200000\0"
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264#else /* !CONFIG_TQM5200_B */
265#define ENV_FLASH_LAYOUT \
266 "fdt_addr=FC0A0000\0" \
267 "kernel_addr=FC0C0000\0" \
268 "ramdisk_addr=FC300000\0"
269#endif
270
81050926 271#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 272 "netdev=eth0\0" \
e1f601b5 273 "console=ttyPSC0\0" \
a5cc5555 274 ENV_FLASH_LAYOUT \
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275 "kernel_addr_r=400000\0" \
276 "fdt_addr_r=600000\0" \
89c02e2c 277 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 278 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 279 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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280 "nfsroot=${serverip}:${rootpath}\0" \
281 "addip=setenv bootargs ${bootargs} " \
282 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
283 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 284 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 285 "console=${console},${baudrate}\0" \
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286 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
287 "flash_self_old=sete console ttyS0; " \
288 "run ramargs addip addcons addmtd; " \
fe126d8b 289 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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290 "flash_self=run ramargs addip addcons;" \
291 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
292 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 293 "bootm ${kernel_addr}\0" \
e1f601b5 294 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 295 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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296 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
297 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
298 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
299 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 300 "run nfsargs addip addcons addmtd; " \
e1f601b5 301 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 302 CUSTOM_ENV_SETTINGS \
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303 "load=tftp 200000 ${u-boot}\0" \
304 ENV_UPDT \
7e6bf358 305 ""
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306
307#define CONFIG_BOOTCOMMAND "run net_nfs"
308
309/*
310 * IPB Bus clocking configuration.
311 */
6d0f6bcf 312#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 313
6d0f6bcf 314#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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315/*
316 * PCI Bus clocking configuration
317 *
318 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 319 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 320 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 321 */
6d0f6bcf 322#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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323#endif
324
325/*
326 * I2C configuration
327 */
328#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 329#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 330#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 331#else
6d0f6bcf 332#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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333#endif
334
335/*
336 * I2C clock frequency
337 *
338 * Please notice, that the resulting clock frequency could differ from the
339 * configured value. This is because the I2C clock is derived from system
340 * clock over a frequency divider with only a few divider values. U-boot
6d0f6bcf 341 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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342 * approximation allways lies below the configured value, never above.
343 */
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JCPV
344#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
345#define CONFIG_SYS_I2C_SLAVE 0x7F
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346
347/*
348 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
349 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
350 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
351 * same configuration could be used.
352 */
6d0f6bcf
JCPV
353#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
354#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
355#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
356#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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357
358/*
359 * HW-Monitor configuration on Mini-FAP
360 */
361#if defined (CONFIG_MINIFAP)
6d0f6bcf 362#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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363#endif
364
365/* List of I2C addresses to be verified by POST */
56523f12 366#if defined (CONFIG_MINIFAP)
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367#undef CONFIG_SYS_POST_I2C_ADDRS
368#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
369 CONFIG_SYS_I2C_HWMON_ADDR, \
370 CONFIG_SYS_I2C_SLAVE}
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371#endif
372
373/*
374 * Flash configuration
375 */
6d0f6bcf 376#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 377
d9384de2 378#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 379#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 380 (= chip selects) */
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JCPV
381#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
382#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
383#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
384
385#define CONFIG_SYS_FLASH_ADDR0 0x555
386#define CONFIG_SYS_FLASH_ADDR1 0x2AA
387#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
388#define CONFIG_SYS_MAX_FLASH_SECT 128
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389#else
390/* use CFI flash driver */
6d0f6bcf 391#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 392#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 393#define CONFIG_FLASH_CFI_MTD /* with MTD support */
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394#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
395#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 396 (= chip selects) */
6d0f6bcf 397#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 398#endif
7299712c 399
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400#define CONFIG_SYS_FLASH_EMPTY_INFO
401#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
402#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 403
135ae006 404#if defined (CONFIG_CAM5200)
6d0f6bcf 405# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 406#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 407# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 408#else
6d0f6bcf 409# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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410#endif
411
d534f5cc 412/* Dynamic MTD partition support */
68d7d651 413#define CONFIG_CMD_MTDPARTS
942556a9 414#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 415#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 416
5624d66a 417#if defined(CONFIG_STK52XX)
5078cce8 418# if defined(CONFIG_TQM5200_B)
6d0f6bcf 419# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 420# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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421 "256k(dtb)," \
422 "2304k(kernel)," \
423 "2560k(small-fs)," \
45a212c4 424 "2m(initrd)," \
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425 "8m(misc)," \
426 "16m(big-fs)"
427# else /* highboot */
259bff7c 428# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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429 "3584k(small-fs)," \
430 "2m(initrd)," \
431 "8m(misc)," \
432 "15m(big-fs)," \
433 "1m(firmware)"
6d0f6bcf 434# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 435# else /* !CONFIG_TQM5200_B */
259bff7c 436# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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437 "128k(dtb)," \
438 "2304k(kernel)," \
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439 "2m(initrd)," \
440 "4m(small-fs)," \
5078cce8 441 "8m(misc)," \
e1f601b5 442 "15m(big-fs)"
5078cce8 443# endif /* CONFIG_TQM5200_B */
135ae006 444#elif defined (CONFIG_CAM5200)
259bff7c 445# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 446 "1792k(kernel)," \
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447 "5632k(rootfs)," \
448 "24m(home)"
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HS
449#elif defined (CONFIG_CHARON)
450# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
451 "1408k(kernel)," \
452 "2m(initrd)," \
453 "4m(small-fs)," \
454 "24320k(big-fs)," \
455 "256k(dts)"
6d3bc9b8 456#elif defined (CONFIG_FO300)
259bff7c 457# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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458 "1408k(kernel)," \
459 "2m(initrd)," \
460 "4m(small-fs)," \
461 "8m(misc)," \
462 "16m(big-fs)"
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463#else
464# error "Unknown Carrier Board"
465#endif /* CONFIG_STK52XX */
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466
467/*
468 * Environment settings
469 */
5a1aceb0 470#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 471#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 472#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 473#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 474#else
0e8d1586 475#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 476#endif /* CONFIG_TQM5200_B */
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477#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
478#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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479
480/*
481 * Memory map
482 */
6d0f6bcf
JCPV
483#define CONFIG_SYS_MBAR 0xF0000000
484#define CONFIG_SYS_SDRAM_BASE 0x00000000
485#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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486
487/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 488#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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489#ifdef CONFIG_POST
490/* preserve space for the post_word at end of on-chip SRAM */
553f0982 491#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 492#else
553f0982 493#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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494#endif
495
496
25ddd1fb 497#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 498#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 499
14d0a02a 500#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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501#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
502# define CONFIG_SYS_RAMBOOT 1
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503#endif
504
135ae006 505#if defined (CONFIG_CAM5200)
6d0f6bcf 506# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 507#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 508# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 509#else
6d0f6bcf 510# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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511#endif
512
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513#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
514#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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515
516/*
517 * Ethernet configuration
518 */
519#define CONFIG_MPC5xxx_FEC 1
86321fc1 520#define CONFIG_MPC5xxx_FEC_MII100
56523f12 521/*
86321fc1 522 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 523 */
86321fc1 524/* #define CONFIG_MPC5xxx_FEC_MII10 */
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525#define CONFIG_PHY_ADDR 0x00
526
527/*
528 * GPIO configuration
529 *
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530 * use CS1: Bit 0 (mask: 0x80000000):
531 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 532 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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533 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
534 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
535 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
536 * Use for REV200 STK52XX boards and FO300 boards. Do not use
537 * with REV100 modules (because, there I2C1 is used as I2C bus).
538 * use ATA: Bits 6-7 (mask 0x03000000):
539 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
540 * Use for CAM5200 board.
541 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
542 * use PSC6: Bits 9-11 (mask 0x00700000):
543 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
544 * UART, CODEC or IrDA.
545 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
546 * enable extended POST tests.
547 * Use for MINI-FAP and TQM5200_IB boards.
548 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
549 * Extended POST test is not available.
550 * Use for STK52xx, FO300 and CAM5200 boards.
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551 * WARNING: When the extended POST is enabled, these bits will
552 * be overridden by this code as GPIOs!
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553 * use PCI_DIS: Bit 16 (mask 0x00008000):
554 * 1 -> disable PCI controller (on CAM5200 board).
555 * use USB: Bits 18-19 (mask 0x00003000):
556 * 10 -> two UARTs (on FO300 and CAM5200).
557 * use PSC3: Bits 20-23 (mask: 0x00000f00):
558 * 0000 -> All PSC3 pins are GPIOs.
559 * 1100 -> UART/SPI (on FO300 board).
560 * 0100 -> UART (on CAM5200 board).
561 * use PSC2: Bits 25:27 (mask: 0x00000030):
562 * 000 -> All PSC2 pins are GPIOs.
563 * 100 -> UART (on CAM5200 board).
564 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 565 * Use for REV100 STK52xx boards
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566 * 01x -> Use AC97 (on FO300 board).
567 * use PSC1: Bits 29-31 (mask: 0x00000007):
568 * 100 -> UART (on all boards).
56523f12 569 */
98e69567 570#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 571#if defined (CONFIG_MINIFAP)
6d0f6bcf 572# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 573#elif defined (CONFIG_STK52XX)
83e40ba7 574# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 575# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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576# else /* STK52xx REV200 and above */
577# if defined (CONFIG_TQM5200_REV100)
578# error TQM5200 REV100 not supported on STK52XX REV200 or above
579# else/* TQM5200 REV200 and above */
6d0f6bcf 580# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 581# endif
8f0b7cbe 582# endif
6d3bc9b8 583#elif defined (CONFIG_FO300)
6d0f6bcf 584# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 585#elif defined (CONFIG_CAM5200)
6d0f6bcf 586# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 587#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 588# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 589#endif
98e69567 590#endif
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591
592/*
593 * RTC configuration
594 */
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595#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
596# define CONFIG_RTC_M41T11 1
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597# define CONFIG_SYS_I2C_RTC_ADDR 0x68
598# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 599 year */
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600#else
601# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
602#endif
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603
604/*
605 * Miscellaneous configurable options
606 */
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607#define CONFIG_SYS_LONGHELP /* undef to save memory */
608#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
5078cce8 609
2751a95a 610#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6d0f6bcf 611#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
5078cce8 612
6d0f6bcf 613#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 614#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 615#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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616#endif
617
618#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 619#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 620#else
6d0f6bcf 621#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 622#endif
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623#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
624#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
625#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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626
627/* Enable an alternate, more extensive memory test */
6d0f6bcf 628#define CONFIG_SYS_ALT_MEMTEST
56523f12 629
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630#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
631#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 632
6d0f6bcf 633#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 634
6d0f6bcf 635#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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636
637/*
a1aa0bb5 638 * Enable loopw command.
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639 */
640#define CONFIG_LOOPW
641
642/*
643 * Various low-level settings
644 */
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645#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
646#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 647
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648#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
649#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
650#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
651#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 652#else
6d0f6bcf 653#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 654#endif
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655#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
656#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 657
7e6bf358 658#define CONFIG_LAST_STAGE_INIT
7e6bf358 659
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660/*
661 * SRAM - Do not map below 2 GB in address space, because this area is used
662 * for SDRAM autosizing.
663 */
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664#define CONFIG_SYS_CS2_START 0xE5000000
665#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
666#define CONFIG_SYS_CS2_CFG 0x0004D930
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667
668/*
669 * Grafic controller - Do not map below 2 GB in address space, because this
670 * area is used for SDRAM autosizing.
671 */
8f0b7cbe 672#define SM501_FB_BASE 0xE0000000
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673#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
674#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
675#define CONFIG_SYS_CS1_CFG 0x8F48FF70
676#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 677
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678#define CONFIG_SYS_CS_BURST 0x00000000
679#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 680
7299712c 681#if defined(CONFIG_CAM5200)
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682#define CONFIG_SYS_CS4_START 0xB0000000
683#define CONFIG_SYS_CS4_SIZE 0x00010000
684#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 685
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686#define CONFIG_SYS_CS5_START 0xD0000000
687#define CONFIG_SYS_CS5_SIZE 0x01208000
688#define CONFIG_SYS_CS5_CFG 0x1414BF10
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689#endif
690
6d0f6bcf 691#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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692
693/*-----------------------------------------------------------------------
694 * USB stuff
695 *-----------------------------------------------------------------------
696 */
697#define CONFIG_USB_CLOCK 0x0001BBBB
698#define CONFIG_USB_CONFIG 0x00001000
699
700/*-----------------------------------------------------------------------
701 * IDE/ATA stuff Supports IDE harddisk
702 *-----------------------------------------------------------------------
703 */
704
81050926 705#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 706
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707#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
708#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 709
81050926 710#define CONFIG_IDE_RESET /* reset for ide supported */
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711#define CONFIG_IDE_PREINIT
712
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713#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
714#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 715
6d0f6bcf 716#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 717
6d0f6bcf 718#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 719
95c44ec4 720/* Offset for data I/O */
6d0f6bcf 721#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 722
95c44ec4 723/* Offset for normal register accesses */
6d0f6bcf 724#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 725
95c44ec4 726/* Offset for alternate registers */
6d0f6bcf 727#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 728
95c44ec4 729/* Interval between registers */
6d0f6bcf 730#define CONFIG_SYS_ATA_STRIDE 4
56523f12 731
33af3e66 732/* Support ATAPI devices */
95c44ec4 733#define CONFIG_ATAPI 1
33af3e66 734
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735/*-----------------------------------------------------------------------
736 * Open firmware flat tree support
737 *-----------------------------------------------------------------------
738 */
cf2817a8 739#define CONFIG_OF_LIBFDT 1
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740#define CONFIG_OF_BOARD_SETUP 1
741
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742#define OF_CPU "PowerPC,5200@0"
743#define OF_SOC "soc5200@f0000000"
744#define OF_TBCLK (bd->bi_busfreq / 4)
745#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
746
56523f12 747#endif /* __CONFIG_H */