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d4ca31c4 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2000-2005 |
d4ca31c4 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c178d3da | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d4ca31c4 WD |
16 | * GNU General Public License for more details. |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
37 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
38 | ||
66ca92a5 WD |
39 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
40 | #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ | |
41 | #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
42 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ | |
c178d3da WD |
43 | /* (it will be used if there is no */ |
44 | /* 'cpuclk' variable with valid value) */ | |
d4ca31c4 | 45 | |
75d1ea7f WD |
46 | #undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */ |
47 | /* (function measure_gclk() */ | |
48 | /* will be called) */ | |
49 | #ifdef CFG_MEASURE_CPUCLK | |
50 | #define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
51 | #endif | |
52 | ||
c178d3da | 53 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
d4ca31c4 WD |
54 | |
55 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
56 | ||
c178d3da | 57 | #define CONFIG_BOOTCOUNT_LIMIT |
d4ca31c4 WD |
58 | |
59 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
60 | ||
61 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
62 | ||
c178d3da | 63 | #define CONFIG_PREBOOT "echo;" \ |
d4ca31c4 WD |
64 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ |
65 | "echo" | |
66 | ||
67 | #undef CONFIG_BOOTARGS | |
68 | ||
c178d3da | 69 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
d4ca31c4 WD |
70 | "netdev=eth0\0" \ |
71 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 72 | "nfsroot=${serverip}:${rootpath}\0" \ |
d4ca31c4 | 73 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
74 | "addip=setenv bootargs ${bootargs} " \ |
75 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
76 | ":${hostname}:${netdev}:off panic=1\0" \ | |
d4ca31c4 | 77 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 78 | "bootm ${kernel_addr}\0" \ |
d4ca31c4 | 79 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
80 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
81 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
d4ca31c4 | 82 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
5e4be00f | 83 | "bootfile=/tftpboot/TQM866M/uImage\0" \ |
9ef57bbe MK |
84 | "fdt_addr=400C0000\0" \ |
85 | "kernel_addr=40100000\0" \ | |
eb6da805 | 86 | "ramdisk_addr=40280000\0" \ |
9ef57bbe MK |
87 | "load=tftp 200000 ${u-boot}\0" \ |
88 | "update=protect off 40000000 +${filesize};" \ | |
89 | "erase 40000000 +${filesize};" \ | |
90 | "cp.b 200000 40000000 ${filesize};" \ | |
91 | "protect on 40000000 +${filesize}\0" \ | |
d4ca31c4 WD |
92 | "" |
93 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
94 | ||
95 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
96 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
97 | ||
98 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
99 | ||
c178d3da | 100 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
d4ca31c4 WD |
101 | |
102 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
103 | ||
104 | /* enable I2C and select the hardware/software driver */ | |
105 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
c178d3da | 106 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
d4ca31c4 WD |
107 | |
108 | #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ | |
109 | #define CFG_I2C_SLAVE 0xFE | |
110 | ||
111 | #ifdef CONFIG_SOFT_I2C | |
112 | /* | |
113 | * Software (bit-bang) I2C driver configuration | |
114 | */ | |
115 | #define PB_SCL 0x00000020 /* PB 26 */ | |
116 | #define PB_SDA 0x00000010 /* PB 27 */ | |
117 | ||
118 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
119 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
120 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
121 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
122 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
c178d3da | 123 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
d4ca31c4 | 124 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
c178d3da | 125 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
d4ca31c4 WD |
126 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
127 | #endif /* CONFIG_SOFT_I2C */ | |
128 | ||
129 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ | |
c178d3da | 130 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ |
d4ca31c4 WD |
131 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 |
132 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
133 | ||
37d4bb70 JL |
134 | /* |
135 | * BOOTP options | |
136 | */ | |
137 | #define CONFIG_BOOTP_SUBNETMASK | |
138 | #define CONFIG_BOOTP_GATEWAY | |
139 | #define CONFIG_BOOTP_HOSTNAME | |
140 | #define CONFIG_BOOTP_BOOTPATH | |
141 | #define CONFIG_BOOTP_BOOTFILESIZE | |
142 | ||
d4ca31c4 WD |
143 | |
144 | #define CONFIG_MAC_PARTITION | |
145 | #define CONFIG_DOS_PARTITION | |
146 | ||
a6cccaea WD |
147 | #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ |
148 | ||
149 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
d4ca31c4 | 150 | |
d4ca31c4 | 151 | |
2694690e JL |
152 | /* |
153 | * Command line configuration. | |
154 | */ | |
155 | #include <config_cmd_default.h> | |
156 | ||
157 | #define CONFIG_CMD_ASKENV | |
158 | #define CONFIG_CMD_DHCP | |
159 | #define CONFIG_CMD_EEPROM | |
160 | #define CONFIG_CMD_I2C | |
161 | #define CONFIG_CMD_IDE | |
162 | #define CONFIG_CMD_NFS | |
163 | ||
d4ca31c4 WD |
164 | |
165 | /* | |
166 | * Miscellaneous configurable options | |
167 | */ | |
c178d3da WD |
168 | #define CFG_LONGHELP /* undef to save memory */ |
169 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
d4ca31c4 | 170 | |
2751a95a WD |
171 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
172 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
d4ca31c4 | 173 | #ifdef CFG_HUSH_PARSER |
2751a95a | 174 | #define CFG_PROMPT_HUSH_PS2 "> " |
d4ca31c4 WD |
175 | #endif |
176 | ||
2694690e | 177 | #if defined(CONFIG_CMD_KGDB) |
c178d3da | 178 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
d4ca31c4 | 179 | #else |
c178d3da | 180 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
d4ca31c4 | 181 | #endif |
c178d3da WD |
182 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
183 | #define CFG_MAXARGS 16 /* max number of command args */ | |
d4ca31c4 WD |
184 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
185 | ||
186 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
187 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
188 | ||
c178d3da | 189 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
d4ca31c4 | 190 | |
c178d3da | 191 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
d4ca31c4 WD |
192 | |
193 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
194 | ||
195 | /* | |
196 | * Low Level Configuration Settings | |
197 | * (address mappings, register initial values, etc.) | |
198 | * You should know what you are doing if you make changes here. | |
199 | */ | |
200 | /*----------------------------------------------------------------------- | |
201 | * Internal Memory Mapped Register | |
202 | */ | |
203 | #define CFG_IMMR 0xFFF00000 | |
204 | ||
205 | /*----------------------------------------------------------------------- | |
206 | * Definitions for initial stack pointer and data area (in DPRAM) | |
207 | */ | |
208 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
c178d3da WD |
209 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
210 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
d4ca31c4 | 211 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
c178d3da | 212 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
d4ca31c4 WD |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * Start addresses for the final memory configuration | |
216 | * (Set up by the startup code) | |
217 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
218 | */ | |
c178d3da | 219 | #define CFG_SDRAM_BASE 0x00000000 |
d4ca31c4 | 220 | #define CFG_FLASH_BASE 0x40000000 |
c178d3da | 221 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
d4ca31c4 | 222 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
9ef57bbe | 223 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ |
d4ca31c4 WD |
224 | |
225 | /* | |
226 | * For booting Linux, the board info and command line data | |
227 | * have to be in the first 8 MB of memory, since this is | |
228 | * the maximum mapped by the Linux kernel during initialization. | |
229 | */ | |
c178d3da | 230 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d4ca31c4 WD |
231 | |
232 | /*----------------------------------------------------------------------- | |
233 | * FLASH organization | |
234 | */ | |
235 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
236 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
237 | ||
238 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
239 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
240 | ||
c178d3da WD |
241 | #define CFG_ENV_IS_IN_FLASH 1 |
242 | #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
243 | #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
9ef57bbe | 244 | #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
d4ca31c4 WD |
245 | |
246 | /* Address and size of Redundant Environment Sector */ | |
247 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) | |
248 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
249 | ||
67c31036 WD |
250 | #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
251 | ||
d4ca31c4 WD |
252 | /*----------------------------------------------------------------------- |
253 | * Hardware Information Block | |
254 | */ | |
255 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
c178d3da | 256 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
d4ca31c4 WD |
257 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
258 | ||
259 | /*----------------------------------------------------------------------- | |
260 | * Cache Configuration | |
261 | */ | |
262 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
2694690e | 263 | #if defined(CONFIG_CMD_KGDB) |
d4ca31c4 WD |
264 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
265 | #endif | |
266 | ||
267 | /*----------------------------------------------------------------------- | |
268 | * SYPCR - System Protection Control 11-9 | |
269 | * SYPCR can only be written once after reset! | |
270 | *----------------------------------------------------------------------- | |
271 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
272 | */ | |
273 | #if defined(CONFIG_WATCHDOG) | |
274 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
275 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
276 | #else | |
277 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
278 | #endif | |
279 | ||
280 | /*----------------------------------------------------------------------- | |
281 | * SIUMCR - SIU Module Configuration 11-6 | |
282 | *----------------------------------------------------------------------- | |
283 | * PCMCIA config., multi-function pin tri-state | |
284 | */ | |
c178d3da | 285 | #ifndef CONFIG_CAN_DRIVER |
d4ca31c4 WD |
286 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
287 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
288 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
289 | #endif /* CONFIG_CAN_DRIVER */ | |
290 | ||
291 | /*----------------------------------------------------------------------- | |
292 | * TBSCR - Time Base Status and Control 11-26 | |
293 | *----------------------------------------------------------------------- | |
294 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
295 | */ | |
296 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
297 | ||
d4ca31c4 WD |
298 | /*----------------------------------------------------------------------- |
299 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
300 | *----------------------------------------------------------------------- | |
301 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
302 | */ | |
303 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
304 | ||
d4ca31c4 WD |
305 | /*----------------------------------------------------------------------- |
306 | * SCCR - System Clock and reset Control Register 15-27 | |
307 | *----------------------------------------------------------------------- | |
308 | * Set clock output, timebase and RTC source and divider, | |
309 | * power management and some other internal clocks | |
310 | */ | |
311 | #define SCCR_MASK SCCR_EBDF11 | |
c178d3da | 312 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
d4ca31c4 WD |
313 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
314 | SCCR_DFALCD00) | |
d4ca31c4 WD |
315 | |
316 | /*----------------------------------------------------------------------- | |
317 | * PCMCIA stuff | |
318 | *----------------------------------------------------------------------- | |
319 | * | |
320 | */ | |
321 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
322 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
323 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
324 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
325 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
326 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
327 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
328 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
329 | ||
330 | /*----------------------------------------------------------------------- | |
331 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
332 | *----------------------------------------------------------------------- | |
333 | */ | |
334 | ||
c178d3da | 335 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
d4ca31c4 | 336 | |
c178d3da WD |
337 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
338 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
d4ca31c4 WD |
339 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
340 | ||
341 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
342 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
343 | ||
344 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
345 | ||
346 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
347 | ||
348 | /* Offset for data I/O */ | |
349 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
350 | ||
351 | /* Offset for normal register accesses */ | |
352 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
353 | ||
354 | /* Offset for alternate registers */ | |
355 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
356 | ||
357 | /*----------------------------------------------------------------------- | |
358 | * | |
359 | *----------------------------------------------------------------------- | |
360 | * | |
361 | */ | |
c178d3da | 362 | #define CFG_DER 0 |
d4ca31c4 WD |
363 | |
364 | /* | |
365 | * Init Memory Controller: | |
366 | * | |
367 | * BR0/1 and OR0/1 (FLASH) | |
368 | */ | |
369 | ||
370 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
371 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
372 | ||
373 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
374 | * restrict access enough to keep SRAM working (if any) | |
375 | * but not too much to meddle with FLASH accesses | |
376 | */ | |
377 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
378 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
379 | ||
380 | /* | |
c178d3da | 381 | * FLASH timing: Default value of OR0 after reset |
d4ca31c4 | 382 | */ |
c178d3da WD |
383 | #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
384 | OR_SCY_15_CLK | OR_TRLX) | |
d4ca31c4 WD |
385 | |
386 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
387 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
388 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
389 | ||
390 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
391 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
392 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
393 | ||
394 | /* | |
395 | * BR2/3 and OR2/3 (SDRAM) | |
396 | * | |
397 | */ | |
398 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
399 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
c178d3da | 400 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
d4ca31c4 WD |
401 | |
402 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
403 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
404 | ||
405 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
406 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
407 | ||
c178d3da WD |
408 | #ifndef CONFIG_CAN_DRIVER |
409 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
d4ca31c4 WD |
410 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
411 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
c178d3da | 412 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
d4ca31c4 WD |
413 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
414 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
415 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
416 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
417 | #endif /* CONFIG_CAN_DRIVER */ | |
418 | ||
c178d3da | 419 | /* |
c178d3da WD |
420 | * 4096 Rows from SDRAM example configuration |
421 | * 1000 factor s -> ms | |
422 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
423 | * 4 Number of refresh cycles per period | |
424 | * 64 Refresh cycle in ms per number of rows | |
425 | */ | |
66ca92a5 | 426 | #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
c178d3da | 427 | |
d4ca31c4 | 428 | /* |
d43e489b MK |
429 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
430 | * | |
431 | * CPUclock(MHz) * 31.2 | |
432 | * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 | |
433 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 | |
434 | * | |
435 | * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us | |
436 | * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us | |
437 | * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us | |
438 | * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us | |
439 | * | |
440 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
441 | * be met also in the default configuration, i.e. if environment variable | |
442 | * 'cpuclk' is not set. | |
d4ca31c4 | 443 | */ |
d43e489b | 444 | #define CFG_MAMR_PTA 97 |
d4ca31c4 WD |
445 | |
446 | /* | |
d43e489b | 447 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
d4ca31c4 | 448 | */ |
d43e489b MK |
449 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
450 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 | |
451 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ | |
452 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 | |
d4ca31c4 WD |
453 | |
454 | /* | |
455 | * MAMR settings for SDRAM | |
456 | */ | |
457 | ||
458 | /* 8 column SDRAM */ | |
459 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
460 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
461 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
462 | /* 9 column SDRAM */ | |
463 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
464 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
465 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
c178d3da WD |
466 | /* 10 column SDRAM */ |
467 | #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
468 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ | |
469 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
d4ca31c4 WD |
470 | |
471 | /* | |
472 | * Internal Definitions | |
473 | * | |
474 | * Boot Flags | |
475 | */ | |
c178d3da | 476 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
d4ca31c4 WD |
477 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
478 | ||
479 | #define CONFIG_SCC1_ENET | |
480 | #define CONFIG_FEC_ENET | |
481 | #define CONFIG_ETHPRIME "SCC ETHERNET" | |
482 | ||
483 | #endif /* __CONFIG_H */ |