[people/ms/u-boot.git] / include / configs / VCMA9.h

/*
 * (C) Copyright 2002, 2003
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 * Gary Jennejohn <gj@denx.de>
 * David Mueller <d.mueller@elsoft.ch>
 *
 * Configuation settings for the MPL VCMA9 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
#define CONFIG_VCMA9		1	/* on a MPL VCMA9 Board  */

/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	12000000/* VCMA9 has 12MHz input clock	*/

#define USE_920T_MMU		1
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	 1


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_USB
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FAT
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP


#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/***********************************************************
 * I2C stuff:
 * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
 * address 0x50 with 16bit addressing
 ***********************************************************/
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at offset 0 */
#define CONFIG_ENV_SIZE		0x800	/* 2KB should be more than enough */

#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* 64 bytes page write mode on 24C256 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/*
 * Size of malloc() pool
 */
/*#define CONFIG_MALLOC_SIZE	(CONFIG_ENV_SIZE + 128*1024)*/
#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_CS8900	1		/* we have a CS8900 on-board */
#define CS8900_BASE		0x20000300
#define CS8900_BUS16		1		/* the Linux driver does accesses as shorts */

#define CONFIG_DRIVER_S3C24X0_I2C	1	/* we use the buildin I2C controller */

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on VCMA9 */

/************************************************************
 * USB support
 ************************************************************/
#define CONFIG_USB_OHCI		1
#define CONFIG_USB_KEYBOARD	1
#define CONFIG_USB_STORAGE	1
#define CONFIG_DOS_PARTITION	1

/* Enable needed helper functions */
#define CONFIG_SYS_DEVICE_DEREGISTER		/* needs device_deregister */

/************************************************************
 * RTC
 ************************************************************/
#define	CONFIG_RTC_S3C24X0	1


/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		9600

#define CONFIG_BOOTDELAY	5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */

#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		10.0.0.110
#define CONFIG_SERVERIP		10.0.0.1

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"VCMA9 # "	/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/

#define CONFIG_SYS_ALT_MEMTEST
#define	CONFIG_SYS_LOAD_ADDR		0x30800000	/* default load address	*/

/* we configure PWM Timer 4 to 1us ~ 1MHz */
/*#define	CONFIG_SYS_HZ			1000000 */
#define	CONFIG_SYS_HZ			1562500

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* support BZIP2 compression */
#define CONFIG_BZIP2		1

/************************************************************
 * Ident
 ************************************************************/
/*#define VERSION_TAG "released"*/
#define VERSION_TAG "unstable"
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
#if 0
#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
#endif

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
#endif

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */

#if 0
#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
#endif


#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000

/*-----------------------------------------------------------------------
 * NAND flash settings
 */
#if defined(CONFIG_CMD_NAND)

#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
#define SECTORSIZE 512

#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS 1

#define NAND_WAIT_READY(nand)	NF_WaitRB()

#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)


#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
#define WRITE_NAND(d, adr)		NF_Write(d)
#define READ_NAND(adr)			NF_Read()
/* the following functions are NOP's because S3C24X0 handles this in hardware */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)

#define CONFIG_MTD_NAND_VERIFY_WRITE	1
#define CONFIG_MTD_NAND_ECC_JFFS2	1

#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
1cb8e980	1	/*
531716e1	2	* (C) Copyright 2002, 2003
1cb8e980 WD	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	* Gary Jennejohn <gj@denx.de>
	6	* David Mueller <d.mueller@elsoft.ch>
	7	*
	8	* Configuation settings for the MPL VCMA9 board.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
1cb8e980 WD	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36	#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
	37	#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
	38	#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
	39
	40	/* input clock of PLL */
	41	#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
	42
	43	#define USE_920T_MMU 1
	44	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	45
53677ef1	46	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
1cb8e980 WD	47	#define CONFIG_SETUP_MEMORY_TAGS 1
	48	#define CONFIG_INITRD_TAG 1
	49
a5562901	50
a1aa0bb5 JL	51	/*
	52	* BOOTP options
	53	*/
	54	#define CONFIG_BOOTP_BOOTFILESIZE
	55	#define CONFIG_BOOTP_BOOTPATH
	56	#define CONFIG_BOOTP_GATEWAY
	57	#define CONFIG_BOOTP_HOSTNAME
	58
	59
a5562901 JL	60	/*
	61	* Command line configuration.
	62	*/
	63	#include <config_cmd_default.h>
	64
	65	#define CONFIG_CMD_CACHE
	66	#define CONFIG_CMD_EEPROM
	67	#define CONFIG_CMD_I2C
	68	#define CONFIG_CMD_USB
	69	#define CONFIG_CMD_REGINFO
	70	#define CONFIG_CMD_FAT
	71	#define CONFIG_CMD_DATE
	72	#define CONFIG_CMD_ELF
	73	#define CONFIG_CMD_DHCP
	74	#define CONFIG_CMD_PING
	75	#define CONFIG_CMD_BSP
	76
1cb8e980	77
6d0f6bcf JCPV	78	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	79	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1cb8e980 WD	80	/***********************************************************
	81	* I2C stuff:
	82	* the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
	83	* address 0x50 with 16bit addressing
	84	***********************************************************/
	85	#define CONFIG_HARD_I2C /* I2C with hardware support */
6d0f6bcf JCPV	86	#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
6d0f6bcf JCPV	87	#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
1cb8e980	88
6d0f6bcf JCPV	89	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
6d0f6bcf JCPV	90	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
bb1f8b4f	91	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	92	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */
0e8d1586 JCPV	93	#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */
1cb8e980	94
6d0f6bcf JCPV	95	#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	96	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */
	97	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
1cb8e980 WD	98
	99	/*
	100	* Size of malloc() pool
	101	*/
0e8d1586	102	/#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 1281024)*/
6d0f6bcf	103	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
1cb8e980	104
6d0f6bcf JCPV	105	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
6d0f6bcf JCPV	106	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
1cb8e980 WD	107
	108	/*
	109	* Hardware drivers
	110	*/
	111	#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
	112	#define CS8900_BASE 0x20000300
53677ef1	113	#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
1cb8e980 WD	114
	115	#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
	116
	117	/*
	118	* select serial console configuration
	119	*/
	120	#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
	121
48b42616 WD	122	/************************************************************
	123	* USB support
	124	************************************************************/
a2663ea4 WD	125	#define CONFIG_USB_OHCI 1
	126	#define CONFIG_USB_KEYBOARD 1
	127	#define CONFIG_USB_STORAGE 1
	128	#define CONFIG_DOS_PARTITION 1
48b42616 WD	129
48b42616 WD	130	/* Enable needed helper functions */
6d0f6bcf	131	#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
48b42616 WD	132
	133	/************************************************************
	134	* RTC
	135	************************************************************/
	136	#define CONFIG_RTC_S3C24X0 1
	137
	138
1cb8e980 WD	139	/* allow to overwrite serial and ethaddr */
	140	#define CONFIG_ENV_OVERWRITE
	141
	142	#define CONFIG_BAUDRATE 9600
	143
a2663ea4 WD	144	#define CONFIG_BOOTDELAY 5
a2663ea4 WD	145	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2893ecbf	146	/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
53677ef1	147	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
a2663ea4	148
1cb8e980 WD	149	#define CONFIG_NETMASK 255.255.255.0
	150	#define CONFIG_IPADDR 10.0.0.110
	151	#define CONFIG_SERVERIP 10.0.0.1
	152
a5562901	153	#if defined(CONFIG_CMD_KGDB)
1cb8e980 WD	154	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	155	/* what's this ? it's not used anywhere */
	156	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	157	#endif
	158
	159	/*
	160	* Miscellaneous configurable options
	161	*/
6d0f6bcf JCPV	162	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	163	#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */
	164	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	165	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	166	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	167	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1cb8e980	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
6d0f6bcf JCPV	170	#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */
531716e1	171
6d0f6bcf JCPV	172	#define CONFIG_SYS_ALT_MEMTEST
6d0f6bcf JCPV	173	#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
1cb8e980	174
1cb8e980	175	/* we configure PWM Timer 4 to 1us ~ 1MHz */
6d0f6bcf JCPV	176	/#define CONFIG_SYS_HZ 1000000 /
6d0f6bcf JCPV	177	#define CONFIG_SYS_HZ 1562500
1cb8e980 WD	178
1cb8e980 WD	179	/* valid baudrates */
6d0f6bcf	180	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
1cb8e980	181
a2663ea4 WD	182	/* support BZIP2 compression */
	183	#define CONFIG_BZIP2 1
	184
48b42616 WD	185	/************************************************************
	186	* Ident
	187	************************************************************/
	188	/#define VERSION_TAG "released"/
	189	#define VERSION_TAG "unstable"
	190	#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
	191
1cb8e980 WD	192	/*-----------------------------------------------------------------------
	193	* Stack sizes
	194	*
	195	* The stack sizes are set up in start.S using the settings below
	196	*/
	197	#define CONFIG_STACKSIZE (1281024) / regular stack */
	198	#ifdef CONFIG_USE_IRQ
	199	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	200	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	201	#endif
	202
	203	/*-----------------------------------------------------------------------
	204	* Physical Memory Map
	205	*/
	206	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	207	#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
1cb8e980 WD	208	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
1cb8e980 WD	209
6d0f6bcf	210	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
1cb8e980 WD	211
	212	/*-----------------------------------------------------------------------
	213	* FLASH and environment organization
	214	*/
	215
	216	#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
	217	#if 0
	218	#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
	219	#endif
	220
6d0f6bcf	221	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
1cb8e980 WD	222	#ifdef CONFIG_AMD_LV800
1cb8e980 WD	223	#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
6d0f6bcf JCPV	224	#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
6d0f6bcf JCPV	225	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
1cb8e980 WD	226	#endif
	227	#ifdef CONFIG_AMD_LV400
	228	#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
6d0f6bcf JCPV	229	#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
6d0f6bcf JCPV	230	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
1cb8e980 WD	231	#endif
	232
	233	/* timeout values are in ticks */
6d0f6bcf JCPV	234	#define CONFIG_SYS_FLASH_ERASE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	235	#define CONFIG_SYS_FLASH_WRITE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Write */
1cb8e980 WD	236
1cb8e980 WD	237	#if 0
5a1aceb0	238	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	239	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
1cb8e980 WD	240	#endif
1cb8e980 WD	241
48b42616	242
6d0f6bcf JCPV	243	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
6d0f6bcf JCPV	244	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
48b42616 WD	245
	246	#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
	247
	248	/*-----------------------------------------------------------------------
	249	* NAND flash settings
	250	*/
a5562901	251	#if defined(CONFIG_CMD_NAND)
48b42616	252
cc4a0cee	253	#define CONFIG_NAND_LEGACY
6d0f6bcf	254	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
48b42616 WD	255	#define SECTORSIZE 512
	256
	257	#define ADDR_COLUMN 1
	258	#define ADDR_PAGE 2
	259	#define ADDR_COLUMN_PAGE 3
	260
53677ef1	261	#define NAND_ChipID_UNKNOWN 0x00
48b42616	262	#define NAND_MAX_FLOORS 1
48b42616 WD	263
	264	#define NAND_WAIT_READY(nand) NF_WaitRB()
	265
	266	#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
	267	#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
	268
	269
	270	#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
	271	#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
	272	#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
	273	#define WRITE_NAND(d, adr) NF_Write(d)
	274	#define READ_NAND(adr) NF_Read()
	275	/* the following functions are NOP's because S3C24X0 handles this in hardware */
	276	#define NAND_CTL_CLRALE(nandptr)
	277	#define NAND_CTL_SETALE(nandptr)
	278	#define NAND_CTL_CLRCLE(nandptr)
	279	#define NAND_CTL_SETCLE(nandptr)
	280
	281	#define CONFIG_MTD_NAND_VERIFY_WRITE 1
	282	#define CONFIG_MTD_NAND_ECC_JFFS2 1
	283
a5562901	284	#endif
1cb8e980 WD	285
1cb8e980 WD	286	#endif /* __CONFIG_H */